JPS62277789A - Manufacture of wiring board - Google Patents

Manufacture of wiring board

Info

Publication number
JPS62277789A
JPS62277789A JP12144986A JP12144986A JPS62277789A JP S62277789 A JPS62277789 A JP S62277789A JP 12144986 A JP12144986 A JP 12144986A JP 12144986 A JP12144986 A JP 12144986A JP S62277789 A JPS62277789 A JP S62277789A
Authority
JP
Japan
Prior art keywords
resist pattern
adhesive film
base material
insulating base
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12144986A
Other languages
Japanese (ja)
Inventor
良明 坪松
直樹 福富
順雄 岩崎
功 塚越
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP12144986A priority Critical patent/JPS62277789A/en
Publication of JPS62277789A publication Critical patent/JPS62277789A/en
Pending legal-status Critical Current

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  • Manufacturing Of Printed Wiring (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 五 発明の詳細な説明 (産業上の利用分野) 本発明は配線板の製造方法に関する。[Detailed description of the invention] V. Detailed description of the invention (Industrial application field) The present invention relates to a method of manufacturing a wiring board.

(従来の技術) 配線板の線巾、線間隔を工LSIの昼集積化に伴いデす
まず細かくなっている。こうした高密度化に対処する微
細パターン形成法として、釦張り積層板または銅箔付き
フィルムの不用部分をエツチングして回路パターンを形
成する方法(fブトラク°ト法)に代り、絶縁基材表面
の必要部分に無電解銅めっき等により回路形成する方法
(アディティブ法)成るいは5〜9μmの銅箔を用いた
銅張り積層板または銅箔付きフィルムをベースに必要部
分にめっきした後ペースの薄い銅箔をクイックエツチン
グする方法(セミアディティブ法)がある。
(Prior Art) The line width and line spacing of wiring boards are rapidly becoming finer as industrial LSIs become increasingly integrated. As a method for forming fine patterns to cope with this increase in density, instead of the method of forming circuit patterns by etching unnecessary parts of button-covered laminates or films with copper foil (f-cutting method), A method of forming circuits on the necessary areas by electroless copper plating (additive method), or using a copper-clad laminate using 5-9 μm copper foil or a film with copper foil as a base, plating the necessary areas and then using a thin paste. There is a method (semi-additive method) of quickly etching copper foil.

(発明が解決しようとする問題点) アディティブ法においては、現状では絶縁基材表面の粗
度が太き(、また無を解銅めっき液の自己分解によって
w1粒子が兵なる場所に析出する所δ11銅つり現象が
あり、サブトラクト法以上の微細パターン形成が容易で
ない。ま1こ、セミアディティブ法においても、Nj4
張り積層板や@箔付きフィルムの製造工程において発生
する銅箔のへこみ及び傷などのため、断線あるいはショ
ートが発生し易い。さらに例nの方法においても、エツ
チングまたはめっぎレジストパターン形成の工程におい
て、フォトマスクの欠陥や露光時のゴミの混入などに帰
因する焼き付は不良の間ypが深刻である。しかもなお
、毎回前記レジストパターン形!E<を行う心安がある
(Problems to be Solved by the Invention) In the additive method, the roughness of the surface of the insulating base material is currently large (and the roughness of the surface of the insulating base material is large, and the roughness of the surface of the insulating base material is large (and the roughness of the non-copper plating solution is large). There is a δ11 copper hanging phenomenon, which makes it difficult to form finer patterns than the subtract method.Also, even in the semi-additive method, Nj4
Due to dents and scratches in the copper foil that occur during the manufacturing process of stretched laminates and foil-covered films, wire breaks or short circuits are likely to occur. Further, in the method of Example n as well, in the process of etching or plating resist pattern formation, the burn-in caused by defects in the photomask or the contamination of dust during exposure has a serious yp during failure. Moreover, the resist pattern shape every time! I feel safe doing E<.

(問題点を解決するための手段) 本発明は次の工程による配勝板の製造方法であろう (1)導電性を有する保持体面に絶縁性を有するレジス
トパターンを形成する。
(Means for Solving the Problems) The present invention is a method for manufacturing a distribution board according to the following steps: (1) forming an insulating resist pattern on a conductive holder surface;

(2)  加熱圧着すると厚さ方向にのみ4電性が得ら
れる接着フィルムを前記レジストパターンが形成さnた
面の全面に加熱圧着する。
(2) An adhesive film that can be heat-pressed to obtain quadrielectricity only in the thickness direction is heat-pressed onto the entire surface on which the resist pattern is formed.

(3)  電気めっきにより、前記レジストパターン以
外の部分に対応する4電パターンを前記接着フィルム上
に形成する。
(3) A four-electrode pattern corresponding to a portion other than the resist pattern is formed on the adhesive film by electroplating.

(4)前記接着フィルムに面して絶縁基材を菫ね合わせ
加熱圧着し前記4蛋性パターン全絶縁基材中に埋め込む
(4) Fold the insulating base materials together facing the adhesive film and heat-press them to embed the four-layer pattern into the entire insulating base material.

(5)前記絶縁基材を前記接着フィルム面より剥離する
(5) Peeling the insulating base material from the adhesive film surface.

次に本発明の実施9IJを図によって説明する。Next, embodiment 9IJ of the present invention will be explained with reference to the drawings.

厚さj m+t+のステンレス板1′t−用意する。そ
の表面をサンドベーパで研摩した後、フォトレジスト(
リストンT−1206)をロールラミネータによってラ
ミネートする。次にフォトマスクを当てて紫外線を照射
した後、現像によつ℃所望す、る部分にレジストパター
ン2を設け、次いで塩化第二鉄(FeC15) 溶0 
(28〜42貞曽%)で前記レジストパターン以外の部
分をエツチングして凹部3を設け、しかる後にnj記レ
ジストパターン2を塩化メチレンで剥離した。前記凹部
3の深さは30〜70μmに調整5T能である。なお、
深さ50〜70μm(1)d囲でエツチングする場せ、
サイドエツチングの影響があるため、フォトマスク設計
時に実際盛装なレジストライン巾より108℃程度広く
設定した方が良い。
A stainless steel plate 1't- with a thickness of j m+t+ is prepared. After polishing the surface with sand vapor, photoresist (
Liston T-1206) is laminated using a roll laminator. Next, after applying a photomask and irradiating with ultraviolet rays, a resist pattern 2 is formed in the desired area by development, and then ferric chloride (FeC15) is dissolved at 0°C.
(28-42 Sadaso%) was used to etch the portions other than the resist pattern to form recesses 3, and then the nj resist pattern 2 was peeled off using methylene chloride. The depth of the recess 3 can be adjusted to 30 to 70 μm by 5T. In addition,
When etching at a depth of 50 to 70 μm (1) d,
Because of the influence of side etching, it is better to set the resist line width to be about 108°C wider than the actual resist line width when designing the photomask.

次に表1に示す紐取の樹脂4を前記凹部5に光填したの
ち150℃、40kg/−て30分間加勢圧着し、再び
サンドベーパで研摩する。この際、光填佃脂4はシート
状にしたものを加熱圧着しても良く、ポリウレタン、ポ
リエステル、シリコーン、フッ素[(gh 、ポリエチ
レン、塩化ビニル樹脂でも良い。また、2度目のkmの
所々はステンレス板1の露出面5が凹部3より深くなら
ないように研摩し、このステンレス板t−マスター基板
6とする。このマスター基板1は、単にステンレス板1
上の所望する部分以外に例えば液状レジストにより厚さ
1へ3μm程度のレジストパターンを形成し1こもので
も、厚さ18へ50μmのフィルム状レジストを使用し
てレジストパターン形成をした佐、電気銅めっきでレジ
スト厚と同じ〕早さのパターンめっきを施したものも使
用町馳である。次に異方尋ゼンィルム7(アニソルム1
052日重化成社製)を150℃、10kg/CMIで
1分間加熱圧着し、こ7″Lをマスター基板l18とす
る。さらに1.6A/U″′c#L酪餉ぬっきを行い、
導体厚10μmの回路パターン9を得た。次に回路パタ
ーン9の全面に酸化銅皮膜10を形成後、接着用プリプ
レグ11と170℃、40kg/afで20分間m、s
圧着した。積層後、絶縁基材11を前記異方尋電フィル
ム7而より剥離して所望する配勝板を得た。この配?f
M板は、線巾、線間隔が80μmの回路パターンを有す
るものである。また、マスター基板16は500回、マ
スター基数l18は100回再利用することかでごろ。
Next, the resin 4 shown in Table 1 was optically filled into the recess 5, and then pressure-bonded at 150 DEG C. and 40 kg/- for 30 minutes, and again polished with a sand vapor. At this time, the light-filled Tsukuda resin 4 may be heat-pressed in the form of a sheet, and may be polyurethane, polyester, silicone, fluorine [(gh), polyethylene, or vinyl chloride resin. The exposed surface 5 of the stainless steel plate 1 is polished so as not to be deeper than the recess 3, and this stainless steel plate t-master substrate 6 is prepared.This master substrate 1 is simply the stainless steel plate 1.
In addition to the desired areas above, for example, a resist pattern with a thickness of 1 to 3 μm is formed using a liquid resist, or a resist pattern is formed using a film resist with a thickness of 18 to 50 μm. Pattern plating with a speed equal to the thickness of the resist may also be used. Next, Anisorum 7 (Anisorum 1)
052 (manufactured by Nikju Kasei Co., Ltd.) for 1 minute at 150°C and 10 kg/CMI, and this 7"L is used as the master board 118.Furthermore, 1.6A/U"'c #L is plated,
A circuit pattern 9 with a conductor thickness of 10 μm was obtained. Next, after forming a copper oxide film 10 on the entire surface of the circuit pattern 9, the adhesive prepreg 11 was applied for 20 minutes at 170° C. and 40 kg/af.
It was crimped. After lamination, the insulating base material 11 was peeled off from the anisotropic thin film 7 to obtain a desired distribution board. This arrangement? f
The M board has a circuit pattern with a line width and line spacing of 80 μm. Also, the master board 16 can be reused 500 times, and the master base number 118 can be reused 100 times.

又、前記ステンレス板1に用いるステンレスに代えて他
の金属板を使用することができる。
Further, instead of the stainless steel used for the stainless steel plate 1, other metal plates can be used.

例えば、ステンレス機上に電気めっきで厚さ50〜80
μm程度の銅めっき層を設けたもの、成るいは厚さjm
+n程度のアルミニウム歓(工尋屯性及び加工1住が優
nている力)も使用できる。
For example, electroplating on a stainless steel machine to a thickness of 50 to 80
With a copper plating layer of about μm, or with a thickness of jm
Aluminum strength of about +n (engineering strength and processing strength is superior) can also be used.

表  1 (発明の効果) 本発明の配線板製造方法におけるマスター基板に丹利用
が可能であるため、工程が短縮できる。
Table 1 (Effects of the Invention) Since the master substrate in the wiring board manufacturing method of the present invention can be made of red, the process can be shortened.

本発明の製造方法は、配線板のMJ密度化に十分対応す
ることができる。
The manufacturing method of the present invention can sufficiently cope with increasing the MJ density of wiring boards.

【図面の簡単な説明】[Brief explanation of drawings]

第1図ta)〜(fJは本発明を説明する断面図である
。 1・・・・・・ステンレス似、2・・・・・・エツチン
グ用レジストパーン、3・・・・・・エツチングe(凹
部)、4・・・・・・凹部光填任(指、5・・・・−・
ステンレス板表面、6・・・・・・マスター基板1,7
・・・・・・異方尋′厖フィルム、8・・・・・・マス
ター、lu、9・・・・・・i6J路パターン、10・
・・・・・敞化銅皮映、11・・・・・・絶線基板。
Figures 1 (ta) to (f) are cross-sectional views for explaining the present invention. 1... Stainless steel-like, 2... Resist pattern for etching, 3... Etching e (Concave), 4...Concave light filler (Finger, 5...--)
Stainless steel plate surface, 6... Master board 1, 7
...Anisotropic film, 8...Master, lu, 9...i6J pattern, 10.
...Copper coating, 11...Disconnected circuit board.

Claims (1)

【特許請求の範囲】 1、次の各工程からなる配線板の製造方法。 (A)導電性を有する保持体面に絶縁性を有するレジス
トパターンを形成する第一工程。 (B)加熱圧着すると厚さ方向にのみ導電性が得られる
接着フィルムを、前記レジストパ ターンを形成した面の全面に加熱圧着する 第二工程。 (C)前記接着フィルム上の前記レジストパターン以外
の部分に、電気めっきによって導 電性パターンを形成する第三工程。 (D)前記接着フィルムに面して絶縁基材を重ね合わせ
て加熱圧着し、前記導電性パター ンを絶縁基材中に埋め込む第四工程。 (E)前記絶縁基材を前記接着フィルム面より剥離する
第五工程。
[Claims] 1. A method for manufacturing a wiring board comprising the following steps. (A) A first step of forming an insulating resist pattern on the conductive holder surface. (B) A second step of heat-pressing an adhesive film that can obtain conductivity only in the thickness direction by heat-pressing onto the entire surface on which the resist pattern is formed. (C) A third step of forming a conductive pattern on a portion of the adhesive film other than the resist pattern by electroplating. (D) A fourth step of stacking an insulating base material facing the adhesive film and heat-pressing it to embed the conductive pattern in the insulating base material. (E) A fifth step of peeling off the insulating base material from the adhesive film surface.
JP12144986A 1986-05-27 1986-05-27 Manufacture of wiring board Pending JPS62277789A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12144986A JPS62277789A (en) 1986-05-27 1986-05-27 Manufacture of wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12144986A JPS62277789A (en) 1986-05-27 1986-05-27 Manufacture of wiring board

Publications (1)

Publication Number Publication Date
JPS62277789A true JPS62277789A (en) 1987-12-02

Family

ID=14811411

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12144986A Pending JPS62277789A (en) 1986-05-27 1986-05-27 Manufacture of wiring board

Country Status (1)

Country Link
JP (1) JPS62277789A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5818564A (en) * 1996-09-13 1998-10-06 Raychem Corporation Assembly including an active matrix liquid crystal display module
US6246459B1 (en) 1998-06-10 2001-06-12 Tyco Electronics Corporation Assembly including an active matrix liquid crystal display module and having plural environmental seals

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5818564A (en) * 1996-09-13 1998-10-06 Raychem Corporation Assembly including an active matrix liquid crystal display module
US6246459B1 (en) 1998-06-10 2001-06-12 Tyco Electronics Corporation Assembly including an active matrix liquid crystal display module and having plural environmental seals

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