JPS59224176A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To make it possible to perform mass production of GaAs elements, whose characteristics are uniform, with good reproducibility, by making it possible to perform substrate heating, and making the film thickness of dug parts uniform. CONSTITUTION:The epitaxial thickness of an operating layer 21 is made uniform. Then, photoresist layers 27 and 28 are removed. A gate-electrode forming part 26 is selectively coated by a photoresist layer 29. Then side etching of the side wall part of an SiO2 film 22 is performed by buffer HF. Thereafter, a metal for forming an operating layer 21 and an ohmic contact is evaporated. Then, the photoresist 29 is removed, and a source electrode 31 and a drain electrode 32 are formed. Then, a photoresist layer 33 is formed again. The exposed operating layer 21 is dug until a specified pinch OFF voltage is obtained. The photoresist layer 33 is removed. Thereafter, a gate electrode is formed in a self- aligning manner with respect to the source and drain electrodes 31 and 32 through the opening part of an SiN film 23 in a recess part. Finally Al 34 is etched, and the SiO2 film 22 is removed by the buffer HF.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a field effect transistor, and more particularly to a method for manufacturing a GaAs Schottky gate type field effect transistor for microwaves using a Schmidtky barrier junction as a gate electrode.
The present invention relates to a method for manufacturing a semiconductor (GaAs MESFET), particularly a self-aligned QaAs ME8FET.

GaAs MESFETs have already been put into practical use as microwave transistors that break through the characteristic limits of St bibulous transistors. Such GaAs MESF
The high frequency characteristics of ET can be improved by shortening the gate length and reducing parasitic resistance.

No, GaAs MESFET for ultra-high frequency of X digits or more
In general, a gate length of 0.5 to 1.0 μm is used. Conventionally, GaAs MESFETs with such short gates have been manufactured by the following method. That is, as shown in FIG. 1(a), semi-insulating GaA
3 n-type GaAs active layer 1 formed on substrate 10
A photoresist 12 having an opening of 0.5 to 1.0 μm per surface is provided, and the required saturation drain current ID5S is
(or pin-off voltage Vp), reduce the source resistance, and facilitate the later lift-off process, after digging the active layer 11 in the opening by chemical etching, the Schottky metal 13 is etched from directly above. After forming the gate electrode 14 by the so-called lift-off method, in which metal is deposited on the entire surface and the photoresist 12 is removed, leaving metal only in the opening, the source electrode 15 and the drain electrode 16 are removed as shown in FIG. 1(b). By depositing and lifting off an ohmic metal in the same way as in Figure 1 (,), p
This is a method to obtain the basic structure of a GaAs MESFET.

However, such conventional methods have the following drawbacks. That is, in the lift-off method, the gate metal must be deposited with the photoresist, which is an organic material, attached, so heating the substrate at a vorticity sufficient to remove the water adhering to the surface of the active layer is sufficient to remove the moisture adhering to the surface of the active layer. This cannot be done because it would cause deformation of the pattern, and impurities still evaporate from the photoresist and contaminate the GaAs surface, making it impossible to obtain good Schottky characteristics with good reproducibility.

In addition, in the method of etching the active layer only by chemical etching, the film thickness at the etched location does not become constant, and the film thickness distribution of the active layer is directly used as the distribution of the saturated drain current ID5S. :1. The disadvantage is that the DBS varies within the plane. Further, in order to provide the saw and drain electrodes 15 and 16 close to the gate electrode 14, mask alignment is required, but misalignment occurs when this mask alignment is performed. This misalignment is highly reproducible, and the direction and thickness vary each time. This misalignment directly affects source resistance and the like, causing variations in high frequency characteristics.

That is, there is a drawback that the characteristics of multiple elements are greatly affected by the alignment accuracy of the mask.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a field effect transistor that can heat the substrate and make the film thickness of the dug portion uniform.

According to the present invention, a first insulating film serving as a spacer and a second insulating film serving as a mask having a slow etching rate are laminated in this order on a semiconductor active layer on a semi-insulating substrate, and then forming a first photoresist layer in which source, drain and gate electrode forming portions are opened;
Using the photoresist layer as a mask, the first and second insulating films were removed by reactive sputter etching, and a second photoresist layer was formed in which the gate electrode formation portion was selectively opened, and the exposed portion was chemically etched. 1st
After side-etching the side wall portion of the insulating film by a predetermined amount, the exposed active layer is anodized and the formed oxide film is removed to provide a recessed portion, After making the active layer thickness uniform and removing the first and second photoresist layers, the gate electrode forming portion is selectively coated with a third photoresist layer)! After side-etching the side wall portion of the first P edge film centered by chemical etching, a metal forming an ohmic contact with the active layer is deposited directly above the third photoresist. By removing the ohmic metal on the third photoresist layer, the ohmic metal on the third photoresist layer is also removed, and then an alloying treatment is performed to form source and drain electrodes with low contact resistance in the source and drain electrode forming portions. After forming a fourth photoresist layer in which the gate electrode forming portion is selectively opened, the dug portion is further etched to a predetermined depth by chemical etching, and the fourth photoresist layer is etched. After the removal, a metal forming the active layer and the Schottky barrier is deposited directly on top of the active layer, so that the gate electrode is connected to the source and drain electrodes through the opening of the second insulating film and into the dug portion. Self ala.

and a step of selectively removing the gate metal and then the first insulating film by chemical etching after covering the dug portion and its vicinity with a fifth photoresist layer. A method for manufacturing a field effect transistor is obtained, characterized in that the method includes:

According to the present invention, since the inorganic anti-resistance film is used as a mask during gate formation, it is possible to heat the substrate to a sufficient temperature before gate metal deposition, and impurities from photoresist as in the conventional method can be heated. Since there is no evaporation or contamination, good Schottky characteristics can be obtained with good reproducibility.The active layer is uniformed by anodic oxidation, and the distance between the source, drain, and gate electrodes is controlled by a mask. Regardless of the alignment accuracy, since it is determined by a single photomask,
Elements with uniform characteristics can be produced with good reproducibility.

Hereinafter, as an example of the present invention, X-band GaAs
A detailed explanation will be given using M E S F E '1' as an example.

FIGS. 2(a) to 2(g) are diagrams for explaining the present invention in detail, and show cross-sectional views of essential parts of the manufacturing process. As shown in FIG. 2(a), first, a semi-insulating GaAs substrate 20
Above is an n-type GaAs active layer 21 (electron concentration n=lQc
m, thickness t'': 0.6 μm) is epitaxially grown, and a CVD5iOz film 22 which becomes a spacer is formed thereon.
Furthermore, plasma CVD serves as a mask when forming gate electrodes.
For example, the 5iN film 23 has a thickness of about 0.4 ttm,
It is formed to a thickness of about 0.3 μm. The 5102 film 22 is formed by a conventional thermal decomposition method using SiH4 and 02 gas at a substrate temperature of 400.degree. On the other hand, when forming the 8iN film 23, buffer HF (HF: 6NH4F
) for the purpose of increasing the etching selectivity with respect to the 5iCh film 22 and providing a mask effect, for example, at a substrate temperature of 350° C., N2. NH3 and SiH4 gases are flowed into the reaction chamber at 70, 6, and 6 SCCM, respectively, and the pressure in the reaction chamber is
Orr XRF power 100W (7) condition test S i N
A film 23 is formed. 54 formed under these conditions
The etching rate of the 0z film 22 and the SiN film 23 with respect to the buffer HF is approximately 6000 A/min, respectively.
.

Approximately 100 A/min, 5iO2JpiiH
The etching speed of '22 is approximately 60 times that of 5iNj@23. Next, a resist (AZ137
After applying 0), the source, drain and gate electrode forming portions 24, 25, 26 are formed by a normal photo process.
For example, the gate electrode forming portion 2 is opened in the photoresist.
The photoresist layer 2 is formed so that the opening width of the photoresist layer 6 is approximately 0.5 to 1.0 μm, and the distance between the source and drain electrode forming portions 24 and 25 and the gate electrode forming portion 26 is approximately 2 μm.
Pattern 7. Next, as shown in FIG. 2 (1)), using the photoresist layer 27 as a mask, CP 4 gas is used or an active spacing method is applied.
v23 O, 1:hi5iOz Membrane 22 wo:ry
fyf to expose the active layer 21. At this time, side etching is hardly performed at X7, so the pattern with the same t1 as the pattern of the photoresist layer 27 is 5iNJ]
123 and 5102 are formed on the film 22. Next, a photoresist layer 28 in which gate electrode forming portions 26 are selectively opened is formed by a normal photo process. At this time, an altered layer containing many fluorine atoms generated during active sputter etching is formed on the surface of the photoresist layer 27.
Since it is insoluble in organic solvents such as butyl acetate and in AZ-based resist developers, the photoresist layer 27 maintains its original pattern as soon as it is deformed. Further, the photoresist layer 28 only needs to cover at least the exposed surface of the active layer 21 in the source and drain electrode forming portions 24 and 25, and the accuracy of mask alignment in this step, that is, the alignment accuracy of the photoresist layer 28, is limited. Not required. Next, the side wall portion of the Sio2 film 22 is etched using buffer HF so that the side wall portion of the Sio2 film 22 is etched, for example, by about 0.5 μm.

At this time, since the etching speed of the SiN film 23 is as slow as about 1/6°, it is hardly etched (up to 80 Å), and the opening width before etching is almost maintained. The gate length of the gate electrode to be formed later is determined by the opening width of this SiN film 23. In addition, by increasing the amount of side etching of the SiO2 film 22, the gate reverse breakdown voltage can be increased, but the output power tends to decrease, so the amount of side etching is determined according to the characteristics required of the device. . Next, under light shielding, the exposed surface of the active layer 21 is anodized in an electrolytic solution consisting of 1 volume of 3-% tartaric acid aqueous solution and 2 volumes of ethylene glycol, and the formed oxide film is removed. By turning the shrimp, the thickness of the working layer 2-1 is made uniform. Anodic oxidation takes advantage of the fact that when the depletion layer formed in the active layer 21 directly under the oxide film reaches the semi-insulating substrate 2° and becomes pinch-off, the growth of the oxide film stops naturally. Therefore, the pinch-off voltage can be made uniform over the entire surface of the wafer, and as a result, the thickness of the strip can be made uniform. Here, the thickness of the active layer 21 is made uniform to about 0.45 μm. Next, after removing the photoresist layers 27 and 28 using a resist stripping agent (J-100), the gate electrode forming portion 26 is selectively covered with a photoresist layer 29 as shown in FIG. 2(C). At this time, the photoresist layer 29 only needs to cover at least the gate electrode forming portion 26, and the mask alignment accuracy in this step is also excellent! ll not required. Next, in order to facilitate the lift-off of the ohmic metal formed later by vapor deposition and the removal of the Si02 film 22 in the final step, SiO
2 The side wall of the membrane 22 is coated with buffer HF to a thickness of, for example, 0.3 μm.
After side etching to a certain extent, a metal for forming an ohmic contact with the active layer 21 is made of, for example, AuGeNi.
/Au30 is evaporated to a thickness of about 0.3 μm from directly above. Next, by removing the photoresist layer 29 with an organic solvent such as acetone, the AuG deposited on the photoresist layer 29 is removed.
After removing the eN i /Au 30 at the same time, heat treatment is performed at 450° C. for about 1 minute in an H 2 gas atmosphere to form a source electrode 31 and a drain electrode 32 with low contact resistance.

Next, as shown in FIG. 2(d), a photoresist layer 33 in which the gate electrode forming portion 26 is selectively opened is again formed. Mask alignment accuracy in this process is also required to be as precise as in the previous process.

Next, the exposed operating layer 21 is further covered with H3PO4:H2O2.
: Using an H20-based etching solution, dig (recess formation) until a predetermined pinch-off voltage (or saturated drain current) is obtained. Here, a predetermined pinch-off voltage (~4V) can be obtained by digging approximately 0.25 μm. Next, after removing the photoresist layer 33, the metal forming the active layer 21 and the Schottky barrier is, for example, At! 34 is deposited approximately 0.5 μm from directly above, the gate electrode 3 is deposited in the recess through the opening of the SiN film 23, as shown in FIG. 2(e).
41 are formed in a self-aligned manner with respect to the source and drain electrodes 31 and 32. At this time, A+! in forming a good Schottky barrier! It is desirable to heat the substrate to about 200° C. before the 34 vapor deposition. Finally, Figure 2 (
As shown in f), the recessed portion and its vicinity are covered with a photoresist 35, the MB2 is etched with a HaPO4 solution, the exposed 5i02 film 22 is removed with a buffer HF, and the photoresist layer 35 is removed. C,
Self-alignment type Ga as shown in Figure 2(g)
The basic structure of AsMESFET is completed.

In the above example, G of the Schottky barrier gate structure is
Although we have talked about aAs field effect transistors, Ga
Of course, the present invention can also be applied to field effect transistors using semiconductors other than AS.

As described above, GaAsME8 according to the present invention
Using the FET manufacturing method, the inorganic 8iN film serves as a mask during gate formation, making it possible to heat the substrate to a sufficient temperature before depositing the gate metal, and eliminating impurities from photoresist as in conventional methods. evaporation, contamination, etc.
In addition to achieving good Schottky characteristics with good reproducibility, the active layer is made uniform by anodic oxidation, and the distance between the source, drain, and gate electrodes is approximately 1, regardless of mask alignment accuracy. Because the process is determined using a single photomask, it has become difficult to mass-produce elements with uniform characteristics with good reproducibility.

[Brief explanation of the drawing]

Figures 1(a) and 1(b) show conventional GaAs MESFETs.
Diagrams for explaining the manufacturing method, Figures 2 (a) to (b)
) is a diagram for explaining one embodiment of the present invention, and is a cross section of a main part of an element in main steps. In the figure, 10... semi-insulating substrate, 11...
...Active layer, 12...Photoresist, 13
... Schottky metal, 14 ... Gate electrode, 15 ... Source electrode, 16 ... Drain electrode, 20 ... Semi-insulating G a A s substrate, 21...n-type GaAS active operation layer, 22.
...8i02 film, 23...SiN film, 2
4, 25.26...□Respectively source, drain, gate a-pole forming portions, 27.28, 29, 33.3
5...Photoresist layer, 3 Q...A
uGeNi/Au, 31--source electrode, 3
2...Drain electrode, 34...AM,
341... Indicates a gate electrode. Agent Patent Attorney Shinto Hara 10 ti porridge zrm

Claims (2)

[Claims] (1) A first insulating film is provided on the semiconductor active layer, a second insulating film having a slower etching rate than the first insulating film is formed thereon, and the first and second insulating films are selected. After removing the semiconductor layer, the semiconductor active layer in the gate electrode formation portion is exposed.
A method for manufacturing a field effect transistor, characterized in that a recess is provided in the gate electrode forming portion by anodizing and digging the recess, and a gate electrode is formed in the recess. (2) The method for manufacturing a field effect transistor according to claim 1, wherein the first insulating film is a CVD8i0z film, and the second insulating film is a plasma CVD81N film.