JPS59224153A - 半導体装置の製造法 - Google Patents

半導体装置の製造法

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Publication number
JPS59224153A
JPS59224153A JP58097803A JP9780383A JPS59224153A JP S59224153 A JPS59224153 A JP S59224153A JP 58097803 A JP58097803 A JP 58097803A JP 9780383 A JP9780383 A JP 9780383A JP S59224153 A JPS59224153 A JP S59224153A
Authority
JP
Japan
Prior art keywords
wafer
substrate
wire
semiconductor device
stage
Prior art date
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Pending
Application number
JP58097803A
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English (en)
Inventor
Takeshi Sugimura
杉村　毅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58097803A priority Critical patent/JPS59224153A/ja
Publication of JPS59224153A publication Critical patent/JPS59224153A/ja
Pending legal-status Critical Current

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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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  • Physics & Mathematics (AREA)
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔技術分野〕 本発明は半導体装置の製造法に関【７１％に組立工程で
の金属線（ワイヤ）による短絡防止技術に関する。
〔背景技術〕
トランジスタやＩＣ等の半導体装置を製造するにあたっ
ては、ウエノ・状態の半導体（シリコン）基体表面に酸
化、ホトエツチング、選択的不純物拡散及び電極金員蒸
着等の諸工程を繰り返すことによって同一仕様の複数の
素子領域を形成【７．この素子の配列にそってウエノ・
を縦横に切断（スクライブ又はダイシング）することに
よって個々に素子を含むペレットに分離する。この後複
数のリードを一体化したリードフレーム上にぺＶットと
なった半導体基体を接続（ぺＶットボンディング）［２
，素子表面の電極とリードとの間をワイヤと称する金、
（又はアルミニウム）線で接続（ワイヤボンディング）
［７，然る後、樹脂成形体により封止［７，外部に突出
するリードの連続部分を切り離して半導体装置を完成す
る。
ところで、ウェハ段階で半導体基体に素子領域表面を保
護するために厚い絶縁膜からなる表面保護膜（パッシベ
イシ日ン）を形成するがこれまでは素子と素子との境界
部はスクライプエリヤと（。
て表面保護膜を部分的にエッチ【７て取り除き基板衣、
面を露出していた。この表面保護膜の部分的工ッチはス
クライブエリヤの位置を見やす（するためとｌ！ｉｔい
保護膜を取り除いた方が半導体基体へのスクライブ溝を
形成しやすいために行うものである。
この後ペレット段階で調子表面の電極リードとの接続を
行う際に下記の問題を生じる。
第１図はワイヤボンディング時の半導体装置の形態を拡
大断面図であられし、たものである。１はペレット段階
のシリコン甲導体基体、２は表面保護膜、３はシリコン
基体の取り付けられたリードフレーム（タブ）、４はリ
ードである。５はワイヤ（金線又はアルミニウム線）シ
リコン基体表面の端子電極（パッド）６からリード４０
間にワイヤボンディングにより接続される。同図に示す
ようにワイヤは５はボンディング時又はボンディング後
にパッド６とリード４との間で下へ垂れ下がりやすく、
その吟に基体表面の露出するスクライブエリヤ特に基板
肩部７に接触すると、短絡を生・しる。このようなワイ
ヤと基体との接触による短絡は半導体装置の致命的な不
良となり、委留りを低下させ、製品の品質保証に支障を
来た丁ことになった。
〔発明の目的〕
本発明は半導体装置におけるワイヤと基体との接触によ
る短絡不良を防止する製造法の提供を目的とする。
〔発明のａ要〕
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば下記のとおりである。
すなわち、ウェハ段階で素子領域を形成［７，ベレット
段階でワイヤボンディングを行う半導体装置の製造法に
おいて、ウェハ段階で素子領域の表面に形成する保護絶
縁膜と素子の境界部表面に存在させた状態でウェハを切
断することにより、ペレット段階でも半導体基体周縁上
に保護絶縁膜を確保し、ワイヤと基体との接触による短
絡不良を防止するものである。
〔実施例〕
第２図〜第５図は本発明の実施例であって、半導体装置
の製造プロセスのうちウェハ段階からペレット切断・組
立段階を１轢断面図により示すものである。
（１）ウェハ状の３ｉ（シリコン）基体１０表面に選択
的拡散により素子領域８を形成し、各拡散領域（ベース
・エミッタ）にコンタクトする八！（アルミニウム）電
１ｉＩｌ１６を形成後、全面にＣＶＤ（気相化学析出）
法によるＳｉＯ，、ＰＳＧ（リンを宮むシリカ糸ガラス
）又はポリイミド系樹脂等からなる表面保護膜２を厚く
形成［７，端子部（パッド）６を露出てるようにホトエ
ッチする。これまではこのホトエッチの際に同時にスク
ライプエリヤＩＡをエッチ（２ていたか１本発明の場合
はこの部分は表面保護膜２で覆ったままとする（第２図
）。
（２）スクライブエリヤＩＡに対（２，グレード９によ
るダイシング加工による切断ケ行い、ウェハを鎖側に素
子を言むペレットｌａ、ｌｂ・・・・・・に分離する←
第３図）。
（３ｒ　　ぺｖットとなった栖体なリードフレームのタ
ブ３上に金・シリコン共°品合金層を介【７で接続（ペ
レットボン、ディング）シ、ワイヤボンダ１０を用いて
基体表面のパッド６とリード４との間をワイヤ５により
接続（ワイヤボンディング）ｆる（第４図）。
第５図はワイヤボンディング後の半導体装置の形態を示
す。この後、図示されないが、樹脂成形体により全体を
封止［２半導体装置を完成する。
〔効　果〕
以上実施例で述べた本発明によれば下記のように効果が
得られる。
ｉｌｌ　　スクライブエリヤの上を表面保護膜で覆って
あってもボンディングバンドやスクライプエリヤ上の一
部に表面保護膜にあけた窓開部を基準とすることにより
スクライブエリヤの位置を決定することができる。
（２）　　ウェハ切断にダイシング加工を採用すること
により表面保護膜を通してシリコン基板を正確に切断す
ることが可能である。
（３（スクライブエリヤの表面は厚い保護膜で絶縁され
ているため、金線が接触しても短絡不良とならず、迩別
少留りが向上する。
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが本発明は上記実施例に限定されるも
のではな（、その要旨を逸脱し７ない範囲で柚々変史で
きる。
〔利用分野〕
本発明はワイヤボンディングにより宝雌イ導出を行う樹
脂モールド形牛導体装置のすべてに適用できる。
本発明はリード数の多いＩＣに適用して有効であるが、
単体のトランジスタに１心用（７ても可能である。
【図面の簡単な説明】
第１図はこれまでの半導体装置にＢいてワイヤ短節不良
の例を示す断面図である。 第２図〜第５図は本発明による実施例であって、半導体
装置のウェハ段階からベレット段階での組立工程を示す
工程断面図である。 工・・・半導体基体、２・・・表面保設膜、３・・・リ
ードフレーム（タブ）、４・・・リード、５・・・ワイ
ヤ、６・・・１勧、７・・・基板肩部、８・・・素子領
域。 代理人　弁理士　　高　橋　明　失 策　　１　　図 第　　５　　図 − 「 第　　３　　図 − ／Ｌ：Ｌ 第　　４　　図

Claims (1)

  1. 【特許請求の範囲】 １、半導体基体表面にウェハの段階で複数の同一仕様の
    素子領域を形成し、素子の配列にそってウェハを縦横方
    向に切断【２て餉々の素子をさむペレットに分離した後
    、支持基板上にペレットヒなった半導体基体を接続し、
    素子よりの金属線による１ｕｉｉ取り出し後素子を樹脂
    成形体で封止する半導体装置の製造法であって、ウェハ
    段階の基体上で素子領域の表面に形成する保護絶縁膜を
    素子と素子との境界部表面に存在させた状態でウェハを
    切断することを特徴とする半導体装置の製造法。
JP58097803A 1983-06-03 1983-06-03 半導体装置の製造法 Pending JPS59224153A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58097803A JPS59224153A (ja) 1983-06-03 1983-06-03 半導体装置の製造法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58097803A JPS59224153A (ja) 1983-06-03 1983-06-03 半導体装置の製造法

Publications (1)

Publication Number Publication Date
JPS59224153A true JPS59224153A (ja) 1984-12-17

Family

ID=14201936

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58097803A Pending JPS59224153A (ja) 1983-06-03 1983-06-03 半導体装置の製造法

Country Status (1)

Country Link
JP (1) JPS59224153A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6230343A (ja) * 1985-07-31 1987-02-09 Nec Corp 半導体装置
JP2008187109A (ja) * 2007-01-31 2008-08-14 Toshiba Corp 積層型半導体装置とその製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6230343A (ja) * 1985-07-31 1987-02-09 Nec Corp 半導体装置
JP2008187109A (ja) * 2007-01-31 2008-08-14 Toshiba Corp 積層型半導体装置とその製造方法
US8039970B2 (en) 2007-01-31 2011-10-18 Kabushiki Kaisha Toshiba Stacked semiconductor device and method of manufacturing the same

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