JPS59219962A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59219962A
JPS59219962A JP58093768A JP9376883A JPS59219962A JP S59219962 A JPS59219962 A JP S59219962A JP 58093768 A JP58093768 A JP 58093768A JP 9376883 A JP9376883 A JP 9376883A JP S59219962 A JPS59219962 A JP S59219962A
Authority
JP
Japan
Prior art keywords
contact
electrode plate
electrode
contact electrode
plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58093768A
Other languages
Japanese (ja)
Inventor
Katsuhiro Endo
遠藤 勝弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Corporate Research and Development Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Corporate Research and Development Ltd filed Critical Fuji Electric Corporate Research and Development Ltd
Priority to JP58093768A priority Critical patent/JPS59219962A/en
Publication of JPS59219962A publication Critical patent/JPS59219962A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/051Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Thyristors (AREA)

Abstract

PURPOSE:To prevent a short circuit between a gate electrode and a cathode electrode and the positional displacement of a semiconductor element by fixing a contact electrode plate, to which an escaping section, such as a groove or a through-hole or the like is formed, to the element. CONSTITUTION:The escaping section 20 of a groove, which is slightly larger than a gate electrode 2 and has a shape of the same contour as the gate electrode 2, is formed at a position opposite to the gate electrode 2 of a contact electrode plate 6, and a pin 21 fitted to a conductive electrode 8 shaping one part of a vessel and the contact electrode plate 6 and a pin 22 inserted to a conductive electrode 16 and a semiconductor support plate 5 are mounted. The contact electrode plate and a semiconductor element can continuously keep the predetermined relationship of relative positions, through which a short circuit is not generated, accurately, and the stable state of operation is obtained at all times.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は、例えば高速サイリスクなどのように、複雑な
形状のゲートTt極を備えた半導体装置の組立構造に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to an assembly structure of a semiconductor device having a complex-shaped gate Tt pole, such as a high-speed silice.

〔従来技術とその問題点〕[Prior art and its problems]

第1図は高速サイリスク素子の表面形状を表わす平面図
であり、第2図は第1図のA−A拡大断面図を示しであ
る。第1図、第2図において、半導体基板1は主表面に
複?f8な形状のゲート電極2と、カソード電極3を備
えており、このような高速サイリスタ素子が正常な動作
を維持するために、ゲート電極2とカソード電極3とが
永続的に短絡することがないよう、両電極はそれぞれ分
離して配置されるのが普通である。4は第1段のゲート
電極である。
FIG. 1 is a plan view showing the surface shape of the high-speed silice element, and FIG. 2 is an enlarged cross-sectional view taken along the line AA in FIG. 1. In FIGS. 1 and 2, a semiconductor substrate 1 has multiple layers on its main surface. It is equipped with a gate electrode 2 having an f8 shape and a cathode electrode 3, and in order for such a high-speed thyristor element to maintain normal operation, the gate electrode 2 and cathode electrode 3 are not permanently short-circuited. Therefore, both electrodes are usually placed separately. 4 is a first stage gate electrode.

このような半導体基板を有する半導体素子を容器に封入
した平型高速サイリスク装置の断面図を第3図に示すが
第1図、第2図と同一符号は同一名称を表わしている。
FIG. 3 shows a sectional view of a flat type high-speed SIRIS device in which a semiconductor element having such a semiconductor substrate is sealed in a container, and the same reference numerals as in FIGS. 1 and 2 represent the same names.

第3図に示すように、半導体基板1はモリブデンオたは
タングステンからなる支持板5に固着されて半導体素子
を構成し、半導体基板1のカソード電極3の上には、平
滑な面をもった導電性金属、例えばモリブデンなどから
なる接触電極板6が当接される。ゲート電極2とカソー
ド電@3とが電気的に短終を生じない配置とする手段は
、第2図または第3図かられかるが、例えばシリコン基
板1の主表面が凹凸面をもつように、薬品などを用いて
エツチング加工により段差を形成し、シリコン基板1の
四部にアルミ蒸着膜からなるゲート電極2さ、シリコン
基板1の最外主表面に同じくアルミ蒸着膜からなるカソ
ード電極3を設けることにより行われる。このようにシ
リコン基板1の主表面に設けた凹凸面の高低差により、
ゲート電極2は接触電極板6との間に空間絶縁部が生じ
、ゲート電極2は接触電極板6に当接しているカソード
電極3と宵気的絶縁状態が保たれているのである。
As shown in FIG. 3, a semiconductor substrate 1 is fixed to a support plate 5 made of molybdenum or tungsten to constitute a semiconductor element, and a cathode electrode 3 on the semiconductor substrate 1 has a smooth surface. A contact electrode plate 6 made of a conductive metal such as molybdenum is brought into contact. As shown in FIGS. 2 and 3, means for arranging the gate electrode 2 and the cathode electrode 3 so as not to cause an electrical short termination can be seen in FIGS. 2 and 3, for example, by making the main surface of the silicon substrate 1 have an uneven surface. Steps are formed by etching using chemicals or the like, and gate electrodes 2 made of an aluminum vapor deposited film are provided on the four parts of the silicon substrate 1, and cathode electrodes 3 made of an aluminum vapor deposited film are provided on the outermost main surface of the silicon substrate 1. This is done by Due to the height difference between the uneven surfaces provided on the main surface of the silicon substrate 1 in this way,
A spatial insulation portion is formed between the gate electrode 2 and the contact electrode plate 6, and the gate electrode 2 is kept in a state of insulation from the cathode electrode 3 which is in contact with the contact electrode plate 6.

第3゛図の平型半導体装置の組立手順を説明すると、先
づフランジ7を介してろう接された電極8と絶縁環9と
からなる容器に、ばね部材10と絶縁部材11とともに
、これらを通したゲートリード糾12を先端がシリコン
基板1の第1段ゲート電極4に当接されるべき個所に載
置し、ゲートリード悲)12の他端は絶縁環9を貫通す
る管13に差込み、管13とともに端末でつぶし一体に
封止する。次に例えはテフロン製のスペースリング14
を容器に挿入するが、スペースリング14には、リード
線12と交差する個所に切込みを入れてリード線12が
邪廠にならないようにしである。しかる後、接触電極板
6と前もって第2図のように主表面が凹凸加工されたシ
リコン基板1と支持板5からなる半導体素子を第3図の
ごとく配設し、最後に容器の盆となるフランジ15を有
する電極16を半4体素子の上にV(き、このフランジ
15と絶縁環9に設けたフランジ17とを容器の全周で
へりアーク溶接してこの平型半導体装置の組立てが完了
する。
To explain the assembly procedure of the flat semiconductor device in FIG. The passed gate lead wire 12 is placed on the silicon substrate 1 at a location where its tip should come into contact with the first stage gate electrode 4, and the other end of the gate lead wire 12 is inserted into the tube 13 passing through the insulating ring 9. , and the tube 13 is crushed at the end and sealed integrally. Next, the example is Teflon space ring 14.
is inserted into the container, but a notch is made in the space ring 14 at the point where it intersects with the lead wire 12 to prevent the lead wire 12 from becoming a wire. Thereafter, a semiconductor element consisting of a contact electrode plate 6, a silicon substrate 1 whose main surface has been roughened in advance as shown in FIG. 2, and a support plate 5 is arranged as shown in FIG. 3, and finally a container tray is formed. An electrode 16 having a flange 15 is placed on top of the semi-quartet element, and this flange 15 and a flange 17 provided on the insulating ring 9 are edge arc welded around the entire circumference of the container to assemble this flat semiconductor device. Complete.

しかしながら、このような構造をとっているためlこ、
この平型半導体装置には次のような欠点が避けられない
However, since it has such a structure,
This flat semiconductor device inevitably has the following drawbacks.

その一つはシリコン基板1の主表面上に形成される凹部
の深さ寸法を0.02±0.01mに制御しなければな
らないという加工上の困駈さを伴うことである。第4図
は第1図〜第3図の符号にしたがって、主表面が凹凸加
工されたシリコン基板1のゲート電極2とカソード′電
極3、および接触電極板6との関係を示した拡大断面図
であるが、例えはシリコン基板1の主表面の凹部の加工
深さが規定寸法より浅すぎた場合には、第4図に示すよ
うにゲート電極2にフォトマスクの精度の悪さに起因し
て突起部18が生じ、この突起部18が接% 31極板
6に接触してし才うことかあり、その結果ゲート電極2
とカソード電極3との電気的な短絡を招く。また第5図
は第4図と同様な断面図を示したものであるが、この場
合は例えばシリコン基板1の主表面に設けた凹部に、製
造過程中に金属微粒子などの異物19が混入したために
、この導電性をもった異物19を介して、ゲート電極2
と接触電極板6が接触することにより、ゲート・カソー
ド両電極間が短絡することを表わしている。
One of them is that the depth of the recess formed on the main surface of the silicon substrate 1 must be controlled to 0.02±0.01 m, which is difficult to process. FIG. 4 is an enlarged sectional view showing the relationship between the gate electrode 2, the cathode' electrode 3, and the contact electrode plate 6 of the silicon substrate 1 whose main surface is roughened according to the symbols in FIGS. 1 to 3. However, for example, if the processing depth of the recess on the main surface of the silicon substrate 1 is too shallow than the specified dimension, the gate electrode 2 may be damaged due to poor precision of the photomask, as shown in FIG. A protrusion 18 is formed, and this protrusion 18 comes into contact with the contact plate 6, and as a result, the gate electrode 2
This results in an electrical short circuit between the electrode 3 and the cathode electrode 3. Further, FIG. 5 shows a cross-sectional view similar to FIG. 4, but in this case, for example, foreign matter 19 such as metal particles got into the recess provided on the main surface of the silicon substrate 1 during the manufacturing process. Then, the gate electrode 2 is connected via this conductive foreign material 19.
This indicates that the contact electrode plate 6 comes into contact with the contact electrode plate 6, causing a short circuit between the gate and cathode electrodes.

欠点の第二は第3図の平型サイリスタの構造では、半導
体素子が容器に収容された後にはじめて接触電極板6が
加圧接触されるものであり、半導体素子も接触電極板6
も常時拘束されているわけではないから、平型サイリス
クは、取扱い中に容器に封入されている半導体素子が回
転などが原因で第5図に示したように異物が混入したと
き、カソード電極を損傷するおそれがあることである。
The second drawback is that in the structure of the flat thyristor shown in FIG. 3, the contact electrode plate 6 is brought into pressure contact only after the semiconductor element is housed in the container, and the semiconductor element is also pressed against the contact electrode plate 6.
Since the electrodes are not always restrained, the cathode electrode of the flat type SIRISK can be removed if foreign matter gets mixed in due to rotation of the semiconductor element sealed in the container during handling, as shown in Figure 5. There is a risk of damage.

〔発明の目的〕[Purpose of the invention]

本発明の目的は上述の欠点を除去し、ゲート電極とカソ
ード■も極が接触型4夕板を介して短絡を生ずることな
く、かつ半導体素子の位置ずれを防止した半導体装置を
提供することにある。
An object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a semiconductor device in which the gate electrode and the cathode do not cause short circuits through the contact-type quarter plate, and also prevent misalignment of the semiconductor element. be.

〔発明の要点〕[Key points of the invention]

本発明は溝または貫通孔などの逃げ部を設けた接触電極
板を半導体素子に同定したti’¥造の半導体装置であ
る。
The present invention is a manufactured semiconductor device in which a contact electrode plate provided with a relief portion such as a groove or a through hole is identified as a semiconductor element.

〔発明の実施例〕[Embodiments of the invention]

以下本発明を実施例に基づき説明する。 The present invention will be explained below based on examples.

第6図は本発明による平y5+H、B速すイリスク装置
の断面図を示す。第6図において、第1図〜第5図と同
一符号は同一名称を表わしている。第6図が第3図と異
る点は、シリコン基板1の主表面に凹凸加工を施すこと
なく、ゲート電極2と接触電極板6とが簡接接慰するの
を防ぐため、接触電極板6のゲート電極2と対向する個
所に、ゲート’rlT極2よりやや太きい同じ翰郭の形
状を有する溝の逃げ部20を設けであることと、容器の
一部を形成する導電電析8と接触電極板6とに嵌合され
るピン21および同じく導電電(ぺ如4と半導体支持板
5にはめ込まれるピン22を備えていることである。
FIG. 6 shows a cross-sectional view of a flat y5+H,B speed iris device according to the present invention. In FIG. 6, the same reference numerals as in FIGS. 1 to 5 represent the same names. The difference between FIG. 6 and FIG. 3 is that the main surface of the silicon substrate 1 is not roughened, and the contact electrode plate 6 is designed to prevent the gate electrode 2 and the contact electrode plate 6 from coming into contact with each other easily. A groove escape part 20 having the same outline shape and slightly thicker than the gate 'rlT electrode 2 is provided at a location facing the gate electrode 2 of the conductive electrode 8 forming a part of the container. A pin 21 is fitted into the contact electrode plate 6 and a pin 22 is fitted into the conductive plate 4 and the semiconductor support plate 5.

第6図に示した平型高速サイリスクのA4立手順は次の
通りである。先ず容器にばね部材10と絶縁部材11と
ともに、ゲートリード線12を′l′¥′13に取付け
るまでは第3図の場合と全く同様である。
The A4 installation procedure for the flat high-speed cyrisk shown in Figure 6 is as follows. The process is exactly the same as that shown in FIG. 3 until first, the spring member 10 and the insulating member 11 are attached to the container, as well as the gate lead wire 12 to 'l'\'13.

本実施例では続いてシリコン基)IFj、1の主表面の
ケ−ト’t7f 庫2に対向する個所に、溝加工を施し
た逃げ部20をイ硲えた接片1濁屯板6と、半導体素子
とを正しく位置合わせし7た才ま、スペースリング14
を圧入することにより、半2ノγ体素子および接触電極
板6の仰!面でこの両者を固定し、一体となったものを
容器に挿入する。その際、電4夕8にピン21を埋め込
んでおき、このピン21と、接触電極板6に設けられた
ピン孔とを合わせると同時に、スペースリング14の切
欠き部と、先に取付けであるゲート11−ド線12を位
置合わせしながら行なう。最後に半導体支持板5にピン
22を差込み、このピン22に、フランジ15を有する
電極16に設けられたピン孔を合わせて電極16をかぶ
せ、フランジ15と絶蒜倶9のフランジ17とを、全周
でへりアーク溶接することによって、本実施例の平型高
速サイリスク装置、fの組立てが終る。
In this embodiment, the contact piece 1 has a grooved relief part 20 formed on the main surface of the silicon base IFj, 1 at a location facing the cage 2; After 7 years of correct alignment with the semiconductor element, Space Ring 14
By press-fitting the half-two gamma body elements and the contact electrode plate 6, Fix the two together using a surface, and insert the combined product into a container. At that time, a pin 21 is embedded in the electrode 4 8, and at the same time, the pin 21 is aligned with the pin hole provided in the contact electrode plate 6, and the notch of the space ring 14 and the mounting are first made. This is done while aligning the gates 11 and 12. Finally, insert the pin 22 into the semiconductor support plate 5, align the pin hole provided in the electrode 16 with the flange 15 with the pin 22, cover the electrode 16, and connect the flange 15 and the flange 17 of the Zettai Garlic 9. By performing edge arc welding around the entire circumference, the assembly of the flat type high-speed silisk device f of this embodiment is completed.

第7図は異る実加;例を示したものであるが、半導体素
子と接触正(塗板の措成のみを図示しである。
FIG. 7 shows a different example; only the structure of the semiconductor element and the contact plate (coated plate) is shown.

第1図〜第6図と同一番号を同一名称で表わす。The same numbers as in FIGS. 1 to 6 are represented by the same names.

第7図では、接触電極板6のゲート電極2と対向する位
置に、カソード電極3との短絡を防ぐための逃げ部20
として溝を設けるかわりに貫通孔とし、接触電極板6と
半導体素子との固定は、ピンを用いずに接触電極板6の
側面と半導体素子の外縁部で、例えばシリコーンゴム2
3などにより固着し、一体としたものである。
In FIG. 7, a relief portion 20 is provided at a position facing the gate electrode 2 of the contact electrode plate 6 to prevent a short circuit with the cathode electrode 3.
Instead of providing a groove, a through hole is used, and the contact electrode plate 6 and the semiconductor element are fixed by using silicone rubber 2, for example, on the side surface of the contact electrode plate 6 and the outer edge of the semiconductor element, without using pins.
3, etc., to make it a single piece.

第8図も同じく半導体素子と接触電極板のオh成のみを
示したものであり、この場合も接か電極板6の逃げ部2
0は貫通孔としであるが、第7図と異る所は、接触電欄
板6と半導体素子との固定は、この両者の接合面にろう
材24によりろう接により固着していることであるが、
ろう材の代りにり:I4などの圧接材を用いて、圧接に
より固着してもよい。
Similarly, FIG. 8 also shows only the configuration of the semiconductor element and the contact electrode plate, and in this case, the relief part 2 of the contact electrode plate 6 is also shown.
0 is a through hole, but the difference from FIG. 7 is that the contact field board 6 and the semiconductor element are fixed by brazing with a brazing material 24 on the joint surface of the two. Yes, but
Instead of brazing filler metal: A pressure welding material such as I4 may be used to secure the parts by pressure welding.

なお第7図、第8図において、逃げ部20は貫通孔とせ
ずに第6図に示したように溝状としてもよいことは勿論
である。才た第7図、第8図の半導体素子の容器への封
入組立ては第3図または第6図について説明した手il
(’iに従って行えばよいが固定ピンの使用は必要とし
ない。
In addition, in FIGS. 7 and 8, it goes without saying that the relief portion 20 may be formed into a groove shape as shown in FIG. 6 instead of being a through hole. The assembly of the semiconductor device shown in FIG. 7 and FIG.
(You can follow 'i, but it is not necessary to use a fixing pin.

〔発明の効果〕〔Effect of the invention〕

以上説明したごとく、本発明によればシリコン基板の主
表面に、極めて手数のかかる面倒なしかも深さの制御が
困難な凹部を設けて、ゲート電極を配置する必要がなく
なり、ゲート、カソード両電極間の短絡が発生すること
なく、長期間にわたって半導体装置を安定に運転するこ
とができる。
As explained above, according to the present invention, it is no longer necessary to provide a recess on the main surface of a silicon substrate, which is extremely time-consuming and troublesome, and whose depth is difficult to control, and to arrange a gate electrode. The semiconductor device can be operated stably for a long period of time without short circuits occurring between the semiconductor devices.

このような効果が得られるのは、ゲート電極と対向する
位置で接触電極板に、ゲート、カソード両電極間の短絡
防止のための逃げ部を設けてあり、ゲート電極と接触電
極板の位置関係が正しく整合しているからであって、こ
の相対位(H,関係がなんらかの理由で維持できなくな
った場合は、再び短゛絡の問題が生ずる。この原因とな
る最も起こりやすい現象は、封入組立後の取扱い中の接
触電極板と半導体素子の回転であるが、これに対して本
発明の装置では、ピンまたは固定胴などを用いて、接触
電極板と半導体素子が一体となるように固定しであるか
ら、いかなる場合にもこれらが単独に回転することは起
こり得ない。すなわち、接触電極板と半導体素子は短路
を生ずることのない一定の相対位置関係を、正確に保ち
続けることができるので、この半導体装置は常に安定な
運転状態が得られるのである。
This effect is achieved because the contact electrode plate is provided with a relief part at a position facing the gate electrode to prevent short circuits between the gate and cathode electrodes, and the positional relationship between the gate electrode and the contact electrode plate is If the relative position (H) cannot be maintained for some reason, the problem of short circuit will occur again.The most likely cause of this problem is In contrast to the rotation of the contact electrode plate and the semiconductor element during subsequent handling, in the apparatus of the present invention, the contact electrode plate and the semiconductor element are fixed together using a pin or a fixing body. Therefore, it is impossible for these to rotate independently in any case.In other words, the contact electrode plate and the semiconductor element can accurately maintain a constant relative positional relationship that does not cause short circuits. , this semiconductor device can always be in a stable operating state.

一方半導体素子の回転防止のためには、接触電極板をか
なり厚くするか、別に補強板などを設けて、重量効果を
期待することもできるが、材料費が増大するばかりでな
く、特性の面からも電気的。
On the other hand, in order to prevent the semiconductor element from rotating, it is possible to make the contact electrode plate considerably thicker or to provide a separate reinforcing plate in order to achieve a weight effect, but this not only increases the material cost but also reduces the characteristics. Also electrical.

熱的な抵抗が増加するなどの連動り:をもたらすのに対
して、本発明における接触ε、電極板0.1〜1咽程度
の厚さで有効に目的を果すことができる。
In contrast, in the present invention, the contact ε and the electrode plate thickness of about 0.1 to 1 mm can effectively achieve the purpose.

以上のように、本発明の半導体装置は、電気的な素子の
短絡と、取扱い中の素子の回転という問題を一挙に解決
したものであり、特に平型半導体装置とした場合に大き
な効果か得られる。
As described above, the semiconductor device of the present invention solves the problems of short-circuiting of electrical elements and rotation of elements during handling, and has great effects especially when used as a flat semiconductor device. It will be done.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は高速ザイリスタ素子の電極配置を示す平面図、
第2図は同じく拡大部分断面図、143図は従来の平型
半導体装置の断面図、第4図、第5図は電極のり絡状態
を示す拡大部分断面図、第6図は本発明による平型半導
体装置の断面図、第7図、第8図は第6図と異る実施例
の半導体素子と接触電析板との固定を示した拡大部分断
面図である。 1・・・シリコン基板、2・・・ゲート型1極、3・・
・カソード電極、5・・・支持板、6・・・接結電極板
、20・・・逃げ部、21.22・・・ピン、23・・
・絶縁材、24・・・ろう材。 第1図 第2図 第3図 第4図 @5図
Figure 1 is a plan view showing the electrode arrangement of a high-speed Zyristor element;
2 is an enlarged partial sectional view, FIG. 143 is a sectional view of a conventional flat semiconductor device, FIGS. 4 and 5 are enlarged partial sectional views showing the state of intertwining of electrodes, and FIG. 7 and 8 are enlarged partial sectional views showing fixing of a semiconductor element and a contact electrodeposition plate in an embodiment different from that shown in FIG. 6. 1...Silicon substrate, 2...Gate type single pole, 3...
- Cathode electrode, 5... Support plate, 6... Connection electrode plate, 20... Relief part, 21.22... Pin, 23...
- Insulating material, 24... brazing material. Figure 1 Figure 2 Figure 3 Figure 4 @Figure 5

Claims (1)

【特許請求の範囲】 1)半導体基板の主表面に、接触電極板と接続される第
一の電極層と、前記接触電極板と接続されない第二の電
極層を有するものにおいて、接触電極板は、前記第一の
電極層と接触する接触面と。 前記第二の電極層と対向する個所に設けられ前記第二の
電極層よりやや大きい輪郭を有する前記接触面からの逃
げ部とを備え、前記半導体基板に対する相対位置が固定
されたことを特徴とする半導体装置。 2、特許請求の範囲第1項記載の装置において、半導体
素子および接触電極板がそれぞれピンにより容器に固定
されたことによって、相対位置が固定されたことを特徴
とする半導体装置。 3)特許請求の範囲第1項記載の装置において、半導体
素子および接触電極板が互に絶縁材により固着されたこ
とによって、相対位置が固定されたことを特徴とする半
導体装置。 4)特許請求の範囲第1項記載の装置において、半導体
素子および接触電極板が互にろう接または圧接により固
着されたことによって相対位置が固定されたことを特徴
とする半導体装置。
[Claims] 1) In a semiconductor substrate having a first electrode layer connected to a contact electrode plate and a second electrode layer not connected to the contact electrode plate on the main surface of the semiconductor substrate, the contact electrode plate is , a contact surface in contact with the first electrode layer. A relief portion from the contact surface is provided at a location facing the second electrode layer and has a slightly larger outline than the second electrode layer, and the relative position with respect to the semiconductor substrate is fixed. semiconductor devices. 2. A semiconductor device according to claim 1, wherein the semiconductor element and the contact electrode plate are each fixed to the container by pins, thereby fixing their relative positions. 3) A semiconductor device according to claim 1, wherein the semiconductor element and the contact electrode plate are fixed to each other by an insulating material, so that their relative positions are fixed. 4) A semiconductor device according to claim 1, wherein the semiconductor element and the contact electrode plate are fixed to each other by soldering or pressure welding, thereby fixing their relative positions.
JP58093768A 1983-05-27 1983-05-27 Semiconductor device Pending JPS59219962A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58093768A JPS59219962A (en) 1983-05-27 1983-05-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58093768A JPS59219962A (en) 1983-05-27 1983-05-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59219962A true JPS59219962A (en) 1984-12-11

Family

ID=14091603

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58093768A Pending JPS59219962A (en) 1983-05-27 1983-05-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59219962A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5046075A (en) * 1973-08-28 1975-04-24
JPS50152664A (en) * 1974-05-27 1975-12-08
JPS54162483A (en) * 1978-06-13 1979-12-24 Mitsubishi Electric Corp Semiconductor device
JPS5610969A (en) * 1979-07-06 1981-02-03 Mitsubishi Electric Corp Semiconductor controlled rectifier

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5046075A (en) * 1973-08-28 1975-04-24
JPS50152664A (en) * 1974-05-27 1975-12-08
JPS54162483A (en) * 1978-06-13 1979-12-24 Mitsubishi Electric Corp Semiconductor device
JPS5610969A (en) * 1979-07-06 1981-02-03 Mitsubishi Electric Corp Semiconductor controlled rectifier

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