JPS603155A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS603155A
JPS603155A JP11117583A JP11117583A JPS603155A JP S603155 A JPS603155 A JP S603155A JP 11117583 A JP11117583 A JP 11117583A JP 11117583 A JP11117583 A JP 11117583A JP S603155 A JPS603155 A JP S603155A
Authority
JP
Japan
Prior art keywords
contact
electrode
electrode plate
plate
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11117583A
Other languages
Japanese (ja)
Inventor
Katsuhiro Endo
遠藤 勝弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Corporate Research and Development Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Corporate Research and Development Ltd filed Critical Fuji Electric Corporate Research and Development Ltd
Priority to JP11117583A priority Critical patent/JPS603155A/en
Publication of JPS603155A publication Critical patent/JPS603155A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thyristors (AREA)

Abstract

PURPOSE:To prevent a short circuit between gate and cathode electrodes and a positional displacement between an element and a contact electrode plate by bonding a relieving section from the gate electrode and the contact electrode plate, to one part of an outer circumference thereof a projection is formed, with a semiconductor substrate with the electrodes by a projecting section. CONSTITUTION:The main surface of an Si substrate 1 is not machined in an irregular manner, and a through-hole 20 (or a groove), which is slightly larger than a gate electrode 2 and has the same contour as the gate electrode, is formed where a contact electrode plate 6 being in contact with a cathode electrode 3 is opposed to the gate electrode 2. A plurality of projections 22 are formed to the outer circumference of the contact plate 6, and a detaining section 24 for adhesives 23 is shaped on the whole circumference in the vicinity of the inside of the projections. The detaining section 24 is made larger than the outer diameter of an electrode 8. According to the constitution, a positional displacement between a semiconductor element and the contact electrode plate and the accidents of short circuits by the contact plate 6 of the gate electrode and the cathode electrode are not generated by the projecting sections 22, the permeation of adhesives 23 is prevented by the detaining section 24, an effective electrode area is not obstructed, and a device having high reliability is obtained.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は、例えば高速ザイリスタなどのように、複雑な
形状のゲート電極を備えた半導体装置−の組立構造に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field to Which the Invention Pertains] The present invention relates to an assembly structure of a semiconductor device having a complex-shaped gate electrode, such as a high-speed Zyristor.

〔従来技術とその問題点〕[Prior art and its problems]

第1図は高速ザイリスタ素子の表面形状を表わす平面図
であシ、第2図は第1図のA−A拡大断面図を示しいず
れも主要部に斜線を入れである。
FIG. 1 is a plan view showing the surface shape of a high-speed Zyristor element, and FIG. 2 is an enlarged sectional view taken along the line AA in FIG. 1, in which main parts are shaded.

第1図、第2図において、半導体基板1は主表面に複雑
な形状のゲート電極2とカソード電極3を備えており、
このような高速ザイリスタ累子が正常な動作を維持する
ために、ゲート電極2とツJンード電極3とが永続的に
短絡することがないよう両電極はそれぞれ分離して配置
されるのが普通である。4は第1段のゲート電極である
。このような半導体基板を有する半導体素子を容器に封
入した平型高速ザイリスタ装置のけ[面図を第3図に示
すが第1図、第2図と同一符号は同一名称を表1′:)
している。第3図に示すように、半導体基板1はモリブ
デンまたはタングステンからなる支持板5に固着されて
半導体素子を+11成し、半巧体基板1のカソード電極
3の上には、平滑な面をもった導電性金属1例えばモリ
ブデンなどから々る接触電極板6が当接される。ゲート
電極2とカソード電極3とが電気的に短絡を生じない配
置とする手段は第2図または第3図かられかるか、例え
ばシリコン基板1の主表面が凹凸面をもつように、薬品
などを用いてエツチング加工にょシ段差を形成し、シリ
コン基板1の四部にアルミ蒸着膜からなるゲート電極2
とシリコン基板1の最外主表面に同じくアルミ蒸着膜か
らなるカソード電極3を設けることによシイラわれる。
In FIGS. 1 and 2, a semiconductor substrate 1 has a complex-shaped gate electrode 2 and a cathode electrode 3 on its main surface.
In order to maintain normal operation of such a high-speed Zyristor resistor, the gate electrode 2 and the tunnel electrode 3 are usually arranged separately from each other so that they are not permanently short-circuited. It is. 4 is a first stage gate electrode. A flat-type high-speed Zyristor device in which a semiconductor element having such a semiconductor substrate is sealed in a container (a top view is shown in FIG. 3, but the same symbols as in FIGS. 1 and 2 are the same names as in Table 1')
are doing. As shown in FIG. 3, the semiconductor substrate 1 is fixed to a support plate 5 made of molybdenum or tungsten to form a semiconductor element, and the cathode electrode 3 of the semi-structured substrate 1 has a smooth surface. A contact electrode plate 6 made of a conductive metal 1 such as molybdenum is abutted. The means for arranging the gate electrode 2 and the cathode electrode 3 so that no electrical short circuit occurs can be found in FIGS. A gate electrode 2 made of an aluminum vapor-deposited film is formed on the four parts of the silicon substrate 1 by etching to form a step.
This is accomplished by providing a cathode electrode 3 made of an aluminum vapor-deposited film on the outermost main surface of the silicon substrate 1.

このようにしてシリコン基板1の主表面に設けた凹凸面
の高低差にょシ、ゲート電&2→接触電極板6との間に
空間絶縁部が生じ、ゲート電極2は接触電極板6に当接
しているカソード電極3と電気的絶縁状態が保たれてい
るのである。
In this way, due to the difference in height of the uneven surface provided on the main surface of the silicon substrate 1, a space insulation part is created between the gate electrode &2 and the contact electrode plate 6, and the gate electrode 2 comes into contact with the contact electrode plate 6. An electrically insulated state from the cathode electrode 3 is maintained.

第3図の平型半導体装置の組立て手順を説明すると、先
づフランジ7を介してろう接されたiK電極と絶縁環9
とからなる容器に、ばね部材1oと絶縁部材11ととも
に、これらを通したゲートリード線12を、先端がシリ
コン基板1の第1段ゲート電極4に当接されるべき個所
に載檻し、ゲートリード線12の他端は絶f桑環9を貫
通する管13に差込み、管13とともに端末でつぶして
一体に封止する。次に例えばテフロン製のスペースリン
グ14を容器に装入するが、スペースリング14には、
リード線12と交差する個所に切込みを入れてリード線
12が邪魔にならないようにしである。しかる後、接触
1L極板6と、前もって第2図のように主表面が凹凸に
加工されたシリコン基板Jと支持板5からなる半導体素
子を第3図のごとく配設し、最後に容器の着となるフラ
ンジ15を有する電極16を半導体素子の−EK信き、
フランジ15と絶縁環9に設けたフランジ17とを容器
の全周でへりアーク溶接してこの平型半導装置の組立て
が完了する。
To explain the assembly procedure of the flat semiconductor device shown in FIG.
The spring member 1o and the insulating member 11, as well as the gate lead wire 12 passed through them, are placed in a container consisting of a spring member 1o, an insulating member 11, and a gate lead wire 12 at a location where the tip thereof is to be in contact with the first stage gate electrode 4 of the silicon substrate 1. The other end of the lead wire 12 is inserted into a tube 13 passing through the mulberry ring 9, and the ends are crushed together with the tube 13 to seal them together. Next, a space ring 14 made of, for example, Teflon is inserted into the container.
A cut is made at the point where the lead wire 12 intersects so that the lead wire 12 does not get in the way. Thereafter, a semiconductor element consisting of a contact 1L electrode plate 6, a silicon substrate J whose main surface has been previously processed to have irregularities as shown in FIG. 2, and a support plate 5 is arranged as shown in FIG. 3, and finally the container is An electrode 16 having a flange 15 to be attached is attached to the -EK side of a semiconductor element,
The flange 15 and the flange 17 provided on the insulating ring 9 are edge arc welded around the entire circumference of the container to complete the assembly of this flat semiconductor device.

しかしながら、上記のような渦造をとっているために、
この平型半導体装置には次のような欠点が避けられない
However, due to the spiral structure described above,
This flat semiconductor device inevitably has the following drawbacks.

その一つは、シリコン基板1の主表面上に形成される凹
部の深さ寸法を0.02±001=に制御しなければな
らないという加工上の困難さを伴うことである。第4図
り第1図〜第3図の符号にしたがって、主表面が凹凸加
工されたシリコン基板1のゲート電極2とカソード電極
3および井j2触■I、極板6との関係を示した拡大断
面し1であるか、例えばシリコン基板1の主表面の凹部
の加工深さが規定寸法よシ浸すぎた場合には、i′r4
図に示すようにゲート電極2にフォトマスクの精度の恕
さなどに起因して突起部18が生じたん合、この突起部
18が接触電極板6に接触してし、ずうことがあシ、そ
の結呆ゲート電極2とカソード電極3との電気的な短路
を招く。址だ鋲5図←1第4図と同様な断面図を示した
ものであるが、この場合は例えにVシリコン基板1の主
表面に設けだ凹部に、製造過程中に金属微粒子などの異
物19が混入したために、との導電性をもった異物19
を介して、ゲート電極2と接触%、棒板6が接触するこ
とによシ、ゲート・カソード両電極間力見豆絡う゛るこ
とを表わしている。
One of the problems is that the depth dimension of the recess formed on the main surface of the silicon substrate 1 must be controlled to 0.02±001, which is difficult in processing. 4th diagram An enlarged diagram showing the relationship between the gate electrode 2 and the cathode electrode 3 of the silicon substrate 1 whose main surface is roughened according to the symbols in FIGS. 1 to 3, and the electrode plate 6. If the cross section is 1 or, for example, if the machining depth of the recess on the main surface of the silicon substrate 1 is too deep than the specified dimension, i'r4
As shown in the figure, if a protrusion 18 is formed on the gate electrode 2 due to the precision of the photomask, this protrusion 18 will come into contact with the contact electrode plate 6, and the result will be an accident. This leads to an electrical short circuit between the gate electrode 2 and the cathode electrode 3. Figure 5 ← 1 This is a cross-sectional view similar to Figure 4, but in this case, it is assumed that foreign matter such as fine metal particles was deposited in the recess formed on the main surface of the V-silicon substrate 1 during the manufacturing process. Due to the contamination of 19, a foreign substance 19 with conductivity of
This indicates that the contact between the gate electrode 2 and the bar plate 6 causes a force to be entangled between the gate and cathode electrodes.

欠点の第二は、第3図の平型ザイリスタの梠造では、半
導体素子が容器に収容された後に使用状態においてはじ
めて接触%j、極板6が加圧接触されるものであシ、半
導体素子も接触電極板6も常時拘束されている訳ではな
いからこのような平型サイリスクは、取扱い中に容器に
封入されている半導体素子や接触電極板6の回転力どが
原因でカソード電極膜3が削られて損傷するばかりでな
く、ゲート・カソード電極間の短絡を招くおそれがある
ことである。
The second drawback is that in the flat structure of the flat Zyristor shown in FIG. Since neither the element nor the contact electrode plate 6 is always restrained, such a flat silicon risk is caused by the rotational force of the semiconductor element sealed in the container or the contact electrode plate 6 during handling, causing the cathode electrode film to 3 is not only scratched and damaged, but also may cause a short circuit between the gate and cathode electrodes.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上述の欠点を除去し、ゲート電極とカ
ソード電極が接触電極板を介して煙路を生ずることなく
、かつ半導体素子と接触電極板との位置ずれを防止した
半導体装置を提供することにある。
An object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a semiconductor device in which a gate electrode and a cathode electrode do not create a smoke path through a contact electrode plate, and in which misalignment between a semiconductor element and a contact electrode plate is prevented. It's about doing.

〔発明の要点〕[Key points of the invention]

本発明の半導体装置は、主表面に凹凸を設りることなく
、ゲート、カソード両電極を配置した半導体基板に、貫
通孔または渦゛などのグー) Tii、 4微からの逃
は部と、外周の一部に突起部を設けた接触電極板を、そ
の突起部で接着剤を用いて半導体素子に取付けることに
よシ、接乃虫電極板と半導体素子との相対位置を整合さ
せたものである。
The semiconductor device of the present invention has a semiconductor substrate in which both a gate electrode and a cathode electrode are arranged without providing any unevenness on the main surface, and a relief portion from the groove such as a through hole or a vortex; A contact electrode plate with a protrusion on a part of its outer periphery is attached to the semiconductor element using adhesive at the protrusion, thereby aligning the relative positions of the contact electrode plate and the semiconductor element. It is.

〔発明の実施例〕[Embodiments of the invention]

以下本発明を実施例に基づき説りIIJする。 The present invention will be explained below based on examples.

本発明の装置とその組立て手順は第3図に示し。The apparatus of the present invention and its assembly procedure are shown in FIG.

たものとtデは同じであるから、零発す4 K rff
接係乙部分のみについて述べる。本発明の半導体装置が
第3図と異るJ力は、シリコン基板1.接触tb栓板6
の形状と、接触電極板6のシリコン基板1への固定構造
の諸点である。これらの点を第1図〜第5図と同一符号
、同一名称を用いて具体的に述べると、第6図に部分拡
大断1/11図で示したごとく、シリコン基板lの主表
面に凹凸加工を施すことなく、ゲート、カソード電極の
短絡を生じないようにするためには、カソード♂41.
極3と当接する接触電極板6のゲート電極2と対向する
個所に、ゲート電極2よpやや大きい同じ翰郭形状を有
する貫通孔20を − 、−設けるか もしくは貫通孔20の代シに、第7図に示したように溝
21を設けることが必要である。とのように接触電極板
6にゲート電極2との接触を避りるために、接触電極板
6の側に貫通孔20またけ溝21などの逃げ部を設ける
ことによυ、シリコン基板1の主表面に四部を設けてゲ
ートTt>14Hn 2を配置する必要はなくなり、モ
リブデンなどからなる接触電極板の貫通孔20や7(”
lj2]々どの逃は部汰さ寸法は0.1〜0.5 Mと
することができるから、この値は従来の欠点とされたシ
リコン基板1の主表面に設けられた凹凸の高低M002
−to、o 1門に比べてはるかに大きく、たとえゲー
ト電極2に前述−した第4図の突起18や第5図の異物
19の混入があったとしても、ゲート釦、核2の厚さ寸
法(1,02制に対して十分対応できる。ずなわちゲー
)TIN2と接触電極板6が直接接触する状態は起らな
いから、ゲート電極2とカソード電極3とが接触電極板
6を介して短絡を生ずるという現象はなくなる。
Since t and t are the same, the 4K rff emitted from zero
Only the connection part B will be described. The J force of the semiconductor device of the present invention is different from that shown in FIG. Contact tb plug plate 6
These are the shape of the contact electrode plate 6 and the fixing structure of the contact electrode plate 6 to the silicon substrate 1. To describe these points in detail using the same symbols and names as in FIGS. 1 to 5, as shown in FIG. In order to prevent a short circuit between the gate and cathode electrodes without any processing, the cathode ♂41.
A through hole 20 having the same outline shape, which is slightly larger than the gate electrode 2, is provided at a portion of the contact electrode plate 6 that contacts the pole 3 and faces the gate electrode 2, or in place of the through hole 20, It is necessary to provide grooves 21 as shown in FIG. In order to avoid the contact electrode plate 6 from coming into contact with the gate electrode 2, by providing relief parts such as through holes 20 and grooves 21 on the side of the contact electrode plate 6, the silicon substrate 1 It is no longer necessary to arrange the gate Tt
lj2] Since the size of each relief section can be set to 0.1 to 0.5 M, this value is determined by the height M002 of the unevenness provided on the main surface of the silicon substrate 1, which has been considered a conventional drawback.
-to, o It is much larger than the gate button 1, and even if the gate electrode 2 is contaminated with the protrusion 18 shown in FIG. 4 or the foreign matter 19 shown in FIG. Dimensions (sufficient for the 1.02 system, i.e. game) Since the TIN 2 and the contact electrode plate 6 do not come into direct contact, the gate electrode 2 and the cathode electrode 3 are connected via the contact electrode plate 6. This eliminates the phenomenon of short circuits.

しかしながら、このことは半導体基板1と4iH触電極
板6とが常に正しい位置を保ち整合されている場合であ
って、前述したように半導体基板1と接触電極板6との
相対位置が、それぞれの回転などによってずれた場合に
は、回転によるカソード電極の磨耗粉などを生じて短絡
することがあり得る。したがって半導体基板1と接触電
極板6とを固定し、との両者の廻り止めを設けなければ
ならない。
However, this is only the case where the semiconductor substrate 1 and the 4iH contact electrode plate 6 are always maintained in the correct position and aligned, and as mentioned above, the relative positions of the semiconductor substrate 1 and the contact electrode plate 6 are different from each other. If it is misaligned due to rotation, etc., the rotation may generate abrasion powder of the cathode electrode, which may cause a short circuit. Therefore, it is necessary to fix the semiconductor substrate 1 and the contact electrode plate 6 and to provide a mechanism to prevent them from rotating.

第8図は本発明に用いられる貫通孔20を有する接触電
極板6の平面図であり、外周に8.数個の突起部22を
設けである。第9図はこの接力虫電極版を例えばシリコ
ンゴムなどの接着剤23を用いてシリコン基板1に固定
した状態を示した1:IX分拡大断面図である。第9図
のように接触電極板6と・シリコン基&1とは突起部2
2の側面でも固着されるから、接触電極板6と、シリコ
ン基板1と支持&5からなる半導体素子は相対位置を正
しく合わされた後、両者の固着により、それぞれ単独に
移動することはなくなる。接触Wi IIIO2半導体
素子を固定するだけならば、接触電極板の外径寸法を大
きくしておき、その外縁部とシリコン基板の間を接着剤
23によシ固着すればよいが、接触電極板6または半導
体素子の回転力に対抗して回転を確実に阻止するために
、第8図のように突起部22を複数個設け、それらの側
面を利用している。なお突起部22は第8図の例では4
個所に設けであるが、この数を増せばさらに強固力廻り
止めをすることができ、寸だ突起部22の巾寸法につい
ても任意に設定することかできるが、これらのことは、
この半導体装置の使用に際しての実状に応じて決定ずれ
ばよい。第10図のように小さな突起部を数個づつ集め
て数個所に配置する外どがその例である。
FIG. 8 is a plan view of a contact electrode plate 6 having a through hole 20 used in the present invention, with an 8. Several protrusions 22 are provided. FIG. 9 is a 1:IX enlarged cross-sectional view showing this contact electrode plate fixed to the silicon substrate 1 using an adhesive 23 such as silicone rubber. As shown in FIG.
Since the contact electrode plate 6, the silicon substrate 1, and the semiconductor element consisting of the support &5 are properly aligned relative to each other, they will not move independently due to their fixation. If only the contact WiIIIO2 semiconductor element is to be fixed, the outer diameter of the contact electrode plate may be increased and the space between the outer edge and the silicon substrate is fixed with adhesive 23, but the contact electrode plate 6 Alternatively, in order to reliably prevent rotation against the rotational force of the semiconductor element, a plurality of protrusions 22 are provided as shown in FIG. 8, and their side surfaces are utilized. Note that the protrusion 22 is 4 in the example shown in FIG.
Although it is provided at several locations, if the number of the protrusions is increased, the rotation can be prevented even more strongly, and the width of the protrusion 22 can also be set arbitrarily, but these things are as follows.
It may be determined according to the actual situation when using this semiconductor device. An example of this is a case where several small protrusions are collected and placed in several locations as shown in FIG.

しかしながら、このような接触電極板6をシリコン板1
に接尤剤23を用いて固着し、第9図のごとくするに際
して、接触電椅、板6とカソード電極3との間に存在す
る微小な隙間に接着剤23が毛管現象によって流れ込み
、接触′r43.極板6とシリコン基板1との電気的接
触状態を害するおそれがある。このことを防ぐためには
、例えは第11図に示したように接触電極板6の突起部
22に接着剤23の滞留部24としC?(゛【形状をつ
けるか、才だけ第12図のごとく、突起部220内側近
傍の全周に、接着剤23の滞留部24を設けておく。
However, if such a contact electrode plate 6 is used as a silicon plate 1,
9, the adhesive 23 flows into the minute gap existing between the contact plate 6 and the cathode electrode 3 by capillary action, and the contact 'r43 .. This may damage the electrical contact between the electrode plate 6 and the silicon substrate 1. In order to prevent this, for example, as shown in FIG. (Due to the shape, as shown in FIG. 12, a retention portion 24 for the adhesive 23 is provided around the entire circumference near the inside of the protrusion 220.

この接着剤23の滞留部24を設けた突起部22を有す
る接触1[5極板6を半導体素子に取シイマ]リブこイ
ろ38と下部電極16も備えた図としである。加圧接触
の平型半導体素子では、加圧力が均等に伝達され、片押
しにならないように電極8および1Gの外径寸法をカソ
ード電極3の外径寸法よシ小さの上に設けられる接着剤
23の滞留部24の位置は、少くとも′FLL槙8の外
径寸法より大きく、接触電極板6の外径寸法よシ小芒い
範囲内におることが必要である。このようにすれは接角
J 7.Lt電極板とシリコン基板1とを接着剤23で
固免するときに、たとえ接着斉1]23が内部に浸透し
2ても滞留部24に捕足されるから、カソード電@3の
有効ル、極面積までm:気的接触状態を害することなく
、この半導体装置の電気的性能に影響を与えることもな
い。
The contact 1 has a protrusion 22 with a retention portion 24 for the adhesive 23 (the five-electrode plate 6 is attached to a semiconductor element), and also includes a rib coil 38 and a lower electrode 16. In a pressurized contact flat semiconductor element, an adhesive is provided on the electrodes 8 and 1G so that the outer diameter is smaller than that of the cathode electrode 3 so that the pressurizing force is evenly transmitted and there is no one-sided push. The position of the retention portion 24 of 23 must be at least larger than the outer diameter of the FLL pin 8 and within a smaller range than the outer diameter of the contact electrode plate 6. In this way, the tangent angle is J7. When the Lt electrode plate and the silicon substrate 1 are firmly separated with the adhesive 23, even if the adhesive 1] 23 penetrates inside, it will be caught in the retention part 24, so the effective luminescence of the cathode electrode @3 will be reduced. , up to the pole area m: does not impair the gas contact state and does not affect the electrical performance of this semiconductor device.

〔発明の効果〕〔Effect of the invention〕

以上説明したごとく、本発明によれdl、シリコン基板
の主表面に、極めて手数がかがシ、シかも深さの寸法精
細が困雌な凹部を設けて、ゲート電極を配置する必要が
なくなシ、ゲート、カソード電極間の短絡が発生するこ
となく、長期間にわたって半導体装置を安定に運転する
ことができる。
As explained above, according to the present invention, it is no longer necessary to provide a recess on the main surface of the silicon substrate, which is extremely complicated and difficult to precisely define the depth, and to arrange the gate electrode. The semiconductor device can be operated stably for a long period of time without short circuits occurring between the gate electrode, the cathode electrode, and the cathode electrode.

このような効果が得られるのは、ゲート’iE+、仲と
対向する位置で、接触電極板にゲート、カソード両’i
l’i:極間の短絡防止のだめの逃げ部を設けてあり、
ゲート電極と接触電極板の位柩門係が正しく擦合してい
るからであるが、この相対位置関係がなんらかの理由で
維持できなくなった場合は41Jひ短絡の問題が生ずる
。これに対して本発明の装置?■でdl、接触電極板の
外周に複数個の突起部を設りて、この突起部と半導体基
板とを、接f’J、’l!711極板の厚さとなってい
る突起部のlli面部でもシリコンゴム在どの接着剤で
固定しであるので、接触電極板や半導体素子の回転方向
も含めた動きを阻止することができる。また接着剤を塗
布−j:たけ滴下するときに、これが接触電極板とシリ
コンJi、板との隙間に浸入1して、半導体素子の導通
性を悪くする懸念に対しては、接触電極板に接着剤の滞
留部を設けて、接着剤の浸入がそれ以上没入しないよう
にし、有効電極面積を減することなく、この半導体装置
の特性が保持されている。
This effect can be obtained at the position opposite to the gate 'iE+ and the center, and when both the gate and cathode 'iE+ are connected to the contact electrode plate.
l'i: A relief part is provided to prevent short circuit between the poles,
This is because the gate electrode and the contact electrode plate are properly rubbed together, but if this relative positional relationship cannot be maintained for some reason, a short circuit problem will occur. In contrast, the device of the present invention? At (dl), a plurality of protrusions are provided on the outer periphery of the contact electrode plate, and the protrusions and the semiconductor substrate are brought into contact with f'J,'l! Since the lli surface portion of the protrusion having the thickness of the 711 electrode plate is fixed with any adhesive such as silicone rubber, movement of the contact electrode plate and the semiconductor element including the direction of rotation can be prevented. In addition, when applying adhesive to the contact electrode plate, there is a possibility that it may penetrate into the gap between the contact electrode plate and the silicon plate, impairing the conductivity of the semiconductor element. An adhesive retention portion is provided to prevent the adhesive from penetrating any further, and the characteristics of this semiconductor device are maintained without reducing the effective electrode area.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は高速ザイリスタ素子の′市価配f+I<を示す
平面図、第2図は同じく部分拡大断面図、第3図は従来
の平型半¥!8体装匹−の…「面図、第4図、第5図は
電極の短絡状態を示す部分拡大断面図、第6図、第7図
は本発明の′@、極第1イ造を示す部分拡大断面図、第
8図、第10図、*!11図、第12図は本発明による
接触電極板の形状を示す平角j図、第9図、第13図は
本発明の接触電極板と半層体基版との固定状態を示す部
分拡大断面図である。 1・・・・・・シリコン基板、2・・・・・・ゲート電
全返、3・・・・・・カソード電極、5・・・・・・支
持板、6・・川・接M+箱極板、20・・・・・・貫通
孔、21・・・・・・溝、22・・曲突起部、23・・
・・・・接着剤、24・・・・・・接着剤滞留部。 71図 1 22図 第5口 第6口 77図 78図 f9図 i10図 771図 才12図 713図  228−
Fig. 1 is a plan view showing the market price distribution f+I< of a high-speed Zyristor element, Fig. 2 is a partially enlarged sectional view of the same, and Fig. 3 is a conventional flat type semi-circular sectional view. Figures 4 and 5 are partially enlarged cross-sectional views showing the short-circuited state of the electrodes, and Figures 6 and 7 show the first structure of the present invention. 8, 10, *! 11, and 12 are rectangular J views showing the shape of the contact electrode plate according to the present invention, and FIGS. 9 and 13 are the contact electrodes of the present invention. It is a partially enlarged cross-sectional view showing the fixed state of the plate and the half-layer substrate. 1...Silicon substrate, 2...Gate electric current fully returned, 3...Cathode Electrode, 5...Support plate, 6...River/contact M+box electrode plate, 20...Through hole, 21...Groove, 22...Curved protrusion, 23・・・
...Adhesive, 24...Adhesive retention part. 71 Figure 1 22 Figure 5 Port 6 Port 77 Figure 78 Figure f9 Figure i10 Figure 771 Figure 12 Figure 713 Figure 228-

Claims (1)

【特許請求の範囲】 1)半導体基板の主表面に、接触電極板と接続される第
一の電極層と、前記接触板と接続されない第二の電極層
を有するものにおいて、接触電極板は、前記第一の電極
層と接触する接触面と、前記第二の電極層と対向する個
所に設けられ前記第二の電極層よシやや大きい輪郭を有
する前記接触面からの逃げ部と、外周側面の複数個所に
設けられた突起部とを備え、該突起部側面と前記半導体
基板とが接着剤により互に固着されたことによって、前
記半導体基板に対する相対位置が固定されたことを特徴
とする半導体装置。 2、特許請求の範囲第1項記載の装置において、接触電
極板の外周部近傍もしくは突起部に、接着剤の滞留部が
設けられたことを特徴とする半導体装置。
[Scope of Claims] 1) In a semiconductor substrate having a first electrode layer connected to a contact electrode plate and a second electrode layer not connected to the contact electrode plate on the main surface of the semiconductor substrate, the contact electrode plate includes: a contact surface that contacts the first electrode layer; a relief portion from the contact surface that is provided at a location facing the second electrode layer and has a slightly larger outline than the second electrode layer; and an outer peripheral side surface. a protrusion provided at a plurality of locations, and a side surface of the protrusion and the semiconductor substrate are fixed to each other with an adhesive, thereby fixing a relative position with respect to the semiconductor substrate. Device. 2. A semiconductor device according to claim 1, characterized in that an adhesive retention portion is provided near the outer periphery of the contact electrode plate or on the protrusion.
JP11117583A 1983-06-21 1983-06-21 Semiconductor device Pending JPS603155A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11117583A JPS603155A (en) 1983-06-21 1983-06-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11117583A JPS603155A (en) 1983-06-21 1983-06-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS603155A true JPS603155A (en) 1985-01-09

Family

ID=14554382

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11117583A Pending JPS603155A (en) 1983-06-21 1983-06-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS603155A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6279669A (en) * 1985-10-03 1987-04-13 Mitsubishi Electric Corp Semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50152664A (en) * 1974-05-27 1975-12-08
JPS5265667A (en) * 1975-11-27 1977-05-31 Mitsubishi Electric Corp Semiconductor device
JPS557342B2 (en) * 1972-05-31 1980-02-25

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS557342B2 (en) * 1972-05-31 1980-02-25
JPS50152664A (en) * 1974-05-27 1975-12-08
JPS5265667A (en) * 1975-11-27 1977-05-31 Mitsubishi Electric Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6279669A (en) * 1985-10-03 1987-04-13 Mitsubishi Electric Corp Semiconductor device

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