JPS605562A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS605562A
JPS605562A JP11333383A JP11333383A JPS605562A JP S605562 A JPS605562 A JP S605562A JP 11333383 A JP11333383 A JP 11333383A JP 11333383 A JP11333383 A JP 11333383A JP S605562 A JPS605562 A JP S605562A
Authority
JP
Japan
Prior art keywords
electrode plate
electrode
contact
plate
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11333383A
Other languages
Japanese (ja)
Inventor
Katsuhiro Endo
遠藤 勝弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Corporate Research and Development Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Corporate Research and Development Ltd filed Critical Fuji Electric Corporate Research and Development Ltd
Priority to JP11333383A priority Critical patent/JPS605562A/en
Publication of JPS605562A publication Critical patent/JPS605562A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492Bases or plates or solder therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To prevent the displacement of the positions between a semiconductor element and a contacting electrode plate by inserting the plate formed with an escape such as a through hole or a groove into a semiconductor substrate on which both gate and cathode electrodes are disposed without forming irregular surface on a main surface along a guide formed of an insulating material secured to the gate electrode. CONSTITUTION:A contacting electrode plate guide ring 22 formed of an insulating material such as resin or ceramic of the same profile as the part is secured to the vicinity of the central region of the surface of a gate electrode 2, for example, by an epoxy resin adhesive 23. A central hole is engaged along the outer periphery of the ring 22 formed on the electrode 2, and a contacting electrode plate 6 having a through hole contacted with a cathode electrode 3 is simultaneously mounted. Thus, a semiconductor substrate 1 and the plate 6 are correctly matched by the shape of the ring 22, and the displacement of the positions between them is not caused at all due to the rotation.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は、例えば高速サイリスタなどのように、複雑な
形状のゲート電極を備えた半導体装置の組立構造に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to an assembly structure of a semiconductor device having a complex-shaped gate electrode, such as a high-speed thyristor.

〔従来技術とその問題点〕[Prior art and its problems]

第1図は高速サイリスタ素子の表面形状を1表わす平面
図であり、第2図は第1図のA−A拡大断゛面図を示し
である。第1図、第2図において、半導体基板1は主表
面に複雑な形状のゲート電極2とカソード電極3を備え
ておシ、このよう々高速サイリスタ素子が正常な動作を
維持するために、ゲート電極2とカソード電極3とが永
続的に短絡することがないよう両電極はそれぞれ分離し
て配置されるのが普通である。外部に接続されて主電流
が流れるのはカソード′#i、極3であシ、ゲー ト電
極2は補助サイリスタの電極である。4は外部に接続さ
れる第1段のゲート電極である。
FIG. 1 is a plan view showing the surface shape of a high-speed thyristor element, and FIG. 2 is an enlarged sectional view taken along the line AA in FIG. 1. 1 and 2, a semiconductor substrate 1 has a complex-shaped gate electrode 2 and a cathode electrode 3 on its main surface. Generally, the electrodes 2 and the cathode electrode 3 are arranged separately from each other to prevent permanent short-circuiting between the two electrodes. The cathode '#i, pole 3 is connected to the outside and the main current flows through it, and the gate electrode 2 is the electrode of the auxiliary thyristor. 4 is a first stage gate electrode connected to the outside.

このような半導体基板を有する半導体素子を容器に封入
した平型高速サイリスタ装置の断面図を第3図に示すが
第1図、第2図と同一符号は同一名称を表わしている。
A sectional view of a flat high speed thyristor device in which a semiconductor element having such a semiconductor substrate is sealed in a container is shown in FIG. 3, and the same reference numerals as in FIGS. 1 and 2 represent the same names.

第3図に示すように、半導体基板1はモリブデンまたは
タングステンからなる支持板5に固着されて半導体素子
を構成シ2、半導体基板1のカソード電極3の上には、
平滑外面をもった導電性金属2例えばモリブデンなどか
らなる接触電極板6が当接される。ゲート電極2とカソ
ード電極3とが電気的に短絡を生じない配置とする手段
は第2図または第3図かられかるが、例えばシリコン基
板lの主表面が凹凸面をもつように、薬品などを用いて
エツチング加工にょシ段差を形成し、シリコン基板1の
凹部にアルミ蒸着膜からなるゲート電極2とシリコン基
板1の最外主表面に同じくアルミ蒸着膜からなるカソー
ド電極3を設けることにより行われる。とのようにして
シリコン基板1の主表面に設けた凹凸面の高低差によシ
、ゲート電極2種接触電極板6との間に。
As shown in FIG. 3, a semiconductor substrate 1 is fixed to a support plate 5 made of molybdenum or tungsten to constitute a semiconductor element 2, and on a cathode electrode 3 of the semiconductor substrate 1,
A contact electrode plate 6 made of a conductive metal 2, such as molybdenum, having a smooth outer surface is brought into contact. The means for arranging the gate electrode 2 and the cathode electrode 3 so that no electrical short circuit occurs is shown in FIGS. This is done by forming a step by etching using a silicon substrate 1, and providing a gate electrode 2 made of an aluminum vapor-deposited film in the recessed part of the silicon substrate 1 and a cathode electrode 3 also made of an aluminum vapor-deposited film on the outermost main surface of the silicon substrate 1. be exposed. Due to the difference in height of the uneven surface provided on the main surface of the silicon substrate 1 as shown in FIG.

空間絶縁部が生じ、ゲート電極2は接触電極板6に当接
しているカソード電極3と電気的絶縁状態が保たれてい
るのである。
A space insulation portion is created, and the gate electrode 2 is kept electrically insulated from the cathode electrode 3 which is in contact with the contact electrode plate 6.

第3図の平型半導体装置の組立て手順を説明すると、先
づフランジ7を介してろう接された電極8と絶縁環9と
からなる容器に、ばね部材1oと絶縁部材11とともに
、これらを通したゲートリード線12を、先端がシリコ
ン基板1の第1段ゲート電極4に当接されるべき個所に
載置し、ゲートリード線12の他端は絶縁環9を貫通す
る管13に差込み、管13とともに端末でつぶして一体
に封止する。次に例えばテフロン製のスペースリング1
4を容器に装入するか、スペースリング14には、リー
ド線12と交差する個所に切込みを入れてリード線12
が邪魔にならないようにしである。しかる後、接触電極
板6と、前もって第2図のように主表面が凹凸に加工さ
れたシリコン基板1と支持板5からなる半導体素子を第
3図のごとく配設し、最後に容器の蓋となるフランジ1
5を崩する電極16を半導体素子の上に置き、フランジ
15と絶縁環9に設けたフランジ17とを容器の全周で
へりアーク溶接してこの平型半導体装置の組立てが完了
する。
To explain the assembly procedure of the flat semiconductor device shown in FIG. 3, first, the spring member 1o and the insulating member 11 are passed through a container consisting of an electrode 8 and an insulating ring 9 which are soldered together via a flange 7. The gate lead wire 12 is placed on the silicon substrate 1 at a location where its tip is to be brought into contact with the first stage gate electrode 4, and the other end of the gate lead wire 12 is inserted into the tube 13 penetrating the insulating ring 9. Together with the tube 13, the ends are crushed and sealed together. Next, for example, Teflon space ring 1
4 into a container, or make a cut in the space ring 14 at the point where it intersects with the lead wire 12 and insert the lead wire 12 into the space ring 14.
Make sure it doesn't get in the way. Thereafter, a semiconductor element consisting of a contact electrode plate 6, a silicon substrate 1 whose main surface has been previously processed to have irregularities as shown in FIG. 2, and a support plate 5 is arranged as shown in FIG. Flange 1
An electrode 16 is placed on top of the semiconductor element, and the flange 15 and the flange 17 provided on the insulating ring 9 are edge arc welded around the entire circumference of the container, completing the assembly of this flat semiconductor device.

しかしながら、上記のような構造をとっているために、
この平型半導体装置には次のような欠点が避けられない
However, due to the structure described above,
This flat semiconductor device inevitably has the following drawbacks.

その一つは、シリコン基板1の土床向上に形成される四
部の深さ寸法を0.02”O°’mに制御しなければな
らないという加工上の困難さを伴うことである。第4図
は第1図〜第3図の符号にしたがって、主表面が凹凸加
工されたシリコン基板1のゲート電極2とカソード電極
3および接触電極板6との関係を示した拡大断面図であ
るが、例えばシリコン基板1の主表面の凹部の加工深さ
が規定寸法よシ浅すぎた場合には、第4図に示すように
ゲート電極2にフォトマスクの精度の悪さ力とに起因し
て突起部18が生じた場合、この突起部18が接触電極
板6に接触してしまうことがあシ、その結果ゲート電極
2とカソード電極3七の電気的な短絡を招く。また第5
図は第4図と同様な断面図を示したものであるが、この
場合は例えばシリコン基板1の主表面に設けた四部に、
製造過程中に金属微粒子などの異物19が混入したため
、この導電性をもった異物19を介して、ゲート電極2
と接触電極板6が接触することによシ、ゲート・カソー
ド両電極間が短絡することを表わしている。
One of them is that the depth dimension of the four parts formed on the soil surface of the silicon substrate 1 must be controlled to 0.02''O°'m, which is accompanied by processing difficulties.Fourth The figure is an enlarged sectional view showing the relationship between a gate electrode 2, a cathode electrode 3, and a contact electrode plate 6 of a silicon substrate 1 whose main surface is roughened according to the symbols in FIGS. 1 to 3. For example, if the machining depth of the recess on the main surface of the silicon substrate 1 is too shallow than the specified dimension, a protrusion may be formed on the gate electrode 2 due to the poor precision of the photomask and force, as shown in FIG. 18, this protrusion 18 may come into contact with the contact electrode plate 6, resulting in an electrical short circuit between the gate electrode 2 and the cathode electrode 37.
The figure shows a cross-sectional view similar to FIG. 4, but in this case, for example, in the four parts provided on the main surface of the silicon substrate 1,
Because foreign matter 19 such as metal particles was mixed in during the manufacturing process, the gate electrode 2
This indicates that when the contact electrode plate 6 comes into contact with the contact electrode plate 6, a short circuit occurs between the gate and cathode electrodes.

欠点の第二は、第3図の平型サイリスタの構造では、半
導体素子が容器に収容された後に使用状態においてはじ
めて接触電極板6が加圧接触されるものであシ、半導体
素子も接触電極板6も常時拘束されている訳ではないか
ら、このような平型サイリスクは、取扱い中に容器に封
入されている半導体素子や接触電極板6の回転な1どが
原因てカソード電極膜3が削られて損傷するばかシで々
く、ゲート・カソード両電極間の短絡を招くおそれがあ
ることである。
The second drawback is that in the structure of the flat thyristor shown in FIG. 3, the contact electrode plate 6 is brought into contact with pressure only in the use state after the semiconductor element is housed in the container, and the semiconductor element also has a contact electrode plate 6. Since the plate 6 is not always restrained, such a flat silicon risk is caused by damage to the cathode electrode film 3 due to rotation of the semiconductor element sealed in the container or the contact electrode plate 6 during handling. It is extremely fragile and can be scratched and damaged, which may lead to a short circuit between the gate and cathode electrodes.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上述の欠点を除去し、ゲート電極とカ
ソード電極が接触電極板を介して短絡を生ずることなく
、かつ半導体素子と接触電極板との位置ずれを防止した
半導体装置を提供することにある。
An object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a semiconductor device in which the gate electrode and the cathode electrode are not short-circuited through the contact electrode plate, and the misalignment between the semiconductor element and the contact electrode plate is prevented. There is a particular thing.

〔発明の股点〕[The crux of invention]

本発明の半導体装置は、主表面に凹凸を設けることなく
ゲート、カソード両電極を配置した半導体基板に、貫通
孔または溝などの逃げ部を設けた接触電極板を、ゲート
電極に固着した絶縁態別からなるガイドに沿って挿入す
ることによシ、接触電極板と半導体素子との相対位置を
整合させて固定したものである。
The semiconductor device of the present invention has an insulating structure in which a contact electrode plate provided with relief parts such as through holes or grooves is fixed to the gate electrode on a semiconductor substrate in which both gate and cathode electrodes are arranged without providing any unevenness on the main surface. By inserting the contact electrode plate and the semiconductor element along separate guides, the relative positions of the contact electrode plate and the semiconductor element are aligned and fixed.

〔発明の実施例〕[Embodiments of the invention]

以下本発明を実施に基づき説明する。 The present invention will be explained below based on implementation.

本発明の半導体装置とその組立て手順は第3図に示した
ものとほぼ同じであるから、本発明に直接係る部分のみ
について述べる0本発明の半導体装置が第3図と異る所
は、シリコン基板1.接触電極板6の形状と、接触電極
板6のシリコン基板1への固定構造の諸点である。これ
ら点を第1図〜第5図と同一符号、同一名称を用いて具
体的に述べると、第6図に部分拡大断面図で示したごと
く、シリコン基板1の主表面に凹凸加工を施すことなく
、カソード電極3と当接する接触電極板6のゲート電極
2と対向する個所に、ゲート電極2よυやや大きい同じ
輪郭形状を有する貫通孔20を設けである。第7図も第
6図と同様、部分拡大断面図であるが、この場合は第6
図の貫通孔20の代りに、接触電極板6に溝21を設け
ている。
Since the semiconductor device of the present invention and its assembly procedure are almost the same as those shown in FIG. 3, only the parts directly related to the present invention will be described. Substrate 1. These are the shape of the contact electrode plate 6 and the structure for fixing the contact electrode plate 6 to the silicon substrate 1. To specifically describe these points using the same symbols and names as in FIGS. 1 to 5, as shown in a partially enlarged cross-sectional view in FIG. Rather, a through hole 20 having the same contour shape and slightly larger than the gate electrode 2 is provided at a portion of the contact electrode plate 6 that is in contact with the cathode electrode 3 and faces the gate electrode 2 . Like FIG. 6, FIG. 7 is also a partially enlarged sectional view, but in this case, the 6th
A groove 21 is provided in the contact electrode plate 6 instead of the through hole 20 shown in the figure.

第6図と第7図かられかるように、このようにすれば、
シリコン基板1の主表面に、凹部を設けてゲート電極2
を配置する必要はなく、まだ接触電極板6として用いら
れるモリブデンなど電気良導体の貫通孔20や溝21な
どの逃げ部深さ寸法は0.1〜0.5 Wtnとするこ
とができるから、従来の欠点とされたシリコン基板1の
主表面に設けた凹凸の高低差0.02:Il:0・Ol
−に比べてはるかに大きく、たとえゲート電極2に前述
した第4図の突起18や第5図の異物19の混入があっ
たとしても、ゲート電極2の厚さ寸法0.02mmに対
して十分対応できる。すなわち、ゲート電、極2と接触
電極板6が直接接触する状態は起こらないから、ゲート
電極2とカソード電極3とが接触電極板6を介して短絡
を生ずるという現象はなくなる。
As you can see from Figures 6 and 7, if you do this,
A concave portion is provided on the main surface of the silicon substrate 1 to form a gate electrode 2.
It is not necessary to arrange the contact electrode plate 6, and the depth dimension of the relief part such as the through hole 20 and groove 21 of a good electrical conductor such as molybdenum used as the contact electrode plate 6 can be set to 0.1 to 0.5 Wtn. The height difference of the unevenness provided on the main surface of the silicon substrate 1, which was considered to be a drawback of 0.02:Il:0・Ol
Even if the gate electrode 2 is contaminated with the protrusion 18 shown in FIG. 4 or the foreign matter 19 shown in FIG. I can handle it. That is, since the gate electrode 2 and the contact electrode plate 6 do not come into direct contact with each other, there is no short circuit between the gate electrode 2 and the cathode electrode 3 via the contact electrode plate 6.

しかし々から、このことは半導体基板1と接触電極板6
とが常に正しい位置を保ち整合されている場合であって
、前述したように半導体基板lと接触電極板6との相対
位置が、それぞれの回転などによってずれた場合には、
回転によるカソード電極の磨耗粉などを生じて短絡を生
ずることがあシ得る。したがって半導体基板1と接触電
極板6とを固定し、この両者の廻シ止めを設けなければ
ならない。第8図と第9図は、この廻シ止めの役割シを
果す接触電極板6を挿入するガイドを設けた半導体基板
1を示したものであシ、第8図は平面図、第9図は第8
図のA−A拡大断面図である。
However, this means that the semiconductor substrate 1 and the contact electrode plate 6
are always kept in the correct position and aligned, and if the relative positions of the semiconductor substrate l and the contact electrode plate 6 are shifted due to their respective rotations as described above,
A short circuit may occur due to abrasion of the cathode electrode due to rotation. Therefore, it is necessary to fix the semiconductor substrate 1 and the contact electrode plate 6 and to provide a stopper for rotation of both. 8 and 9 show the semiconductor substrate 1 provided with a guide for inserting the contact electrode plate 6, which serves as a rotation stopper. FIG. 8 is a plan view, and FIG. 9 is a plan view. is the 8th
It is an AA enlarged sectional view of a figure.

第8図および第9図は第1〜第7図と同一符号。8 and 9 have the same reference numerals as in FIGS. 1 to 7.

同一名称で表わしであるが、ゲート電極2の表面の中心
領域近くにその部分と同じ輪郭の樹脂またはセラミック
などの絶縁材料からなる接触電極板ガイド環22を例え
ばエポキシ樹脂系接着剤23によシ固着した状態を示す
。第10図はゲート電極2上に設けられた接触宜モ極板
ガイド現22の外周に沿って中心孔がはめ込まれ、同時
にカソード電極3と当接される貫通孔をもった接触電極
板6が取付けられた状態を拡大断面図で示したものであ
る。かくして、本発明の半導体装置においては、第8図
に示したガイド環22の形状から、半導体基板1と接触
電極板6が正しく墓合された以後、回転などによって両
者の位置がずれるという心配は全くないことがわかる。
Although expressed by the same name, a contact electrode plate guide ring 22 made of an insulating material such as resin or ceramic and having the same outline as that part is attached near the center area of the surface of the gate electrode 2 using, for example, an epoxy resin adhesive 23. Indicates a fixed state. FIG. 10 shows a contact electrode plate 6 having a center hole fitted along the outer periphery of a contact electrode plate guide 22 provided on the gate electrode 2, and a through hole that is brought into contact with the cathode electrode 3 at the same time. It is an enlarged sectional view showing the installed state. Thus, in the semiconductor device of the present invention, due to the shape of the guide ring 22 shown in FIG. 8, there is no fear that the positions of the semiconductor substrate 1 and the contact electrode plate 6 will shift due to rotation or the like after they are properly aligned. It turns out that there is none at all.

〔発明の効果〕〔Effect of the invention〕

以上説明したごとく、本発明によれば、シリコン基板の
主表面に、極めて手数がかがシ、シかも深さの制御が困
難な凹部を設けて、ゲート電極を配置する必要がなくな
シ、ゲート、カソード電極間の短絡が発生するとと々く
、長期間にわたって半導体装置を安定に運転することが
できる。このような効果が得られるのは、ゲート電極と
対向する位置で、接触電極板にゲート、カソード両箱。
As explained above, according to the present invention, it is no longer necessary to provide a recess on the main surface of a silicon substrate, which is extremely complicated and whose depth is difficult to control, and to arrange a gate electrode. As soon as a short circuit occurs between the gate and cathode electrodes, the semiconductor device can be stably operated for a long period of time. This effect can be obtained at the position facing the gate electrode, where both the gate and cathode boxes are placed on the contact electrode plate.

極間の短絡防止のための逃は部を設けてあシ、ゲート電
極と接触電極板の位置関係が正しく整合しているからで
あるが、この相対位置関係がなんらかの理由で維持でき
なくなった場合は、再び短絡の問題が生ずる。この原因
となる最も起とシやすい現象は、封入組立後の取扱い中
の接触電極板と半導体素子の回転であるが、これに対し
て本発明の装置では、ゲート電極の上に接触電極板と組
合せて効果のあるm、b止め部品を固着して、接触驚極
板と半導体基板がそ些ぞれ単独に回転するととをなくし
ている。すなわち、ゲート電極の主部と枝部の一部に固
着した絶縁環と接触電極板が嵌合して回転を阻止するこ
とができる。廻り止めの目的だけならば必ずしもグー)
E極上だけに限ることなく、半導体基板の主表面をさら
に広く利用することもできるが、本発明で特にゲート電
極上に廻シ止めを設けたのは、接着剤を介して絶縁物を
固着するという簡単な方法をとるために、この絶縁物が
、主電流の流れるカソード電極領域にまで及ぶことがな
いようにし、カソード電極の有効面積を最大限に活かし
たためである。すなわち本発明の装置はこの半導体装置
の電気的性能に全く形管のない半導体累子栴成要素の回
転防止を実現でき、芒らに別の利点としてmb止め部品
が上述の回転防止だけでなく、接触電極板の取付ガイド
の役割をも果している。以上述べたように接触電極板と
半導体素子は短絡を生ずることのない一定の相対位置関
係を正確に保ち続けることができるので、この半導体装
置は常に安定な運転状態が得られるのである。
This is because a relief part is provided to prevent a short circuit between the electrodes, and the positional relationship between the gate electrode and the contact electrode plate is correctly aligned, but if this relative positional relationship cannot be maintained for some reason. In this case, the problem of short circuit occurs again. The phenomenon that is most likely to cause this is the rotation of the contact electrode plate and semiconductor element during handling after encapsulation assembly, but in the device of the present invention, the contact electrode plate is placed on top of the gate electrode. By fixing stop parts m and b, which are effective in combination, it is possible to eliminate the problem that the contact start plate and the semiconductor substrate rotate independently. That is, the insulating ring fixed to the main part and part of the branch part of the gate electrode fits into the contact electrode plate, thereby preventing rotation. If the purpose is only to stop rotation, it is not necessarily good)
Although the main surface of the semiconductor substrate can be used more widely than just on the E electrode, the reason why the rotation stopper is particularly provided on the gate electrode in the present invention is that the insulator is fixed using an adhesive. In order to take this simple method, the insulator was prevented from reaching the cathode electrode area where the main current flows, and the effective area of the cathode electrode was utilized to the maximum. In other words, the device of the present invention can prevent the rotation of the semiconductor component forming element without any form in the electrical performance of the semiconductor device, and has another advantage that the MB stopper not only prevents the rotation as described above. , also serves as a mounting guide for the contact electrode plate. As described above, since the contact electrode plate and the semiconductor element can continue to accurately maintain a certain relative positional relationship without causing a short circuit, this semiconductor device can always maintain a stable operating state.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は高速サイリスタ素子の電極配置を示す゛平面図
、第2図は同じく拡大部分断面図、第3図は従来の平型
半導体装置の断面図、第4図、第5図は電極の短終状態
を示す拡大部分断面図、第6図、第7図は本発明の電極
構造を示す拡大部分断面図、第8図はゲート電極上に設
けたガイド更を示す平面図、第9図は同じく拡大部分断
面図、第10図は本発明の接触電極板と半導体基板との
固定状態を示す拡大部分断面図である。 1・・・・・・シリコン基板、2・・・・・・グー) 
電&r 3・・・・・・カソードを極、6・・・・・・
接触電極板、20・・・・・・貫通孔、21・・・・・
・接触電極板ガイド環、23・・・・・・接71図 才2図 才4図 第5図 96図 オフ図 才8図 29図
Fig. 1 is a plan view showing the electrode arrangement of a high-speed thyristor element, Fig. 2 is an enlarged partial sectional view, Fig. 3 is a sectional view of a conventional flat semiconductor device, and Figs. 4 and 5 show the arrangement of electrodes. 6 and 7 are enlarged partial sectional views showing the electrode structure of the present invention; FIG. 8 is a plan view showing a guide layer provided on the gate electrode; FIG. 9 10 is also an enlarged partial sectional view, and FIG. 10 is an enlarged partial sectional view showing the state in which the contact electrode plate of the present invention and the semiconductor substrate are fixed. 1...Silicon substrate, 2...Goo)
Electron &r 3...Cathode as pole, 6...
Contact electrode plate, 20... Through hole, 21...
・Contact electrode plate guide ring, 23...Contact 71 Figure 2 Figure 4 Figure 5 Figure 96 Off figure 8 Figure 29

Claims (1)

【特許請求の範囲】[Claims] 1)半導体基板の主表面に、接触電極板を介して外部回
路に接続される第一の電極層と、外部回路に接続されな
い主部と枝部からなる第二の電極層とを有するものにお
いて、接触電極販社、前記第一の電極層と接触する接触
面と、前記第二の電極層と対向する個所に設けられ前記
第二の電極層よシや中大きく主部と枝部からなる前記接
触面からの逃げ部を有し、かつ逃げ部の主部および枝部
の一部に嵌合し、前記第二の電極層の上に固着される絶
縁環が備えられたことを特徴とする半導体装置0
1) In a semiconductor substrate having, on the main surface thereof, a first electrode layer connected to an external circuit via a contact electrode plate, and a second electrode layer consisting of a main part and a branch part not connected to the external circuit. , a contact electrode sales company, the contact surface that contacts the first electrode layer, and the second electrode layer, which is provided at a location facing the second electrode layer, and has a main portion and branch portions that are large in size. An insulating ring is provided, which has a relief part from the contact surface, fits into the main part and part of the branch part of the relief part, and is fixed on the second electrode layer. Semiconductor device 0
JP11333383A 1983-06-23 1983-06-23 Semiconductor device Pending JPS605562A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11333383A JPS605562A (en) 1983-06-23 1983-06-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11333383A JPS605562A (en) 1983-06-23 1983-06-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS605562A true JPS605562A (en) 1985-01-12

Family

ID=14609579

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11333383A Pending JPS605562A (en) 1983-06-23 1983-06-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS605562A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01293186A (en) * 1988-05-18 1989-11-27 Daicel Chem Ind Ltd Antibacterial treatment of washing water for flush toilet

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4939367B1 (en) * 1970-12-31 1974-10-25
JPS5297670A (en) * 1976-02-12 1977-08-16 Mitsubishi Electric Corp Semiconductor device
JPS54162483A (en) * 1978-06-13 1979-12-24 Mitsubishi Electric Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4939367B1 (en) * 1970-12-31 1974-10-25
JPS5297670A (en) * 1976-02-12 1977-08-16 Mitsubishi Electric Corp Semiconductor device
JPS54162483A (en) * 1978-06-13 1979-12-24 Mitsubishi Electric Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01293186A (en) * 1988-05-18 1989-11-27 Daicel Chem Ind Ltd Antibacterial treatment of washing water for flush toilet

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