JPS605564A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS605564A
JPS605564A JP58113335A JP11333583A JPS605564A JP S605564 A JPS605564 A JP S605564A JP 58113335 A JP58113335 A JP 58113335A JP 11333583 A JP11333583 A JP 11333583A JP S605564 A JPS605564 A JP S605564A
Authority
JP
Japan
Prior art keywords
plate
electrode plate
contact
groove
contact electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58113335A
Other languages
Japanese (ja)
Inventor
Katsuhiro Endo
遠藤 勝弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Corporate Research and Development Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Corporate Research and Development Ltd filed Critical Fuji Electric Corporate Research and Development Ltd
Priority to JP58113335A priority Critical patent/JPS605564A/en
Publication of JPS605564A publication Critical patent/JPS605564A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/32Holders for supporting the complete device in operation, i.e. detachable fixtures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thyristors (AREA)

Abstract

PURPOSE:To prevent the displacement of the positions between a semiconductor element and a contacting electrode plate by holding by a U-shaped clip a supporting plate of a semiconductor substrate, on which both gate and cathode electrodes are disposed without providing an irregular surface on a main surface, and a contacting electrode plate formed with an escape such as a through hole or a groove. CONSTITUTION:A stationary groove 22 for mounting a clamp to prevent the rotation is provided in the vicinity of the outer periphery of the surface of a contacting electrode plate. The contacting plate 6 and a semiconductor element formed of a silicon substrate 1 and a supporting plate 5 are secured with a U- shaped clamp 23 having a hook at the end formed of an insulating member such as rubber or Teflon. In this case, a groove 24 is formed similarly to the groove 22 of the plate 6 in the vicinity of the outer periphery of the surface of the plate 5. Thus, the clamp 23 is engaged with the stationary grooves 22, 24, thereby matching the plate 6 and the element at the relative positions to thereafter inhibit them to solely move.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は、例えば高速サイリスタなどのように、複雑な
形状のゲート電極を備えた半導体装置の組立構造に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to an assembly structure of a semiconductor device having a complex-shaped gate electrode, such as a high-speed thyristor.

〔従来技術とその問題点〕[Prior art and its problems]

第1図は高速サイリスク素子の表面形状を表わす平面図
であシ、第2図は第1図のA−A拡大断面図を示しいず
れも主要部に斜線を入れである。
FIG. 1 is a plan view showing the surface shape of a high-speed silice element, and FIG. 2 is an enlarged cross-sectional view taken along the line AA in FIG. 1, in which main parts are shaded.

第1図、第2図において、半導体基板1は主表面に複雑
な形状のゲート電極2とカソード電極3を備えておシ、
このような高速サイリスタ素子が正常な動作を維持する
ために、ゲート電極2とカソード電極3とが永続的に短
絡することがないよう両電極はそれぞれ分離して配置さ
れるのが普通である。4は第1段のゲート電極である。
In FIGS. 1 and 2, a semiconductor substrate 1 has a complex-shaped gate electrode 2 and a cathode electrode 3 on its main surface.
In order to maintain normal operation of such a high-speed thyristor element, the gate electrode 2 and the cathode electrode 3 are generally arranged separately from each other so that the two electrodes are not permanently short-circuited. 4 is a first stage gate electrode.

このような半導体基板を有する半導体素子を容器に封入
した平型高速サイリスタ装置の断面図を第3図に示すが
第1図、第2図と同一符号は同一名称を表わしている。
A sectional view of a flat high speed thyristor device in which a semiconductor element having such a semiconductor substrate is sealed in a container is shown in FIG. 3, and the same reference numerals as in FIGS. 1 and 2 represent the same names.

第3図に示すように、半導体基板1はモリブデンまたは
タングステンからなる支持板5に固着されて半導体素子
を構成し、半導体基板1のカソード電極3の上には、平
滑な面をもった導電性金属1例えばモリブデンなどから
なる接触電極板6が当接される。ゲート電極2とカソー
ド電極3とが電気的に短絡を生じない配置とする手段は
第2図または第3図かられかるが、例えばシリコン基板
1の主表面が凹凸面をもつように、薬品などを用いてエ
ツチング加工により段差を形成し、シリコン基板1の凹
部にアルミ蒸着膜からなるゲート電極2とシリコン基板
1の最外主表面に同じくアルミ蒸着膜から々るカソード
電極3を設けることにより行われる。このようにしてシ
リコン基板1の主表面に設けた凹凸面の高低差によp1
ゲート%、極2社接触電極板6との間に空間絶縁部が生
じ、ゲート電&2は接触電極板6に当接しているカソー
ド電極3と電気的絶縁状態が保たれているのである。
As shown in FIG. 3, a semiconductor substrate 1 is fixed to a support plate 5 made of molybdenum or tungsten to constitute a semiconductor element, and a conductive layer with a smooth surface is placed on a cathode electrode 3 of the semiconductor substrate 1. A contact electrode plate 6 made of a metal 1 such as molybdenum is brought into contact. The means for arranging the gate electrode 2 and the cathode electrode 3 so that no electrical short circuit occurs is shown in FIGS. This is done by forming a step by etching using silicon substrate 1, and providing a gate electrode 2 made of an aluminum vapor deposited film in the recessed part of the silicon substrate 1 and a cathode electrode 3 also made of an aluminum vapor deposited film on the outermost main surface of the silicon substrate 1. be exposed. In this way, due to the height difference of the uneven surface provided on the main surface of the silicon substrate 1, p1
A space insulation portion is created between the gate electrode and the contact electrode plate 6, and the gate electrode &2 is kept electrically insulated from the cathode electrode 3 which is in contact with the contact electrode plate 6.

第3図の平型半導体装置の組立て手順を説明すると、先
づフランジ7を介してろう接された電極8と絶縁環9と
からなる容器に、ばね部材10と絶縁部材11とともに
、これらを通したゲートリード線12を、先端がシリコ
ン基板1の第1段ゲート電極4に当接されるべき個所に
載置し、ゲートリード線12の他端は絶縁環9を貫通す
るち・13に差込み、管13とともに端末でつぶして一
体に封止する。次に例えばテフロン製のスペースリング
14を容器に装入するが、スペースリング14には、リ
ードm12と交差する個所に切込みをへれてリード線1
2が邪魔にならないようにしである。しかる後、接触電
極板6と、前もって第2図のように主表面が凹凸に加工
されたシリコン基板1と支持板5からなる半導体素子を
第3図のごとく配設し、最後に容器の蓋となるフランジ
15を有する電極16を半導体素子の上に置き、フラン
ジ15と絶縁環9に設けたフランジ17とを容器の全周
でへりアーク溶接してこの平型半導装置の組立てが完了
する。
To explain the assembly procedure of the flat semiconductor device shown in FIG. 3, first, the electrodes 8 and the insulating ring 9 are passed through the container together with the spring member 10 and the insulating member 11, which are soldered via the flange 7. The gate lead wire 12 is placed on the silicon substrate 1 at a location where its tip is to be in contact with the first stage gate electrode 4, and the other end of the gate lead wire 12 is inserted into the hole 13 that passes through the insulating ring 9. , together with the tube 13, are crushed at the ends and sealed together. Next, a space ring 14 made of, for example, Teflon is inserted into the container, and a notch is cut into the space ring 14 at the point where it intersects with the lead wire m12.
2 so that it doesn't get in the way. Thereafter, a semiconductor element consisting of a contact electrode plate 6, a silicon substrate 1 whose main surface has been previously processed to have irregularities as shown in FIG. 2, and a support plate 5 is arranged as shown in FIG. An electrode 16 having a flange 15 as shown in FIG. .

しかしながら、上記のような構造をとっているために、
この平型半導体装置には次のような欠点が避けられない
However, due to the structure described above,
This flat semiconductor device inevitably has the following drawbacks.

その一つは、シリコン基17Rhの主表面上に形成され
る四部の深さ寸法を0102±001瓢に制御しなけれ
ばならないという加工上の困難さを伴うことである。第
4図は第1図〜第3図の符号にしたがつて、主表面が凹
凸加工されたシリコン基板1のゲート電極2とカソード
電極3および接触電極板6との関係を示した拡大断面図
でおるが、例えばシリコン基板1の主表面の凹部の加工
深さが規定寸法よシ浅すぎた場合には、第4図に示すよ
うにゲート電極2にフォトマスクの精度の悪さなどに起
因して突起部18が生じた場合、この突起部18が接触
電極板6に接触してしまうことがあシ、その結果ゲート
電極2とカソード電極3との電気的な短絡を招く。また
第5図は第4図と同様な断面図を示したものであるが、
この場合は例えばシリコン基板1の主表面に設けた凹部
に、製造過程中に金属微粒子などの異物19が混入した
ために、この導電性をもった異物19を介して、ゲート
電極2と接触電極板6が接触することによシ、ゲート・
カソード両電極間が短絡することを表わしている。
One of them is that it is difficult to process because the depth dimension of the four parts formed on the main surface of the silicon base 17Rh must be controlled to 0102±001 mm. FIG. 4 is an enlarged sectional view showing the relationship between the gate electrode 2, the cathode electrode 3, and the contact electrode plate 6 of the silicon substrate 1 whose main surface is roughened according to the symbols in FIGS. 1 to 3. However, for example, if the processing depth of the recess on the main surface of the silicon substrate 1 is too shallow than the specified dimension, the gate electrode 2 may be damaged due to poor precision of the photomask, etc., as shown in FIG. If the protrusion 18 is generated, the protrusion 18 may come into contact with the contact electrode plate 6, resulting in an electrical short circuit between the gate electrode 2 and the cathode electrode 3. In addition, Fig. 5 shows a cross-sectional view similar to Fig. 4, but
In this case, for example, because foreign matter 19 such as metal particles has entered the concave portion provided on the main surface of the silicon substrate 1 during the manufacturing process, the conductive foreign matter 19 may be interposed between the gate electrode 2 and the contact electrode plate. By contacting 6, the gate
This indicates that there is a short circuit between the cathode and both electrodes.

欠点の第二は、第3図の平型サイリスタの構造では、半
導体素子が容器に収容された後に使用状態においてはじ
めて接触電極板6が加圧接触されるものであシ、半導体
素子も接触電極板6も常時拘束されている訳ではないか
らこのような平型サイリスタは、取扱い中に容器に封入
されている半導体素子や接触電極板6の回転などが原因
でカソード電極膜3が削られて損傷するばかシでなく、
ゲート・カソード両電極間の短絡を招くおそれがあると
とである。
The second drawback is that in the structure of the flat thyristor shown in FIG. 3, the contact electrode plate 6 is brought into contact with pressure only in the use state after the semiconductor element is housed in the container, and the semiconductor element also has a contact electrode plate 6. Since the plate 6 is not always restrained, the cathode electrode film 3 of such a flat thyristor may be scraped due to rotation of the semiconductor element sealed in the container or the contact electrode plate 6 during handling. Don't be afraid to damage it,
This may lead to a short circuit between the gate and cathode electrodes.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上述の欠点を除去し、ゲート電極とカ
ソード電極が接触電極板を介して短絡を生ずることなく
、かつ半導体素子と接触電極板との位置ずれを防止した
半導体装置を提供することにある。
An object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a semiconductor device in which the gate electrode and the cathode electrode are not short-circuited through the contact electrode plate, and the misalignment between the semiconductor element and the contact electrode plate is prevented. There is a particular thing.

〔発明の要点〕[Key points of the invention]

本発明の半導体装置は、主表面に凹凸を設けることなく
、ゲート、カソード−両電極を配置した半導体基板の受
持セ→支持板と、貫゛通孔または溝などの逃げ部を設け
た接触電極板とをコの字状クリップで挾むことによシ、
接触電極板と半導体素子との相対位置を整合させて固定
したものである。
The semiconductor device of the present invention has no irregularities on its main surface, and has a support plate for a semiconductor substrate having a gate, a cathode, and both electrodes, and a contact plate provided with relief parts such as through holes or grooves. By holding the electrode plate with a U-shaped clip,
The contact electrode plate and the semiconductor element are fixed by aligning their relative positions.

〔発明の実施例〕[Embodiments of the invention]

以下本発明を実施例に基づき説明する0本発明の半導体
装置とその組立手順は、第3図に示したものと原理的に
は同じであシ、共通点も多いから、以下本発明に直接係
る部分のみについて述べる0本発明の半導体装置が第3
図と異る所は、シリコン基板1.接触電極板6の形状と
、接触電極板6のシリコン基板1への固定構造に関する
諸点である。これらの点を第1図〜第5図と同一符号、
同一名称を用いて述べると、第6図に部分拡大断面で示
したごとく、シリコン基板1の主表面に凹凸加工を施す
ことなく、ゲート、カソード両電極の短絡を生じないよ
うにするためには、カソード翫&3と当接する接触電極
板6のゲートを極2と対向する個所に、ケー)%極2よ
シやや大きい同じ輪郭形状を有する貫通孔20を設りる
か、もしくは貫通孔20の代シに、第7図に示したよう
に溝21を設けることが必要でちる0このように接触−
極板6にゲートを極2との接触を避けるために、接触電
極板6の側に貫通孔20または溝21などの逃げ部を設
けることによシ、シリコン基板1の主表面に凹部を設け
てグー)1極2を配置する必要はなくなシ、モリブデン
などからなる接触電極板の貫通孔−20や溝21などの
逃げ部深さ寸法は0.1〜05咽とすることができるか
ら、この値は従来の欠点とされたシリコン基板1の主表
面に設けられた凹凸の高低差0.02″:061論に比
べてはるかに大きく、たとえゲート電極2に前述した第
4図の突起18や第5図の異物19の混入があったとし
ても、ゲート−極2の厚さ寸法0.02mに対して十分
対応できる。すなわちゲート電極2と接触電極板6が直
接接触する状態は起こらないから、ゲート電極2とカソ
ード電極3とが接触電極板6を介して短絡を生ずるとい
う現象はなくなる。
The present invention will be described below based on examples.The semiconductor device of the present invention and its assembly procedure are the same in principle as the one shown in FIG. Only the relevant parts will be described.The semiconductor device of the present invention is the third embodiment.
The difference from the figure is silicon substrate 1. These are various points regarding the shape of the contact electrode plate 6 and the fixing structure of the contact electrode plate 6 to the silicon substrate 1. These points are designated by the same symbols as in Figures 1 to 5.
Using the same name, as shown in the partially enlarged cross section of FIG. 6, in order to prevent short-circuiting between the gate and cathode electrodes without applying unevenness to the main surface of the silicon substrate 1, , a through hole 20 having the same contour shape and slightly larger than the electrode 2 is provided at a location where the gate of the contact electrode plate 6 that comes into contact with the cathode rod &3 faces the electrode 2; It is necessary to provide a groove 21 in the contact hole as shown in FIG.
In order to prevent the gate from contacting the electrode plate 6 with the electrode 2, a recess such as a through hole 20 or a groove 21 is provided on the side of the contact electrode plate 6, and a recess is provided on the main surface of the silicon substrate 1. It is no longer necessary to arrange one pole and two, and the depth of the relief parts such as through holes 20 and grooves 21 of the contact electrode plate made of molybdenum etc. can be set to 0.1 to 0.5 mm. , this value is much larger than the height difference of 0.02":061 between the unevenness provided on the main surface of the silicon substrate 1, which has been considered a drawback of the conventional method. Even if the protrusion shown in FIG. Even if the foreign matter 18 or the foreign matter 19 shown in FIG. Therefore, the phenomenon of short circuit between the gate electrode 2 and the cathode electrode 3 via the contact electrode plate 6 is eliminated.

しかしながら、このことは半導体基板1と接触電極板6
とが常に正しい位置を保ち整合されている場合であって
、前述したように半導体基板1と接触電極板6との相対
位置か、それぞれの回転などによってずれた場合には、
回転によるカソード電極の磨耗粉などを生じて短絡する
ことがあシ得る。したがって半導体基板1と接触電極板
6とを固定し、この両者のNu)止めを設けなければな
らカい。
However, this does not mean that the semiconductor substrate 1 and the contact electrode plate 6
are always kept in the correct position and aligned, but if the relative positions of the semiconductor substrate 1 and the contact electrode plate 6 are shifted due to their respective rotations, etc., as described above,
Due to rotation, abrasion of the cathode electrode may generate powder, which may cause a short circuit. Therefore, it is necessary to fix the semiconductor substrate 1 and the contact electrode plate 6 and provide a stop for both.

第8図は本発明に用いられる接触電極板6の平面図、第
9図は同じく第8図のB−B断面図を示したものであシ
、逃は部として貫通孔20を備えている場合であるが、
回転を防ぐだめの固定具を数句けるための固定溝22を
この接触電極板6の表面外周近傍に設けである。
FIG. 8 is a plan view of the contact electrode plate 6 used in the present invention, and FIG. 9 is a sectional view taken along the line B-B in FIG. In case,
A fixing groove 22 is provided near the outer periphery of the surface of the contact electrode plate 6 to provide a fixing member for preventing rotation.

第10図は上記接触版6と、シリコン基板1と支持板5
からなる半導体素子を、((’itえばゴム、テフロン
などの絶縁部材からなる先端に鉤状部を有するコ字状固
定具23を用いて固定した状態を示しているが、この際
支持板5の表面外周部近傍に接触電極板6の固定溝22
と同様に溝24を設けておく。第10図かられかるよう
にコ字状固定具23を固定溝22および24にはめ込む
ことにより接触電極板6と半導体素子は相対位置が整合
され、以後単独に移動することはない。なお第8図で固
定溝22を接触電極板6の全周に設けであるがとれは部
分的に設置してもよく、支持板5の固定溝24について
も同様である。この場合コ字状固定具23はこれらの固
定溝に応じて設ければよい。すなわち接触電極板6と半
導体素子との固定個所の面積が大きい程回転力の阻止に
対して有効ではあるが、必ずしも全周を用いる必要はな
く、適宜実状に応じて決めればよい。
FIG. 10 shows the contact plate 6, the silicon substrate 1, and the support plate 5.
A semiconductor element made of A fixing groove 22 of the contact electrode plate 6 is provided near the outer periphery of the surface of the contact electrode plate 6.
Similarly, a groove 24 is provided. As shown in FIG. 10, by fitting the U-shaped fixture 23 into the fixing grooves 22 and 24, the relative positions of the contact electrode plate 6 and the semiconductor element are aligned, and they will not move independently thereafter. In FIG. 8, the fixing groove 22 is provided around the entire circumference of the contact electrode plate 6, but the groove may be provided partially, and the same applies to the fixing groove 24 of the support plate 5. In this case, the U-shaped fixture 23 may be provided in accordance with these fixing grooves. That is, the larger the area of the fixing point between the contact electrode plate 6 and the semiconductor element, the more effective it is in blocking rotational force, but it is not necessarily necessary to use the entire circumference, and it may be determined as appropriate depending on the actual situation.

〔発明の効果〕〔Effect of the invention〕

以上説明したごとく、本発明によれば、シリコン基板の
主表面に、極めて手数がかがシ、シかも深さの制御が困
難な凹部を設けて、ゲート電極を配置する必要がなくな
シ、ゲート、カソード両電極間の短絡が発生することな
く、長期間にわたって半導体装置を安定に運転すること
ができる。このような効果が得られるのは、グー)%極
と対向する位置で、接触電極板にゲート、カソード両電
極間の短絡防止のための逃は部を設けてあシ、ゲート電
極と接触電極板の位置関係が正しく整合しているからで
あるが、この相対位置関係がなんらかの理由で維持でき
なくなった場合は、再び短絡の問題が生ずる。これに対
し本発明の装置では、それぞれ取シ付は溝が設けられた
接触電極板と半導体基板の支持板との側面から、先端に
鉤状部を有するコ字状絶縁体をはめ込むことにより、接
触電極板と半導体素子を一体として固定し、それぞれが
単独に回転することをなくしている。この廻り止め部品
は、本発明の半導体装置の組立てに際しては、接触電極
の貫通孔をゲート電極の上に置くようにして、接触電極
板と半導体素子との位置決めをした後、伸縮性を利用し
てはめ込むだけでよいから、組立て操作は極めて簡単で
作業性がよく、シかも確実に接触電極板や半導体素子の
回転を阻止することができるという効果のほかに、この
廻シ止め具は接触電極板と半導体素子の側面から押えて
いるだけで、半導体基板自体にはなんら手を加えること
がないので、半導体装置の電気的性能については、全く
懸念する必要がないという利点もちる。
As explained above, according to the present invention, it is no longer necessary to provide a recess on the main surface of a silicon substrate, which is extremely complicated and whose depth is difficult to control, and to arrange a gate electrode. The semiconductor device can be stably operated for a long period of time without shorting between the gate and cathode electrodes. This effect can be obtained by providing a relief part on the contact electrode plate to prevent short circuit between the gate and cathode electrodes at the position opposite to the contact electrode. This is because the positional relationship of the plates is correctly matched, but if this relative positional relationship cannot be maintained for some reason, the problem of short circuit will occur again. On the other hand, in the device of the present invention, the mounting is carried out by fitting a U-shaped insulator having a hook-shaped portion at the tip from the side surface of the grooved contact electrode plate and the support plate of the semiconductor substrate. The contact electrode plate and the semiconductor element are fixed as one body, preventing each from rotating independently. When assembling the semiconductor device of the present invention, this anti-rotation component is used after positioning the contact electrode plate and the semiconductor element by placing the through hole of the contact electrode on top of the gate electrode, and then using its elasticity. The assembly operation is extremely simple and workable, as all you have to do is fit it in.In addition to being able to reliably prevent the rotation of the contact electrode plate and semiconductor element, this rotation stopper also has the advantage of being able to prevent the contact electrode plate and semiconductor elements from rotating. This method has the advantage that there is no need to worry about the electrical performance of the semiconductor device at all, since the semiconductor substrate itself is not touched at all by simply holding down the board and the semiconductor element from the sides.

第1図は高速サイリスタ素子の電極配置を示す平面図、
第2図は同じく部分拡大断面図、第3図は従来の平型半
導体装置の断面図、第4図、第5図社電極の短絡状態を
示す部分拡大断面図、@6図、第7図は本発明の電極構
造を示す部分拡大断面図、第8図は本発明による接触電
極板の平面図。
Figure 1 is a plan view showing the electrode arrangement of a high-speed thyristor element;
Fig. 2 is a partially enlarged sectional view, Fig. 3 is a sectional view of a conventional flat semiconductor device, Figs. 4 and 5 are partially enlarged sectional views showing the short-circuited state of the electrodes, @ Fig. 6, and Fig. 7. 8 is a partially enlarged sectional view showing the electrode structure of the present invention, and FIG. 8 is a plan view of the contact electrode plate according to the present invention.

第9図は同じく断面図、第10図は本発明の接触電極板
と半導体素子との同定状態を示す部分拡大断面図である
FIG. 9 is a sectional view, and FIG. 10 is a partially enlarged sectional view showing how the contact electrode plate and semiconductor element of the present invention are identified.

1・・・・・・シリコン基板、2・・・・・・ゲート電
極、3・・・・・・カソード電極、5・・・・・・支持
板、6・・・・・・接触電極板、20・・・・・・貫通
孔、21・・・・・・構、22.24・・・・・・固定
溝、23・・・・・・コ字状絶縁体。
DESCRIPTION OF SYMBOLS 1...Silicon substrate, 2...Gate electrode, 3...Cathode electrode, 5...Support plate, 6...Contact electrode plate , 20... through hole, 21... structure, 22.24... fixing groove, 23... U-shaped insulator.

71図 才2図 24図 才5図 16図 $7阿 f9図 才10図Figure 71 2nd figure Figure 24 5th figure Figure 16 $7a f9 diagram age 10

Claims (1)

【特許請求の範囲】[Claims] 1)半導体基板の主表面に、接触電極板と接続される第
一の電極層と、前記接触板と接続されない第二の電極層
を有するものにおいて、接触電極板は、前記第一の電極
層と接触する接触面と、前記第二の電極層と対向する個
所に設けられ前記第二の電極層よシやや大きい輪郭を有
する前記接触面からの逃げ部と、前記接触面と反対の面
に固定具取付は溝とを備え、かつ該取付は溝と半導体支
持板に設けられた固定具取付は溝とに掛かる鉤状部を先
端に有するコ字状絶縁体が備えられたことを特徴とする
半導体装置。
1) In a semiconductor substrate having a first electrode layer connected to the contact electrode plate and a second electrode layer not connected to the contact plate on the main surface of the semiconductor substrate, the contact electrode plate has a first electrode layer connected to the contact electrode plate. a contact surface in contact with the contact surface, a relief portion from the contact surface provided at a location facing the second electrode layer and having a slightly larger outline than the second electrode layer, and a relief portion on a surface opposite to the contact surface. The fixture mounting includes a groove, and the fixture is provided with a U-shaped insulator having a hook-shaped portion at its tip that hangs over the groove and the semiconductor support plate. semiconductor devices.
JP58113335A 1983-06-23 1983-06-23 Semiconductor device Pending JPS605564A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58113335A JPS605564A (en) 1983-06-23 1983-06-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58113335A JPS605564A (en) 1983-06-23 1983-06-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS605564A true JPS605564A (en) 1985-01-12

Family

ID=14609631

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58113335A Pending JPS605564A (en) 1983-06-23 1983-06-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS605564A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03149880A (en) * 1989-11-06 1991-06-26 Mitsubishi Electric Corp Semiconductor device and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03149880A (en) * 1989-11-06 1991-06-26 Mitsubishi Electric Corp Semiconductor device and manufacture thereof

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