JPS6114666B2 - - Google Patents

Info

Publication number
JPS6114666B2
JPS6114666B2 JP55183103A JP18310380A JPS6114666B2 JP S6114666 B2 JPS6114666 B2 JP S6114666B2 JP 55183103 A JP55183103 A JP 55183103A JP 18310380 A JP18310380 A JP 18310380A JP S6114666 B2 JPS6114666 B2 JP S6114666B2
Authority
JP
Japan
Prior art keywords
base metal
electrode layer
metal layer
solder
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55183103A
Other languages
Japanese (ja)
Other versions
JPS57106056A (en
Inventor
Keiji Inoe
Yasuo Kamya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55183103A priority Critical patent/JPS57106056A/en
Publication of JPS57106056A publication Critical patent/JPS57106056A/en
Publication of JPS6114666B2 publication Critical patent/JPS6114666B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05551—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05555—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/05578—Plural external layers being disposed next to each other, e.g. side-to-side arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/13076—Plural core members being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/13078—Plural core members being disposed next to each other, e.g. side-to-side arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

【発明の詳細な説明】 この発明は、半導体装置の電極構造体に関し、
フエース・ダウン・ボンデイング（Face Down
Bonding）法により半導体チツプと支持基板を電
気的、機械的に結合する際に、信頼性の良好な半
導体装置の電極構造体を提供するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrode structure for a semiconductor device,
Face Down Bonding
The present invention provides an electrode structure for a semiconductor device that is highly reliable when electrically and mechanically bonding a semiconductor chip and a supporting substrate using a bonding method.

フエース・ダウン・ボンデイング法は半導体装
置の性能向上や高集積化、あるいは製造工程の簡
略化、歩留りの向上等の要望に応えるものであ
る。この接続方法は半導体チツプ上の複数個の電
極膜と絶縁性支持基板上の複数個の配線を半田を
介して接続するものであり、上記の半導体チツプ
上の電極膜、および基板上の配線のいずれか一
方、あるいは両方に半田丘を設け、半導体チツプ
と基板とを所定位置に固定した後に加熱、冷却す
ることによつて、上記半田丘を介して半導体チツ
プと基板間を電気的に接続するとともに、半導体
チツプを基板に支持固定するものである。 The face-down bonding method responds to demands for improved performance and higher integration of semiconductor devices, simplification of manufacturing processes, and improved yields. This connection method connects multiple electrode films on a semiconductor chip and multiple wiring lines on an insulating support substrate through solder. By providing a solder hill on one or both of them, fixing the semiconductor chip and the board in a predetermined position, and then heating and cooling, the semiconductor chip and the board are electrically connected via the solder hill. It also supports and fixes the semiconductor chip to the substrate.

以下に、この種の半導体チツプの構造につい
て、第１図の断面図を使用して説明する。 The structure of this type of semiconductor chip will be explained below using the sectional view of FIG.

第１図において、１は半導体基板、２は前記半
導体基板１の主表面に形成した絶縁膜、３はAl
等の配接層であり、これらで各種電気回路素子が
完成し、この電気回路素子表面は表面保護膜４で
覆われている。そして、配線層３上の半田電極層
を設ける位置のみが開孔され、その上に半田電極
層の下地金属層５が形成されている。この下地金
属層は５、例えばクローム（0.1μｍ）―銅（10
μｍ）のような構成で形成されている。この後、
半田丘である半田電極層６をデイツピング法で形
成する。 In FIG. 1, 1 is a semiconductor substrate, 2 is an insulating film formed on the main surface of the semiconductor substrate 1, and 3 is an Al
Various electric circuit elements are completed with these interconnection layers, and the surface of this electric circuit element is covered with a surface protection film 4. A hole is formed only at a position on the wiring layer 3 where a solder electrode layer is to be provided, and a base metal layer 5 for the solder electrode layer is formed thereon. This base metal layer is 5, for example, chrome (0.1 μm)-copper (10
μm). After this,
A solder electrode layer 6, which is a solder hill, is formed by a dipping method.

上記の構造を有し、半田電極層６の下地金属層
５が第３図に示すような形状で120μｍ×120μｍ
程度の大きさを有する従来の半田電極層６の場
合、半田電極層６直下の表面保護膜４にクラツク
ｃが第２図に示すように入ることがある。このク
ラツクｃは、この後の組立工程、および製品とし
て使用時の熱衝撃で拡大し配線を断線させたり、
また、著しい場合は半導体の電気回路素子の特性
を劣化させたりして、製品としての信頼性を著し
く低下させる原因となつていた。 It has the above structure, and the base metal layer 5 of the solder electrode layer 6 has a shape as shown in FIG. 3 and has a size of 120 μm×120 μm.
In the case of a conventional solder electrode layer 6 having a certain size, cracks c may form in the surface protective film 4 directly under the solder electrode layer 6 as shown in FIG. This crack C expands during the subsequent assembly process and due to thermal shock during use as a product, causing the wiring to break.
Furthermore, in severe cases, the characteristics of semiconductor electric circuit elements may be deteriorated, resulting in a significant decrease in the reliability of the product.

このクラツクｃの発生原因を第２図の断面図に
より説明する。第２図は半田電極層６直下の表面
保護膜４′の周辺部を拡大したものである。ただ
し、半田電極層６は除いている。半田電極層６の
下地金属層５は半田デイピング時の高温処理時に
膨張し、第２図の矢印ａの方向に強い力を受け
る。しかし、表面保護膜４，４′は下地金属層５
の大部分を形成している銅に比べて熱膨張率が非
常に小さいので、半田電極層６直下の表面保護膜
４′は矢印ｂの方向にひずむ力を受ける。そこ
で、最も力のかかる半田電極層６の下地金属層５
のエツヂ部分の近傍で、表面保護膜４にクラツク
ｃが発生する。 The cause of this crack c will be explained with reference to the sectional view of FIG. FIG. 2 is an enlarged view of the periphery of the surface protection film 4' directly under the solder electrode layer 6. However, the solder electrode layer 6 is excluded. The base metal layer 5 of the solder electrode layer 6 expands during high temperature treatment during solder dipping and is subjected to a strong force in the direction of arrow a in FIG. However, the surface protective films 4, 4' are
Since the coefficient of thermal expansion is much smaller than that of copper, which forms most of the solder electrode layer 6, the surface protection film 4' directly under the solder electrode layer 6 is subjected to a straining force in the direction of the arrow b. Therefore, the base metal layer 5 of the solder electrode layer 6, which is subjected to the most force,
A crack c occurs in the surface protective film 4 near the edge portion.

第３図は前述したように半田電極層６の下地金
属層５の上面図を示す。この場合、半田デイツプ
時の高温処理時に膨張する際に受ける力ａは、そ
の方向の下地金属層５の長さｈに比例すると考え
てよい。このことから考えると、半田電極層６の
各辺の長さを小さくするとよいことがわかる。し
かし、半田電極層６の大きさは電気的特性および
機械的強度、また、ボンデイング時の位置合せ余
裕度を考慮すると、必要以上にその面積を小さく
することはできない。 FIG. 3 shows a top view of the base metal layer 5 of the solder electrode layer 6, as described above. In this case, it can be considered that the force a received during expansion during high temperature treatment during solder dipping is proportional to the length h of the base metal layer 5 in that direction. Considering this, it can be seen that it is better to reduce the length of each side of the solder electrode layer 6. However, the size of the solder electrode layer 6 cannot be made smaller than necessary in consideration of electrical characteristics and mechanical strength, as well as positioning margin during bonding.

この発明は、これらの欠点を改良することを目
的としたもので、クラツクの発生しない半田電極
層構造を提供するものである。以下、この発明に
ついて説明する。 The present invention aims to improve these drawbacks and provides a solder electrode layer structure that does not cause cracks. This invention will be explained below.

第４図にこの発明の一実施例における下地金属
層の平面図を示す。この実施例は、半田電極層６
の外周寸法は第３図と同じであるが、４分割する
ことによつて各下地金属層５の寸法を小さくし、
熱膨張時に受ける力を小さくするものである。こ
の場合、下地金属層５を分割している隙間を適当
に選ぶことによつて半田丘すなわち半田電極層６
を一体のものとして第５図に示すように形成する
ことができる。また、完全に隙間を埋めることが
できない場合でも、下地電極層５としての効果は
ほとんど減ぜられることはない。 FIG. 4 shows a plan view of a base metal layer in an embodiment of the present invention. In this embodiment, the solder electrode layer 6
The outer circumferential dimension of is the same as that in FIG. 3, but by dividing it into four, the dimensions of each base metal layer 5 are reduced,
This reduces the force received during thermal expansion. In this case, by appropriately selecting the gap dividing the base metal layer 5, the solder hill, that is, the solder electrode layer 6
can be formed as an integral piece as shown in FIG. Further, even if the gap cannot be completely filled, the effect of the base electrode layer 5 is hardly reduced.

なお、上述した実施例以外にも同様の効果を有
する種々の構造が考えられることは言うまでもな
い。 It goes without saying that in addition to the embodiments described above, various structures having similar effects can be considered.

以上詳細に述べたように、この発明は電極構造
体の下地金属層を２つ以上の領域に分割した構
造、または下地金属層内の少なくとも１部をくり
抜いた構造にしたので、半田電極層周辺のクラツ
クの発生を皆無にし、信頼性の高い電極構造体を
有する半導体装置を実現することができる利点が
ある。 As described in detail above, the present invention has a structure in which the base metal layer of the electrode structure is divided into two or more regions, or a structure in which at least a part of the base metal layer is hollowed out. This has the advantage that the occurrence of cracks can be completely eliminated and a semiconductor device having a highly reliable electrode structure can be realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は一般的な電極層構造の断面図、第２図
は第１図の要部の拡大断面図、第３図は下地金属
層の従来の構造を示す上面図、第４図はこの発明
による下地金属層の実施例をそれぞれ示す上面
図、第５図はこの発明による電極層構造の実施例
を示す断面図である。 図中、１は半導体基板、２は絶縁膜、３は配線
層、４，４′は表面保護膜、５は下地金属層、６
は半田電極層である。なお、図中の同一符号は同
一または相当部分を示す。 Figure 1 is a cross-sectional view of a general electrode layer structure, Figure 2 is an enlarged cross-sectional view of the main part of Figure 1, Figure 3 is a top view showing the conventional structure of the base metal layer, and Figure 4 is this. FIG. 5 is a top view showing an embodiment of the base metal layer according to the invention, and FIG. 5 is a cross-sectional view showing an embodiment of the electrode layer structure according to the invention. In the figure, 1 is a semiconductor substrate, 2 is an insulating film, 3 is a wiring layer, 4 and 4' are surface protection films, 5 is a base metal layer, and 6
is a solder electrode layer. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] １ 電気素子を有する半導体基板上に絶縁膜を介
して配線層を設け、この配線層の所要部を前記電
気素子にオーミツクコンタクトせしめ、前記配線
層をおおつて表面保護膜を形成し、この表面保護
膜は前記配線層の所定部分を露出させる開孔を設
け、この開孔内の前記配線層の所定部分に接触す
るとともに少なくとも一部を前記表面保護膜上に
オーバラツプさせて下地金属層を設け、この下地
金属層に接触して半田電極層を設けたものにおい
て、前記下地金属層を少なくとも２つ以上の領域
に分割したことを特徴とする半導体装置の電極構
造体。1. A wiring layer is provided on a semiconductor substrate having an electric element via an insulating film, a required portion of this wiring layer is brought into ohmic contact with the electric element, a surface protective film is formed over the wiring layer, and a surface protection film is formed over the wiring layer. The protective film is provided with an opening that exposes a predetermined portion of the wiring layer, and a base metal layer is provided in contact with the predetermined portion of the wiring layer within the opening and overlaps at least a portion of the surface protective film. An electrode structure for a semiconductor device comprising a solder electrode layer in contact with the base metal layer, wherein the base metal layer is divided into at least two regions.
JP55183103A 1980-12-23 1980-12-23 Electrode structural body of semiconductor device Granted JPS57106056A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55183103A JPS57106056A (en) 1980-12-23 1980-12-23 Electrode structural body of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55183103A JPS57106056A (en) 1980-12-23 1980-12-23 Electrode structural body of semiconductor device

Publications (2)

Publication Number Publication Date
JPS57106056A JPS57106056A (en) 1982-07-01
JPS6114666B2 true JPS6114666B2 (en) 1986-04-19

Family

ID=16129816

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55183103A Granted JPS57106056A (en) 1980-12-23 1980-12-23 Electrode structural body of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57106056A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6374481U (en) * 1986-10-31 1988-05-18

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5948924A (en) * 1982-09-14 1984-03-21 Nec Corp Positioning mark for electron beam exposure
JPS607758A (en) * 1983-06-27 1985-01-16 Nec Corp Semiconductor device
US5477086A (en) * 1993-04-30 1995-12-19 Lsi Logic Corporation Shaped, self-aligning micro-bump structures
US5767580A (en) * 1993-04-30 1998-06-16 Lsi Logic Corporation Systems having shaped, self-aligning micro-bump structures
US7034402B1 (en) 2000-06-28 2006-04-25 Intel Corporation Device with segmented ball limiting metallurgy
US7180195B2 (en) 2003-12-17 2007-02-20 Intel Corporation Method and apparatus for improved power routing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6374481U (en) * 1986-10-31 1988-05-18

Also Published As

Publication number Publication date
JPS57106056A (en) 1982-07-01

Similar Documents

Publication Publication Date Title
US7443022B2 (en) Board-on-chip packages
US4530152A (en) Method for encapsulating semiconductor components using temporary substrates
US5653891A (en) Method of producing a semiconductor device with a heat sink
US6246114B1 (en) Semiconductor device and resin film
US6461890B1 (en) Structure of semiconductor chip suitable for chip-on-board system and methods of fabricating and mounting the same
US3997963A (en) Novel beam-lead integrated circuit structure and method for making the same including automatic registration of beam-leads with corresponding dielectric substrate leads
JPH10321631A (en) Semiconductor device and its manufacture
JPH06295939A (en) Semiconductor device
KR20040097899A (en) Method of production of semiconductor device
JPS6114666B2 (en)
US5866951A (en) Hybrid circuit with an electrically conductive adhesive
JPS62136049A (en) Manufacture of semiconductor device
JP3686047B2 (en) Manufacturing method of semiconductor device
JPH0758112A (en) Semiconductor device
JP2001230267A (en) Semiconductor device and manufacturing method
JPH0677631A (en) Mounting method of chip component onto aluminum board
JP3258564B2 (en) Semiconductor device and manufacturing method thereof
JP3855941B2 (en) Manufacturing method of semiconductor device with convex heat sink
JP4175339B2 (en) Manufacturing method of semiconductor device
JPH0661404A (en) Semiconductor device
JPH0244145B2 (en)
JP2600898B2 (en) Thin package device
JP2636808B2 (en) Semiconductor device
JP2797269B2 (en) Semiconductor device
JP2000068423A (en) Semiconductor device and manufacture thereof