JPS59210691A - Circuit board for carrying semiconductor element - Google Patents

Circuit board for carrying semiconductor element

Info

Publication number
JPS59210691A
JPS59210691A JP8549083A JP8549083A JPS59210691A JP S59210691 A JPS59210691 A JP S59210691A JP 8549083 A JP8549083 A JP 8549083A JP 8549083 A JP8549083 A JP 8549083A JP S59210691 A JPS59210691 A JP S59210691A
Authority
JP
Japan
Prior art keywords
semiconductor element
wiring board
weight
parts
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8549083A
Other languages
Japanese (ja)
Inventor
堀部 芳幸
上山 守
正則 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP8549083A priority Critical patent/JPS59210691A/en
Publication of JPS59210691A publication Critical patent/JPS59210691A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は、半導体素子搭載用配線板の改良に関する。[Detailed description of the invention] The present invention relates to improvements in wiring boards for mounting semiconductor elements.

従来の半導体素子搭載用配線板(以下配線板という)は
、第1図に示すように、半導体素子搭載用パッド1を有
する半導体素子搭載部分4と、導体2を有する配線部分
とを構成する基材には同一材料例えばアルミナセラミッ
クスの絶縁体3が用いられている。第2図に示す搭載し
た半導体素子5から発生する熱の放散性は、配線板の基
材となる絶縁体3の熱伝導率に依存する。したがって。
A conventional wiring board for mounting a semiconductor element (hereinafter referred to as a wiring board) has a base that constitutes a semiconductor element mounting part 4 having a semiconductor element mounting pad 1 and a wiring part having a conductor 2, as shown in FIG. The insulator 3 is made of the same material, for example, alumina ceramics. The dissipation of heat generated from the mounted semiconductor element 5 shown in FIG. 2 depends on the thermal conductivity of the insulator 3 serving as the base material of the wiring board. therefore.

絶縁体3の熱伝導率が小さい場合には、半導体素子5か
ら発生する熱の放散の為、冷却片6を取シ付けたり2強
制的に空冷、水冷するなど構造が複雑になる欠点があっ
た。また熱伝導率の高い材料。
If the thermal conductivity of the insulator 3 is low, there is a disadvantage that the structure becomes complicated, such as installing a cooling plate 6 or forcing air cooling or water cooling to dissipate the heat generated from the semiconductor element 5. Ta. It is also a material with high thermal conductivity.

例えば基材全てにベリリアセラツクス又は炭化硅素を用
いれば、ある程度上記の欠点を解消することはできるが
ベリリアセラミックスは非常に高価であり、まだ炭化硅
素は絶縁性を確保するのが困難であるという欠点があっ
た。
For example, if beryllia ceramics or silicon carbide is used as the entire base material, the above drawbacks can be overcome to some extent, but beryllia ceramics are very expensive, and it is still difficult to ensure insulation properties with silicon carbide. There was a drawback.

本発明はこれらの欠点のない配線板を提供することを目
的とするものである。
The object of the present invention is to provide a wiring board free of these drawbacks.

本発明は絶縁体に半導体素子搭載用パッドを有する半導
体素子搭載部分と導体を有する配線部分とを形成してな
る配線板において、半導体素子搭載部分にのみ、配線部
分の絶縁体よシ熱伝導率が高くかつ絶縁性を有するセラ
ミックスを用いてなる配線板に関する。
The present invention provides a wiring board in which a semiconductor element mounting part having a semiconductor element mounting pad and a wiring part having a conductor are formed on an insulator, and only the semiconductor element mounting part has a higher thermal conductivity than the insulator of the wiring part. The present invention relates to a wiring board using ceramics having high insulation properties and high insulation properties.

本発明において導体としては銅、銀、銀−パラジウム、
金、タングステン、モリブデン等が用いられ、tた導体
を有する配線部分の絶縁体とじてはアルミナ、ガラスセ
ラミックス、フェノール樹脂、ガラス−エポキシ樹脂等
が用いられる。更に半導体素子搭載部分に用いられるセ
ラミックスとしては、炭化硅素、窒化硅素、べIJ I
Jア等の焼結体があるが1本発明では配線部分の絶縁体
より熱伝導率が高くかつ絶縁性を有することが必要であ
り、これらの条件を満たす焼結体として半導体素子に用
いられるシリコン単結晶の熱膨張係数3〜4 X 10
−’/℃に近くかつ1010Ωα以上の絶縁性を有する
炭化硅素焼結体を用いることが信頼性の点で好ましい。
In the present invention, conductors include copper, silver, silver-palladium,
Gold, tungsten, molybdenum, etc. are used, and alumina, glass ceramics, phenol resin, glass-epoxy resin, etc. are used as the insulator for the wiring portion having the conductor. Furthermore, the ceramics used for the semiconductor element mounting part include silicon carbide, silicon nitride, and silicon carbide.
There are sintered bodies such as JA, but in the present invention, it is necessary that the sintered body has higher thermal conductivity and insulation properties than the insulator of the wiring part, and it is used in semiconductor devices as a sintered body that satisfies these conditions. Thermal expansion coefficient of silicon single crystal 3-4 x 10
In terms of reliability, it is preferable to use a silicon carbide sintered body having an insulating property close to -'/°C and 1010 Ωα or more.

以丁9本発明の実施例を図面を引用して説明する。Embodiments of the present invention will be described with reference to the drawings.

実施例1 配線板となる基材として、アルミナ96重量部。Example 1 96 parts by weight of alumina as a base material for a wiring board.

焼結助剤としてアルミナ(24,5重量%)、シリカ(
47,9重量%)、マグネシア(18,7重量%)。
Alumina (24.5% by weight) and silica (
47.9% by weight), magnesia (18.7% by weight).

カルシア(8,9重量1から成るガラス粉末4重量部、
結合剤としてブチラール樹脂8重量部、可塑剤としてフ
タル酸エステル系可塑剤DOP5重量部及び溶剤として
、ブタノール20fjft部、)リクロルエチレン50
重量部を添加しボールミルにて均一に混合してスリップ
とし、テープキャスティング法によりグリーンシートを
得た。
Calcia (4 parts by weight of glass powder consisting of 8,9 parts by weight,
8 parts by weight of butyral resin as a binder, 5 parts by weight of phthalate plasticizer DOP as a plasticizer, and 20 parts by weight of butanol as a solvent, 50 parts by weight of dichlorethylene
Parts by weight were added and mixed uniformly in a ball mill to form a slip, and a green sheet was obtained by tape casting.

上記とは別にアルミナ96重量部、上記と同じ成分のガ
ラス粉末4重量部、ブチラール樹脂8重量部、フタル酸
エステル系可塑剤DOP 5重量部。
In addition to the above, 96 parts by weight of alumina, 4 parts by weight of glass powder having the same components as above, 8 parts by weight of butyral resin, and 5 parts by weight of phthalate plasticizer DOP.

カルピトールアセテート15重量部、テルピネオール2
0重量部を添加し、らいかい機にて均一に混合して絶縁
ペーストを得た。次に第3図および第4図に示す形状に
前述のグリーンシート7を打ち抜いた後第5図に示す如
く前述のグリーンシート70片面にタングステンペース
ト(アサヒ化学製、商品名3TW−10001を印刷し
て導体2を形成し、その上面に前述の絶縁ベース)−1
印刷し絶縁層9を形成した。なおスルホール10には上
層との導通を得るため前述のタングステンペーストを印
刷した。この工程を2回くり返した後、最上層に前述の
タングステンペーストを印刷して第5図に示すものを得
た。
15 parts by weight of carpitol acetate, 2 parts by weight of terpineol
0 parts by weight was added and mixed uniformly in a sieve machine to obtain an insulating paste. Next, after punching out the above-mentioned green sheet 7 into the shape shown in FIGS. 3 and 4, tungsten paste (manufactured by Asahi Chemical, trade name 3TW-10001) was printed on one side of the above-mentioned green sheet 70 as shown in FIG. to form a conductor 2, and the above-mentioned insulating base)-1 is formed on the top surface of the conductor 2.
An insulating layer 9 was formed by printing. Note that the above-mentioned tungsten paste was printed on the through holes 10 in order to obtain conduction with the upper layer. After repeating this process twice, the above-mentioned tungsten paste was printed on the top layer to obtain what is shown in FIG.

次に第6図に示すように貫通孔8に1010Ωmの絶縁
性を有するSiC焼結体11(日立製作所、商品名8C
−1011の側面に前述の絶縁ペースト12を印刷した
ものを挿入した。その後弱還元性雰囲気中にて1600
℃で30分保持して焼成し第7図に示す本発明になる配
線板を得た。なお第7図において、13ばSiC焼結体
と配線とを形成したアルミナ焼結体との接合部である。
Next, as shown in FIG. 6, a SiC sintered body 11 (Hitachi, trade name: 8C
-1011, the above-mentioned insulating paste 12 printed on the side surface was inserted. After that, it was heated to 1600 in a weakly reducing atmosphere.
C. for 30 minutes and fired to obtain a wiring board according to the present invention shown in FIG. In FIG. 7, reference numeral 13 indicates a joint between the SiC sintered body and the alumina sintered body on which the wiring is formed.

14はアルミナの焼結体である。14 is a sintered body of alumina.

実施例2 配線板となる基材として実施例1で使用したグリーンシ
ートを用い、実施例1と同様な工程で第5図に示すもの
を得た。これを弱還元性雰囲気中にて1600℃で30
分保持して焼成し1貫通孔8付きの配線板を得た。この
貫通孔8に実施例1−り・ で使用したSiC焼結体11の側面に、シリカ33重量
部、アルミナ45重量部、酸化鉛10重量部。
Example 2 The green sheet used in Example 1 was used as a base material for a wiring board, and the same process as in Example 1 was carried out to obtain the one shown in FIG. 5. This was heated at 1600℃ for 30 minutes in a slightly reducing atmosphere.
A wiring board with one through hole 8 was obtained by holding and firing for 1 minute. In this through hole 8, 33 parts by weight of silica, 45 parts by weight of alumina, and 10 parts by weight of lead oxide were added to the side surface of the SiC sintered body 11 used in Example 1.

カルシア3.5重量部、酸化ホウ素3.0重量部から成
るガラスペーストを印刷したものを挿入した。
A printed glass paste consisting of 3.5 parts by weight of calcia and 3.0 parts by weight of boron oxide was inserted.

その後窒素雰囲気中にて900℃で焼成し、第7図に示
す本発明になる配線板を得た。
Thereafter, it was fired at 900° C. in a nitrogen atmosphere to obtain a wiring board according to the present invention shown in FIG.

実施例3 実施例2で用いた配線板の貫通孔8にSiC焼結体11
のかわりにべIJ IJア焼結体の側面に実施例2で用
いたガラスペーストを印刷したものを挿入した。その後
窒素雰囲気中にて900℃で焼成し。
Example 3 SiC sintered body 11 was placed in the through hole 8 of the wiring board used in Example 2.
Instead, the glass paste used in Example 2 was printed on the side surface of the sintered body. Thereafter, it was fired at 900°C in a nitrogen atmosphere.

第7図に示す本発明になる配線板を得た。A wiring board according to the present invention shown in FIG. 7 was obtained.

次に実施例1,2および3で得られた配線板に第8図に
示す如く無電解ニッケルメッキ15を施し、その上に金
メッキ16を施した。その後SiC焼成体11およびベ
リIJア焼結体上部のチップ搭載部に金ペーストを印刷
後850℃で焼成してチップ搭載用パッド1を得だ。次
に半導体素子5を金−シリコンの共晶ポンディグにより
チップ搭載用パッド1に搭載し、金ワイヤ17をワイヤ
ポンディングした。さらにアルミニウムの冷却片6をシ
リコンゴム系接着剤を用いて配線板に接着して半導体装
置を得た。なお第81図において18は配線板と冷却片
6との接合部である。
Next, as shown in FIG. 8, electroless nickel plating 15 was applied to the wiring boards obtained in Examples 1, 2, and 3, and gold plating 16 was applied thereon. Thereafter, gold paste was printed on the chip mounting portion of the SiC sintered body 11 and the top of the Veri IJ sintered body, and then fired at 850° C. to obtain the chip mounting pad 1. Next, the semiconductor element 5 was mounted on the chip mounting pad 1 by gold-silicon eutectic bonding, and the gold wire 17 was wire bonded. Further, the aluminum cooling piece 6 was adhered to a wiring board using a silicone rubber adhesive to obtain a semiconductor device. In FIG. 81, reference numeral 18 indicates a joint between the wiring board and the cooling piece 6.

次に基材にアルミナセラミックを用いた従来の配線板と
本発明になる実施例1,2および3によって得られた配
線板について熱抵抗(θja)を測定した結果、熱の放
散性は第1表に示すごとく。
Next, as a result of measuring the thermal resistance (θja) of the conventional wiring board using alumina ceramic as the base material and the wiring board obtained in Examples 1, 2, and 3 according to the present invention, the heat dissipation performance was the first. As shown in the table.

大幅に改善できた。I was able to improve it significantly.

本発明は、半導体素子搭載部分のみ、配線部分の絶縁体
より熱伝導率が高く、かつ絶縁性を有するセラミックス
を用いるため、搭載した半導体素子から発生する熱の放
散性が良好となる。また多数個の半導体素子を同一の配
線板に搭載しても。
In the present invention, since ceramics having higher thermal conductivity and insulating properties are used only in the semiconductor element mounting portion than the insulator in the wiring portion, the heat dissipation property generated from the mounted semiconductor element is improved. Also, even if a large number of semiconductor elements are mounted on the same wiring board.

絶縁性を有するセラミックスに搭載するため、各素子の
絶縁は十分確保される。更に半導体素子搭載部分のみ熱
伝導率の高いセラミックスを用いるため、基材全てにベ
リリアセラミックスを用いだ配線板に比較し安価に製造
できる。
Since it is mounted on insulating ceramics, sufficient insulation of each element is ensured. Furthermore, since ceramics with high thermal conductivity are used only in the part where the semiconductor elements are mounted, it can be manufactured at a lower cost than wiring boards that use beryllia ceramics for the entire base material.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の配線板の断面図、第2図は第1図に示す
従来の配線板に半導体素子を搭載し、冷却片を取付けた
半導体装置の断面図、第3図は本発明の配線板に用いら
れるグリーンシートの上面図、第4図は第3図のA−A
’断面図、第5図および第6図は本発明の実施例になる
配線板の製造工程を示す断面図、第7図は本発明の実施
例になる配線板の断面図、第8図は、第7図に示す本発
明によって得られた配線板に半導体素子を搭載し。 冷却片を取付けた半導体装置の断面図である、符号の説
明 1・・・半導体素子搭載用パッド 2・・・導体      3・・・絶縁体4・・・半導
体素子搭載部分 5・・・半導体素子   6・・・冷却片7・・・グリ
ーンシート 8・・・貫通孔9・・・絶i層     
10・・・スルホール11・・・SiC焼結体  12
・・・絶縁ペースト13・・・接合部     14・
・・焼結体15・・・ニッケルメッキ16・・・金メッ
キ17・・・金ワイヤ    18・・・接合部4 71 図 茅 3 図 輩+回 438−
FIG. 1 is a sectional view of a conventional wiring board, FIG. 2 is a sectional view of a semiconductor device in which a semiconductor element is mounted on the conventional wiring board shown in FIG. A top view of the green sheet used for wiring boards, Figure 4 is A-A in Figure 3.
5 and 6 are cross-sectional views showing the manufacturing process of a wiring board according to an embodiment of the present invention, FIG. 7 is a cross-sectional view of a wiring board according to an embodiment of the present invention, and FIG. , a semiconductor element was mounted on a wiring board obtained according to the present invention as shown in FIG. This is a cross-sectional view of a semiconductor device with a cooling piece attached. Explanation of symbols 1...Semiconductor element mounting pad 2...Conductor 3...Insulator 4...Semiconductor element mounting portion 5...Semiconductor element 6...Cooling piece 7...Green sheet 8...Through hole 9...I-layer
10...Through hole 11...SiC sintered body 12
... Insulating paste 13 ... Joint part 14.
...Sintered body 15...Nickel plating 16...Gold plating 17...Gold wire 18...Joint portion 4 71 Fig. 3 Fig. 3 Fig. 438-

Claims (1)

【特許請求の範囲】 1、絶縁体に半導体素子搭載用パッドを有する半導体素
子搭載部分と導体を有する配線部分とを形成してなる半
導体素子搭載用配線板において。 半導体素子搭載部分にのみ、配線部分の絶縁体より熱伝
導率が高くかつ絶縁性を有するセラミックスを用いてな
る半導体素子搭載用配線板。
[Scope of Claims] 1. A wiring board for mounting a semiconductor element, which includes a semiconductor element mounting part having a semiconductor element mounting pad and a wiring part having a conductor formed on an insulator. A wiring board for mounting a semiconductor element, which uses ceramics having higher thermal conductivity and insulation properties than the insulator of the wiring part only in the semiconductor element mounting part.
JP8549083A 1983-05-16 1983-05-16 Circuit board for carrying semiconductor element Pending JPS59210691A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8549083A JPS59210691A (en) 1983-05-16 1983-05-16 Circuit board for carrying semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8549083A JPS59210691A (en) 1983-05-16 1983-05-16 Circuit board for carrying semiconductor element

Publications (1)

Publication Number Publication Date
JPS59210691A true JPS59210691A (en) 1984-11-29

Family

ID=13860364

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8549083A Pending JPS59210691A (en) 1983-05-16 1983-05-16 Circuit board for carrying semiconductor element

Country Status (1)

Country Link
JP (1) JPS59210691A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0982857A (en) * 1995-09-18 1997-03-28 Nec Corp Multi-chip package structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0982857A (en) * 1995-09-18 1997-03-28 Nec Corp Multi-chip package structure

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