JP2000252391A - Wiring board for mounting semiconductor device and its mounting structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase reliability in connection (continuity of connection terminals) between a package and a circuit board. SOLUTION: In a package A having a mounting structure H1 for a wiring board for mounting a semiconductor device, a semiconductor device B is mounted on an insulating substrate 1, and connection electrodes 8 of the semiconductor device B and a metallized interconnection layer 2 of the insulating substrate 1 are connected by wires 9. Then, the entire body is covered with a sealing layer 10 and a plurality of stress reducing recesses 13 are formed on the surface of the sealing layer 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board on which a semiconductor element is mounted, and in which a semiconductor element is fixed on a surface-mount type insulating substrate (wiring board) having a high thermal expansion characteristic and sealed with a thermosetting resin. The present invention relates to a semiconductor element mounting wiring board and a mounting structure thereof.

[0002]

2. Description of the Related Art A wiring board has a structure in which a metallized wiring layer is provided on the surface or inside of an insulating substrate. As a typical example, a semiconductor element, particularly a semiconductor integrated circuit such as an LSI (large-scale integrated circuit element) is used. There is a semiconductor device housing package for housing an element.

In a package for housing a semiconductor element, a plurality of metallized wiring layers made of a refractory metal powder such as tungsten or molybdenum are provided on the surface and inside of an insulating substrate made of alumina ceramics, and a connection formed on the semiconductor element is formed. The electrode for use and the metallized layer formed around the element mounting portion on the package side are connected by wires. According to such a wire bonding method, a thermosetting resin is applied onto a package, a semiconductor element is mounted via the thermosetting resin, and the resin is cured to fix the semiconductor element.

In general, as the degree of integration of semiconductor devices increases,
The number of electrodes formed on the semiconductor element increases, and the number of terminals in the semiconductor storage package also increases. further,
The size of the package is required year by year, and in recent years, a chip size package (CSP) in which a chip area of a semiconductor element reaches 50% or more of the package area is mainly used.

In some cases, a package (wiring board) to which a semiconductor element is fixed is mounted on an external electric circuit board for a motherboard. In this case, a connection terminal formed on the bottom of the wiring board and an external electric circuit The wiring conductor formed on the substrate is electrically connected and mounted by a conductive adhesive such as a brazing material. This external electric circuit board is composed of a composite material of glass such as a printed board and a synthetic resin.

[0006]

However, in a wiring board having connection terminals formed at a high density, such as a ball grid array (BGA), the insulating substrate is formed of ceramics such as alumina and mullite. However, when such a wiring board is surface-mounted on an external electric circuit board such as a printed circuit board containing an organic resin such as a glass-epoxy resin composite material, heat generated during operation of the semiconductor element is generated by the insulating substrate and the external electric circuit board. Is repeatedly applied to both of them, and a thermal stress is generated due to a difference in thermal expansion coefficient between the two, and the thermal stress causes the connection terminal to peel off from the insulating substrate or to cause a crack or the like at a connection portion of the connection terminal. Therefore, there is a problem that the wiring board is not stably fixed on the external electric circuit board for a long time.

In order to solve this problem, the insulating substrate is formed of a high thermal expansion glass ceramic instead of ceramics such as alumina and mullite, thereby reducing the thermal expansion difference between the wiring substrate and the external electric circuit substrate. A technique for improving connection reliability has been proposed (Japanese Patent Laid-Open No. 8-27).
9574 and Japanese Patent Application No. 8-322038).

However, even when such an insulating substrate made of a high thermal expansion material is used, in a structure in which wires and semiconductor elements are sealed with a thermosetting resin, when a wiring board is surface-mounted on an external electric circuit board, the The heat generated during the operation of the element, resulting in a large difference in the coefficient of thermal expansion and the Young's modulus between the thermosetting resin and the insulating substrate. There is a problem that stress concentrates on the interface, the connection terminal peels off from the insulating substrate, and the electrical connection state cannot be stably maintained for a long time.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor element wiring board excellent in long-term reliability in which deformation of a wiring board (insulating substrate) is made as small as possible, and an electric connection state is stably maintained for a long time. It is to provide the mounting structure.

[0010]

According to the present invention, there is provided a wiring board for mounting a semiconductor element, wherein a semiconductor element is fixed via an adhesive on a wiring board having a metallized wiring layer formed on an insulating substrate, and the metallized wiring layer and the semiconductor are mounted on the wiring board. The element and the element are electrically connected by a wire, and the wire and the semiconductor element are sealed with a sealing layer made of a thermosetting resin, and a plurality of grooves are provided on the surface of the sealing layer. It is characterized by.

Further, according to the mounting structure of a semiconductor element mounting wiring board of the present invention, a semiconductor element is fixed via an adhesive on a wiring board formed by forming a metallized wiring layer on an insulating substrate, and the metallized wiring layer is connected to the semiconductor element. And a semiconductor element mounting wiring board in which the wires and the semiconductor elements are electrically sealed by a sealing layer made of a thermosetting resin, which is composed of an insulating plate made of a composite material of glass and synthetic resin. And a plurality of grooves are provided on the surface of the sealing layer.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A ball grid array (BGA) type chip size package will be described as an example of a semiconductor element mounting wiring board of the present invention with reference to FIGS.
FIG. 1 is a sectional view of a mounting structure H1 of a semiconductor element mounting wiring board, and FIGS. 2 (1) to (3) are perspective views showing a manufacturing process thereof. FIG. 3 is a cross-sectional view of a mounting structure H2 of another semiconductor element mounting wiring board, and FIGS. 4 to 12 are plan views showing patterns of grooves formed on the surface of the sealing layer.

[0013] In the semiconductor element mounting wiring board mounting a semiconductor element wiring mounting structure H1 of the substrate, A is BGA type package which is a semiconductor element mounting wiring board, B is a semiconductor device, C is a circuit board, the package A Will be described.

A metallized wiring layer 2 connected to the semiconductor element B is formed on the surface of the insulating substrate 1, and connection pads 6 for connecting to the circuit board C are mounted on the bottom surface. The metallized wiring layer 2 and the metallized wiring layer 4 formed inside the insulating substrate 1 are electrically connected to connection pads 6 through via hole conductors 5. The connection terminal 3 is formed of a ball-shaped solder ball, and is attached to the connection pad 6 by solder or the like.

The semiconductor element B is made of a silicon (Si) material and is bonded and fixed to the surface of the insulating substrate 1 with, for example, a thermosetting resin 7. The use of a novolak type epoxy or a bisphenol A type epoxy resin as the thermosetting resin 7 is advantageous in that the adhesiveness to the insulating substrate 1 is excellent. Also,
The semiconductor element B is provided with a connection electrode 8 and is electrically connected to the metallized wiring layer 2 by a wire 9.
Further, the semiconductor element B and the wire 9 are covered with a sealing layer 10 made of a sealing resin. Such a sealing resin is formed of epoxy resin, phenol resin, urea resin, melanin resin, polyimide resin, silicone resin, unsaturated polyester resin, diallyl phthalate resin, polyurethane resin, etc. An epoxy resin such as a mold epoxy is preferred.

In order to mount the semiconductor element B on the package A, an uncured (soft state) thermosetting resin is applied to the surface of the insulating substrate 1, and then the semiconductor element B is placed and adhered. The thermosetting resin is cured and fixed by heating at a temperature of about 200 ° C. After that, the connection electrode 8 of the semiconductor element B and the metallized wiring layer 2 of the package A are connected by the wire 9, and a sealing material made of a thermosetting resin is applied to seal and cure, thereby sealing. A stop layer 10 is formed.

A plurality of stress relaxation grooves 13 are formed on the surface of the sealing layer 10 before or after the sealing material is cured.

In order to form the stress relaxation groove 13 before the sealing layer 10 is cured, a jig provided with a projection pattern corresponding to the pattern of the stress relaxation groove 13 is pressed after applying the sealing material, Then it is cured. After the curing, the stress relief grooves 13 are formed in the pattern of the stress relief grooves 13 using a rotary blade, a laser, or the like.

FIGS. 4 to 12 show stress relief grooves 13a to 13i as typical examples of such stress relief grooves 13. FIG. The stress relaxing groove 13a shown in FIG. 4 has a lattice shape, the stress relaxing groove 13b of FIG. 5 has an annular shape, the stress relaxing groove 13c of FIG. 6 has a combination of two lattice shapes, and the stress relaxing groove 13d of FIG. It is formed obliquely. The stress relaxation grooves 13e, 13f, and 13g shown in FIGS. 8 to 10 are formed in a rectangular shape, a diagonal shape, and an annular shape by broken lines. Stress relief groove 1 shown in FIG.
3h, radial grooves are formed as stress relief grooves 13i shown in FIG.
Then, a cross-shaped groove is formed.

Thus, according to the package A, the sealing layer 1
By forming a plurality of stress relaxation grooves 13 on the surface of the package A either before or after the sealing material is cured, stress can be absorbed even if the package A is warped.

The width of the stress relaxation groove 13 is 0.02 to 0.2 m
m, preferably 0.05-0.1 mm, depth 0.02-
0.3 mm, preferably 0.05 to 0.1 mm.

When the width of the stress relaxation groove 13 is less than 0.02 mm, the relaxation effect is not remarkably exhibited, and the insulating substrate is deformed and broken. If the thickness exceeds 0.2 mm, the width is too wide, and the groove is broken by stress, and the substrate itself is broken.

When the depth of the stress relaxation groove 13 is less than 0.02 mm, the relaxation effect is not remarkably exhibited, and the insulating substrate is deformed and destroyed. If it exceeds 0.3 mm, the groove is too deep, so that the groove is broken by the stress and the substrate itself is broken.

Although the warpage of the insulating substrate 1 is absorbed by the sealing layer 10, a remarkable effect is obtained as the difference in thermal expansion coefficient between the sealing layer 10 and the insulating substrate 1 increases. In particular, the difference in thermal expansion coefficient between the sealing layer 10 and the insulating substrate 1 is 5 ppm / ° C.
Above, the most remarkable effect can be obtained because the warpage is not sufficiently absorbed by the sealing layer 10.

Method of Manufacturing Package A The insulating substrate 1 is made of, for example, a high thermal expansion ceramic material, and includes lithium silicate glass, PbO glass, Z
For glass components such as nO-based glass and BaO-based glass,
Enstatatite, forsterite, SiO ₂ (quartz, tridymite, cristobalite), MgO,
Those obtained by combining various fillers such as ZrO ₂ and petalite are preferable (see JP-A-63-117929).

For example, 20 to 90% by volume of a glass component,
An organic binder is added to a mixture of 80 to 10% by volume of a filler to prepare a slurry, and the slurry is formed into a sheet. Then, a low-resistance metal such as copper, gold, or silver is coated on the surface of the sheet-shaped formed body. The conductive paste containing is printed and applied.
Further, if necessary, a through hole is formed in a predetermined portion of the sheet-like molded body by a microdrill, a laser, or the like, and the hole is filled with the conductive paste. Then, a plurality of the sheet-shaped molded bodies are laminated and pressed to produce a laminated body. Thereafter, degreasing is performed in a nitrogen atmosphere or a nitrogen atmosphere containing water vapor, and then baked at a temperature of 800 to 1000 ° C. to obtain a package A. .

When the insulating substrate 1 is made of a material having a thermal expansion coefficient of 8 to 18 ppm / .degree. C. at 40 to 400.degree. C., the thermosetting resin 7 has a thermal expansion coefficient of 20 to 40.degree. To 70 ppm / ° C., whereby the gap between the insulating substrate 1 and the thermosetting resin 7, the gap between the thermosetting resin 7 and the semiconductor element B, the sealing layer 10
There is an advantage that stress generated between the substrate and the insulating substrate 1 is reduced, and separation or the like hardly occurs at each interface.

Such a thermosetting resin 7 is prepared by adding a small amount of a curing agent to an epoxy resin such as a bisphenol A type epoxy or a novolak type epoxy to have an average particle size of 3 to 50 μm.
m of silica or alumina powder from 30 to
What contained 90 weight% should just be used.

[0029] illustrating the mounting structure H1 of the semiconductor element mounting wiring board on which the package A semiconductor element mounting wiring board of the mounting structure H1 then the configuration on the circuit board C. The circuit board C contains at least one kind of thermosetting resin selected from an epoxy resin, a phenol resin, an aramid resin, a polyimide resin, and a polyolefin resin as an organic resin such as a printed board, and further includes glass-epoxy containing glass as a filler component. Cu, Au, Al, Ni, Pb-Sn are formed on the surface of an insulating substrate 11 made of a material containing an organic resin such as a resin or a glass-polyimide resin composite material.
And a wiring layer 12 containing at least one metal selected from the group consisting of:

Then, on the wiring layer 12 of the circuit board C,
When the connection terminals 3 of the package A are electrically connected via a brazing material such as solder, the package A
Implemented above.

In the package A and the mounting structure H1, the insulating substrate 1 is preferably made of a material having a coefficient of thermal expansion of 8 to 18 ppm / ° C. at 40 to 400 ° C., particularly ceramics. That is, usually, the semiconductor element B
The thermal expansion coefficient of the insulating substrate 1 is 2 to 3 ppm / ° C., the thermal expansion coefficient of the sealing layer 10 is 15 to 70 ppm / ° C., and the thermal expansion coefficient of the circuit board C is 12 to 18 ppm / ° C. By setting the coefficient to 8 to 18 ppm / ° C., the stress is reduced overall. The thermal expansion coefficient of the insulating substrate 1 is 8 pp
When the temperature is less than m / ° C., high stress is likely to be generated in the connection terminal between the circuit board C and the sealing layer 10, and the pressure is 18 pp.
If it exceeds m / ° C., the stress with the semiconductor element B tends to increase.

The mounting structure H1 of the semiconductor element mounting wiring board
Manufacturing Method A manufacturing process of the mounting structure H1 having the above configuration will be described with reference to FIG. In order to obtain four mounting structures H1, four insulating substrates 1 on each of which a semiconductor element B is mounted are arranged on a base substrate 14 as shown in FIG.
The wire 9 is connected, and then a thermosetting resin 15 is applied and cured as shown in FIG. 2B, and then cut along the broken line, and the semiconductor element is mounted as shown in FIG. The mounting structure H1 of the wiring board is obtained.

Next , the mounting structure H2 of another semiconductor element mounting wiring board will be described with reference to FIG. The mounting structure H2 is different from the mounting structure H1 of the semiconductor element mounting wiring board in a manufacturing method. The same parts as those of the mounting structure H1 of the semiconductor element mounting wiring board are denoted by the same reference numerals.

In the mounting structure H2 of the semiconductor element mounting wiring board, the semiconductor element B is mounted on the insulating substrate 1 which has been cut into pieces before sintering or cut or snapped after sintering. Subsequently, the wire 9 is wire-bonded, and a thermosetting resin is applied and cured so as to cover the wire 9 and the semiconductor element B, thereby forming the package A1 without the sealing layer 10. This package A1
Is mounted on a circuit board C prepared in advance.

When comparing the mounting structure H1 of the semiconductor element mounting wiring board and the mounting structure H2 of the semiconductor element mounting wiring board, a difference occurs in the method of applying the thermosetting resin for the sealing layer 10 between the two. As a result, the amount of the thermosetting resin used for the sealing layer 10 used in the mounting structure H2 of the semiconductor element mounting wiring board is reduced, thereby reducing the generated stress.

[0036]

EXAMPLE 1 A mounting structure H2 of a semiconductor element mounting wiring board in which a stress relaxation groove 13c as shown in FIG. 6 was formed in the sealing layer 10 was manufactured, and a heat cycle test was performed.

The insulating substrate 1 forming the package A1 is made of glass ceramic (lithium silicate-based, lead-based, zirconia-based glass, and the like, and filler such as silica-based or forsterite-added). The expansion coefficient was 11.5 ppm / ° C. Simultaneous firing at a temperature of 900 ° C. at the time of manufacturing the insulating substrate 1 using such a material allows the metallized wiring layer 2 and 144 connection pads 6 on the surface of the insulating substrate 1, A metallized wiring layer 4 and a via-hole conductor 5 are formed inside by printing or filling with a copper paste to obtain a package A1.

Next, a high melting point solder ball (Sn: Pb weight ratio = 10: 90, diameter: 0.5 m) is provided on each connection pad 6 via a low melting point solder (Sn: Pb weight ratio = 63: 37).
m) was attached to form package A1. Such package dimensions are 13 mm × 13 mm × 0.4 mm.

8 mm ×
An 8 mm semiconductor element B (made of silicon (Si) having a thermal expansion coefficient of 2.6 ppm / ° C. at 40 to 400 ° C.) is mounted via a thermosetting resin 7 made of bisphenol-type epoxy.

Thereafter, the connection electrode 8 and the metallized wiring layer 2 are electrically connected by the wire 9, and the semiconductor element B and the wire 9 are thermosetting resin made of a novolak-type epoxy resin containing 80% by weight of a silica filler. And sealing with a sealing layer 10 (thermal expansion coefficient: 19.5 ppm / ° C.).

Subsequently, various jigs having various projection patterns of different sizes are pressed against the applied sealing layer 10 and then cured, whereby the width of the stress relief groove 13 is changed as shown in Table 1. And a package A1 having a different depth. After the thermosetting resin of the sealing layer 10 is cured,
Even when the pattern of the stress relaxation groove 13 was formed by using a rotary blade or a laser, no difference was observed in the characteristics due to the difference between the two forming methods.

[0042]

[Table 1]

The various packages A1 (Sample Nos. 1 to 13) thus obtained were subjected to a durability test called a heat cycle test. Sample No. 1 is stress relief groove 1
3 is not formed.

In the thermal cycle test, both the secondary mounting cycle life and the wire electrical connection thermal cycle life were measured and evaluated.

The secondary mounting cycle life is defined as package A1.
Life of the connection terminal 3 that electrically connects the circuit board C to the connection terminal 3, and the connection terminal 3
A stress is generated by a temperature cycle test due to a difference in thermal expansion coefficient between the substrate and the circuit board C, and the resulting durability is evaluated.

The wire electrical connection thermal cycle life is the life of the wire 9 breaking. That is, the wire is not broken when the thickness (amount) of the sealing layer 10 is sufficient, but the thickness of the sealing layer 10 is reduced by providing the stress relaxation groove as in the present invention. Although high stress is generated, the durability of such a wire is evaluated.

In these thermal cycle tests, the mounting structure H2 of each semiconductor element mounting wiring board in which various packages A1 were mounted on the circuit board C was held at -40 ° C. for 25 minutes in the air atmosphere. 125
By holding at 25 ° C. for 25 minutes, one cycle was performed, and an experiment in which such a cycle was repeated up to 3,000 times was performed. In order to evaluate the secondary mounting cycle life, a test was conducted between the package A1 and the circuit board C. The connection state (energization of the connection terminal 3) and the connection state (energization of the wire 9) between the connection electrode 8 of the semiconductor element B and the metallized wiring layer 2 of the package A1 were measured every 50 cycles.

As is clear from the results shown in Table 1, the sample No. 2-No. In No. 13, all of them have excellent heat cycle durability, that is, when the temperature changes from a high temperature to a low temperature, the sealing layer 10 is largely contracted and deformed.
High stress is generated at the interface between the package A1 and the sealing layer 10, and the stress causes the package A1 to be deformed so as to be lifted at the peripheral portion. The deformation causes the connection terminal 3 particularly located at the package peripheral portion. Although high stress is generated and cracks are generated in the connection terminals 3 and disconnection is easily caused, deformation of the sealing layer 10 is reduced by providing the stress relaxation grooves, and stress generated in the connection terminals 3 is reduced. As a result, excellent characteristics of 1400 cycles or more in secondary mounting cycle life were obtained. On the other hand, the conventional sample No. 1
Then, it was up to 1000 cycles. Further, according to the present invention, a characteristic of a secondary mounting cycle life of 1200 cycles or more was obtained.

Example 2 The insulating substrate 1 used in Example 1 was made of glass ceramics and had a coefficient of thermal expansion of 11.5 ppm / ° C. The expansion coefficient is 6.0 ppm /
° C. Then, as shown in Table 2, a package A1 having different widths and depths of the stress relaxation grooves 13 was manufactured.
14 to sample no. 26) Similarly, when the secondary mounting cycle life and the wire electrical connection thermal cycle life were measured,
The results as shown in Table 2 were obtained. The sample No. 1
4 shows a case where the stress relaxation groove 13 is not formed.

[0050]

[Table 2]

As is clear from this table, the sample No. of the present invention. 15-No. 26, all have excellent heat cycle durability, and the secondary mounting cycle life is 11
Excellent characteristics of 00 cycles or more were obtained. On the other hand, the conventional sample No. 14 was up to 700 cycles. Further, according to the present invention, the characteristics of the secondary mounting cycle life of 1200 cycles or more were obtained.

(Example 3) In (Example 1), the mounting structure H2 of the semiconductor element mounting wiring board was manufactured. Instead, the mounting structure H1 of the semiconductor element mounting wiring board was manufactured. However, the other structure is exactly the same as the mounting structure H2 of the semiconductor element mounting wiring board. Then, as shown in Table 3, the package A in which the width and the depth of the stress relaxation groove 13 are different.
(Sample No. 27 to Sample No. 39), and the secondary mounting cycle life and the wire electrical connection heat cycle life were similarly measured. The results shown in Table 3 were obtained. The sample No. 27 shows the case where the stress relaxation groove 13 is not formed.

[0053]

[Table 3]

As is clear from this table, the sample No. of the present invention. 28-No. 39, all have excellent heat cycle durability, and the secondary mounting cycle life is 11
Excellent characteristics of 00 cycles or more were obtained. On the other hand, the conventional sample No. 27, it was up to 800 cycles. Further, according to the present invention, a characteristic of a secondary mounting cycle life of 1500 cycles or more was obtained.

(Example 4) In (Example 1), the mounting structure H2 of the semiconductor element mounting wiring board in which the stress relaxation groove 13c was formed as shown in FIG. 6 was manufactured. Instead, as shown in FIG. The mounting structure H2 of the semiconductor element mounting wiring board in which the stress relaxation grooves 13b were formed was manufactured. However, other structures are exactly the same as in (Example 1). And Table 4
As shown in the figure, a package A having different widths and depths of the stress relaxation grooves 13b was manufactured.
1) Similarly, when the secondary mounting cycle life and the wire electrical connection thermal cycle life were measured, the results shown in Table 4 were obtained.

[0056]

[Table 4]

As is clear from this table, all of the above have excellent heat cycle durability, and have excellent characteristics of 1700 cycles or more in the secondary mounting cycle life. Also,
Regarding the secondary mounting cycle life, a characteristic of 1300 cycles or more was obtained.

It should be noted that the present invention is not limited to the above embodiment, and various changes and improvements may be made without departing from the scope of the present invention. For example, in the above embodiment, the grooves formed on the surface of the sealing layer 10 are formed into linear or broken stress relief grooves 13. However, instead of this, a large number of dot-shaped grooves are randomly arranged, or They may be arranged side by side.

[0059]

As described above, according to the semiconductor element mounting wiring board of the present invention, the wires and the semiconductor element are sealed by the sealing layer made of a thermosetting resin, and a plurality of grooves are formed on the surface of the sealing layer. With this arrangement, even if the wiring board is warped, the accompanying stress is absorbed, and as a result, a highly reliable semiconductor element mounting wiring board can be provided.

Further, according to the mounting structure of the wiring board for mounting a semiconductor element of the present invention, the use of the wiring board for mounting a semiconductor element of the present invention minimizes the deformation of the wiring board. A long-term reliable semiconductor element wiring board mounting structure in which a stable electrical connection state is maintained can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view of a mounting structure of a semiconductor element mounting wiring board of the present invention.

FIGS. 2 (1), (2) and (3) are perspective views showing steps of manufacturing a mounting structure of a semiconductor element mounting wiring board according to the present invention.

FIG. 3 is a sectional view of a mounting structure of another semiconductor element mounting wiring board according to the present invention.

FIG. 4 is a plan view showing a pattern of a groove formed in a sealing layer of the semiconductor element mounting wiring board of the present invention.

FIG. 5 is a plan view showing a pattern of a groove formed in a sealing layer of the semiconductor element mounting wiring board of the present invention.

FIG. 6 is a plan view showing a pattern of a groove formed in a sealing layer of the semiconductor element mounting wiring board of the present invention.

FIG. 7 is a plan view showing a pattern of a groove formed in a sealing layer of the semiconductor element mounting wiring board of the present invention.

FIG. 8 is a plan view showing a pattern of a groove formed in a sealing layer of the semiconductor element mounting wiring board of the present invention.

FIG. 9 is a plan view showing a pattern of a groove formed in a sealing layer of the semiconductor element mounting wiring board of the present invention.

FIG. 10 is a plan view showing a pattern of a groove formed in a sealing layer of the semiconductor element mounting wiring board of the present invention.

FIG. 11 is a plan view showing a pattern of a groove formed in a sealing layer of the semiconductor element mounting wiring board of the present invention.

FIG. 12 is a plan view showing a pattern of a groove formed in a sealing layer of the wiring board for mounting a semiconductor element of the present invention.

[Explanation of symbols]

 H1, H2 Mounting structure of semiconductor element mounting wiring board A package B semiconductor element C circuit board 1 insulating substrate 2, 4, metallized wiring layer 3 connection terminal 5 via hole conductor 6 connection pad 7 thermosetting resin 8 connection electrode 9 wire 10 sealing Stop layer 11 Insulating substrate 12 Wiring layer 13, 13a-13i Stress relaxation groove

Claims (2)

[Claims] A semiconductor device is fixed via an adhesive on a wiring board having a metallized wiring layer formed on an insulating substrate, and the metallized wiring layer and the semiconductor element are electrically connected by wires. A semiconductor element mounting wiring board, wherein a plurality of grooves are provided on a surface of the sealing layer in a semiconductor element mounting wiring board in which an element is sealed with a sealing layer made of a thermosetting resin. 2. A semiconductor device is fixed via an adhesive on a wiring board having a metallized wiring layer formed on an insulating substrate, and the metallized wiring layer and the semiconductor element are electrically connected by wires. A semiconductor element mounting wiring board in which elements are sealed with a sealing layer made of a thermosetting resin, and a semiconductor element mounting wiring board is provided on a circuit board made of an insulating plate made of a composite material of glass and synthetic resin. A mounting structure for a semiconductor element mounting wiring board, wherein a plurality of grooves are provided on the surface of the sealing layer in the mounting structure of the substrate.