JP2011253879A - Semiconductor element and substrate with built-in semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element with a reduced thickness, having strength more efficiently reinforced and suppressing the occurrence of cracks in pickup.SOLUTION: A semiconductor element according to the present invention includes a semiconductor substrate having a circuit surface. In the semiconductor element, the semiconductor substrate is reduced in thickness, and a cured thermosetting resin layer is provided at least on a side of a surface opposite to the circuit surface of the semiconductor substrate.

Description

  The present invention relates to a semiconductor element and a semiconductor-embedded substrate that incorporates the semiconductor element.

  In recent years, a substrate with a built-in semiconductor in which a semiconductor element is built has been proposed for the purpose of further increasing the integration and functionality of electronic devices such as semiconductor devices. The semiconductor-embedded substrate can suppress the mounting area of the semiconductor element by incorporating the semiconductor element in the substrate. In addition, it is possible to mount other components on the outermost layer surface of the semiconductor-embedded substrate, and the semiconductor device can be reduced in size. This technology is expected as a high-density mounting technology that realizes further higher integration and higher functionality of a semiconductor device, and realizes package thinning, cost reduction, high frequency compatibility, low stress connection, and the like.

  In addition, for the purpose of further higher integration and higher functionality, it is desired to reduce the thickness of the semiconductor-embedded substrate, and to reduce the thickness of the semiconductor element itself. In order to reduce the thickness of the semiconductor element itself, a semiconductor wafer is thinned from the back side after a circuit is formed on the semiconductor wafer.

  As a technique for thinning the semiconductor wafer, there are a backside grinding (BSG) technique for grinding the back surface of the semiconductor wafer, a technique for chemically etching the back surface of the semiconductor wafer, and the like. However, for example, a semiconductor wafer thinned to a thickness of 100 μm or less has insufficient strength (rigidity), and therefore, when an assembly process after thinning is performed, particularly when picking up from a dicing tape, a semiconductor element may be cracked. There is. Further, when the semiconductor element is thinned, warping occurs, which may cause trouble when mounted.

  Therefore, in Patent Document 1, the strength is improved by forming a reinforcing member made of a thermoplastic resin or a thermosetting resin of a B stage on the back surface of the semiconductor element, and in a pick-up process, a test process, a transport process, and the like. The generation of cracks is suppressed.

Japanese Patent Laid-Open No. 2002-110636

  However, in the method of Patent Document 1, since a thermoplastic resin, a B-stage thermosetting resin, or the like is used, the strength is insufficient, and a crack may occur due to an impact during pickup.

  Further, during the manufacture of the semiconductor-embedded substrate as described above, the thermoplastic resin reinforcing member is softened by heat from a heating press or the like, making it impossible to apply an appropriate pressure and load, and the insulating layer of the semiconductor-embedded substrate is It may be difficult to control the film thickness. If the thickness of the insulating layer cannot be controlled, the impedance of the wiring cannot be controlled, and high-speed and high-frequency signal transmission becomes difficult. In addition, when a height difference exceeding 10 μm occurs, for example, the difference in the depth of focus of the exposure machine becomes large, so that the patterning of the resist used for wiring formation is not stable, the width of the wiring becomes non-uniform, and the cause of disconnection or short circuit It may become. Furthermore, since the thermoplastic resin has a melting point, the temperature during the process must be kept below the melting point. Therefore, the selectable range of materials is narrowed, and it becomes difficult to select a configuration advantageous for reliability and electrical characteristics. In other words, if the lamination process of the insulating layer of the semiconductor-embedded substrate is performed at a temperature exceeding the melting point, the thermoplastic resin on the back surface of the semiconductor substrate is softened during the forming process, and the film thickness of the laminated insulating layer is kept uniform. May not be possible. If the insulating layer is severely deformed, the wiring and vias may be disconnected. Furthermore, since the thermoplastic resin has a relatively tendency to retain moisture in the resin film, the thermoplastic resin portion may swell in a reflow process or the like.

  Accordingly, an object of the present invention is to provide a semiconductor device that is thinned and has a strength that is more effectively reinforced and cracks are suppressed during pickup. It is another object of the present invention to provide a semiconductor element capable of manufacturing a semiconductor-embedded substrate by controlling the film thickness by heating during manufacturing.

Therefore, the present invention provides
A semiconductor element including a semiconductor substrate having a circuit surface,
The semiconductor element is a semiconductor element, wherein the semiconductor substrate is thinned and a cured thermosetting resin layer is provided on at least a surface opposite to a circuit surface of the semiconductor substrate.

  In addition, the present invention is a substrate with a built-in semiconductor including a covering insulating layer in which the semiconductor element is embedded, and a wiring layer that is electrically connected to an electrode terminal of the semiconductor element disposed on a circuit surface side.

  The present invention provides a semiconductor element capable of more effectively suppressing the occurrence of cracks due to impact during pick-up or the like by reinforcing the back side of a thinned semiconductor substrate with a cured thermosetting resin. be able to. In addition, since the semiconductor element according to the present invention is already reinforced with a cured thermosetting resin, it is not softened by heating during manufacturing of the semiconductor-embedded substrate. For this reason, since the film thickness does not change due to heating during the manufacture of the semiconductor-embedded substrate, the semiconductor-embedded substrate can be manufactured by controlling the film thickness easily by using the semiconductor element according to the present invention.

  Further, the present invention can provide a semiconductor-embedded substrate that can be thinned and can be manufactured by easily controlling the film thickness.

It is a schematic sectional drawing for demonstrating the structural example of the semiconductor element of this embodiment. It is a schematic sectional drawing for demonstrating the structural example of the semiconductor element of this embodiment. It is a schematic sectional drawing for demonstrating the structural example of the semiconductor element of this embodiment. It is a schematic sectional drawing for demonstrating the structural example of the semiconductor element of this embodiment. It is a schematic sectional drawing for demonstrating the structural example of the substrate with a built-in semiconductor element of this embodiment. It is a schematic sectional drawing for demonstrating the structural example of the substrate with a built-in semiconductor element of this embodiment. It is a schematic sectional drawing for demonstrating the structural example of the substrate with a built-in semiconductor element of this embodiment. It is a schematic sectional drawing for demonstrating the structural example of the substrate with a built-in semiconductor element of this embodiment. It is a schematic sectional drawing for demonstrating the structural example of the substrate with a built-in semiconductor element of this embodiment. It is a schematic sectional drawing for demonstrating the structural example of the semiconductor element of this embodiment. It is a schematic sectional drawing for demonstrating the structural example of the semiconductor element of this embodiment. It is a schematic sectional drawing for demonstrating the structural example of the semiconductor element of this embodiment. It is a schematic sectional drawing for demonstrating the structural example of the semiconductor element of this embodiment. FIG. 8 is a cross-sectional process diagram for explaining an example of manufacturing the semiconductor element shown in FIG. 1. FIG. 3 is a cross-sectional process diagram for explaining an example of manufacturing the semiconductor element shown in FIG. 2. FIG. 6 is a cross-sectional process diagram for explaining a manufacturing process of the semiconductor element built-in substrate shown in FIG. It is a schematic sectional drawing for demonstrating the structural example of the substrate with a built-in semiconductor element of this embodiment.

  Hereinafter, the present invention will be described in detail while describing embodiments with reference to the drawings.

(Embodiment 1)
FIG. 1 is a schematic cross-sectional view for explaining a configuration of a semiconductor element according to an embodiment of the present invention. As shown in FIG. 1, a semiconductor element 100 of the present invention includes at least a semiconductor substrate 101 on which a circuit 102 is formed, and is a surface opposite to a circuit surface (surface on which a circuit is formed) of the semiconductor substrate (hereinafter referred to as a circuit). Further, a cured thermosetting resin layer 104 is disposed on the side of the semiconductor substrate. Further, the semiconductor element of the present invention can include a passivation film 103 that protects the circuit surface on the circuit surface, and can include an electrode terminal on the circuit surface side, although not shown. As a matter of course, the circuit 102 does not need to be formed on the entire circuit surface. In addition, a circuit of a semiconductor element such as an LSI can constitute various functional blocks such as an interface block, a drive block, an A / D conversion block, a logic circuit block, a CPU block, a memory block, or a compression circuit block. .

  The present invention is characterized in that a cured thermosetting resin layer is provided on a surface opposite to a circuit surface of a thinned semiconductor substrate. By adopting the configuration of the present invention, the strength of the thinned semiconductor substrate can be further improved, and for example, the generation of cracks due to an impact at the time of pickup or the like can be more effectively suppressed. Further, the cured thermosetting resin layer used for reinforcing the semiconductor element is not softened by heat. For this reason, since the film thickness does not change due to heating during the manufacture of the semiconductor-embedded substrate, the semiconductor-embedded substrate can be manufactured by controlling the film thickness easily by using the semiconductor element according to the present invention.

  In the present invention, as shown in FIG. 2, a thermosetting resin layer can also be provided on the side surface of the semiconductor substrate. By providing the thermosetting resin layer on the back surface side and the side surface side of the semiconductor substrate, the strength of the semiconductor element can be further improved.

  The semiconductor substrate 101 is thinned from the back side by using, for example, BSG or etching, and the thickness of the semiconductor substrate 101 is, for example, 10 to 100 μm, preferably 20 to 80 μm, and preferably 20 to 70 μm. Is more preferable. Further, the material of the semiconductor substrate 101 is not particularly limited, and examples thereof include Si, GaAs, InP, and SiGe. Examples of the semiconductor element include a transistor, an IC, or an LSI. As the semiconductor element, although not particularly limited, for example, a complementary metal oxide semiconductor (CMOS) can be selected.

  A thermosetting resin layer is comprised from the thermosetting resin after hardening. As the thermosetting resin, for example, polyimide resin, polyamide resin, polybenzoxazole resin, epoxy resin, or silicone resin can be used. Among these, a polyimide resin, a polyamide resin, or a polybenzoxazole resin can be preferably used from the viewpoints of electrical characteristics and heat resistance. In addition, it is particularly preferable to use polyimide having high heat resistance and high elastic modulus as the thermosetting resin. The thermosetting resin layer is formed by, for example, a curing reaction including a crosslinking reaction and a ring closing reaction.

  As a method for forming the thermosetting resin layer, for example, an uncured thermosetting resin is applied to the back surface of the thinned semiconductor substrate 101 and cured, or a thermosetting resin cured in a sheet shape is used as an adhesive. The method of pasting using is mentioned. The curing reaction is not particularly limited, but can be cured by heating. In addition to heating, a curing reaction may be caused by light irradiation. The thermosetting resin layer is cured to the C stage state. By curing to the C stage state, the thinned semiconductor substrate can be effectively reinforced. 1 illustrates the form in which the semiconductor substrate 101 and the thermosetting resin layer 104 are in direct contact with each other, an adhesive may be disposed between the semiconductor substrate 101 and the thermosetting resin layer 104.

  The thickness of the thermosetting resin layer disposed on the back surface side or side surface side of the semiconductor substrate is, for example, 3 to 30 μm, and preferably 5 to 20 μm.

  The elastic modulus of the thermosetting resin layer is, for example, 1 to 30 GPa, and preferably 2 to 10 GPa. Further, as the thermosetting resin, it is preferable to use a polyimide resin having an elastic modulus after curing of 5 GPa or more and Tg of 250 ° C. or more.

  The linear expansion coefficient (1 / K) of the thermosetting resin layer is, for example, 10 to 100, and preferably 20 to 60.

  The elongation at break of the thermosetting resin layer is, for example, 10% or more, and more preferably 20% or more.

  The passivation film that protects the circuit surface can be formed using, for example, silicon oxide, silicon nitride, or an insulator material. Polyimide resin can be preferably used as the insulator material that constitutes the passivation film. The thickness of the passivation film made of polyimide resin is, for example, 5 to 10 μm.

  The passivation film can be formed of a plurality of layers, for example, a stacked film of an inorganic film such as silicon oxide or silicon nitride and an organic film made of polyimide resin.

  In the present invention, the warpage of the semiconductor element can be reduced by maintaining a balance between the shrinkage stress due to the passivation film 103 formed on the circuit surface and the shrinkage stress of the thermosetting resin layer 104 disposed on the back surface. From such a viewpoint, the residual stress of the passivation film and the thermosetting resin layer is obtained by a calculation method from the warpage amount using a Si wafer having a known thickness and size, and the difference between the residual stresses is 10 times. The following combinations are preferable, more preferably 5 times or less, and still more preferably 2 times or less.

(Embodiment 2)
A semiconductor-embedded substrate can be obtained by incorporating the semiconductor element of the present invention in an insulating layer and disposing a wiring layer. Since the thermosetting resin layer used for reinforcing the semiconductor element is already cured, it is not deformed by heat at the time of manufacturing the semiconductor-embedded substrate. Therefore, by manufacturing the semiconductor-embedded substrate using the semiconductor element according to the present invention, the film thickness of the semiconductor-embedded substrate can be easily controlled, and the semiconductor built-in substrate can be manufactured with stable performance quality.

  FIG. 5 is a schematic cross-sectional view for explaining a configuration example of a semiconductor-embedded substrate according to the present invention. In FIG. 5, the passivation film, the circuit, and the electrode terminal are omitted.

  In FIG. 5A, a thermosetting resin layer 104 is provided on the back surface of the semiconductor element 100. In addition, the semiconductor element 100 is disposed on the back insulating layer 1001 with the surface having electrode terminals facing upward through the adhesive layer 1003. Further, the electrode terminal surface and the side surface of the semiconductor element 100 are covered with a covering insulating layer 1002.

  A wiring layer 1005 is disposed on the covering insulating layer 1002. An element via 1004 that electrically connects the wiring layer 1005 and the semiconductor element 100 is provided in the covering insulating layer 1002. The wiring layer 1005 includes wiring such as signal wiring, power supply wiring, or ground wiring. In this specification, the wiring layer (the wiring layer 1005 in FIG. 1) disposed on the electrode terminal surface side of the semiconductor element is also referred to as a front-side wiring layer.

  The wiring layer 1005 is covered with a wiring insulating layer 1006, and a solder resist 1009 is provided on the wiring insulating layer 1006. In the solder resist 1009, an external connection terminal 1008 used for connection to an external substrate or the like is provided. In the wiring insulating layer 1006, wiring vias 1007 for electrically connecting the wiring layer 1005 and the external connection terminals 1008 are provided.

  The external connection terminal 1008 is connected to an external substrate such as a motherboard via a BGA ball, for example. Further, the external connection terminal 1008 may have a configuration in which signal wiring and ground wiring are opened in the solder resist 1009. That is, a second wiring layer having a ground wiring and a signal wiring is provided on the wiring insulating layer 1006, and the solder resist 1009 is formed on the ground wiring and the signal wiring so that a part of them is opened. it can. Further, the surface of the external connection terminal can be protected so that, for example, solder does not flow.

  As a material for the covering insulating layer, an insulating resin can be used, and an insulator used for a normal wiring board can be used. Examples of the material for the covering insulating layer include an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, and a polynorbornene resin. In addition, other examples include BCB (Benzocyclobutene), PBO (Polybenzoxazole), and the like. Among these, polyimide resin and PBO are excellent in mechanical properties such as film strength, tensile elastic modulus, elongation at break, and the like, so that high reliability can be obtained. The material of the covering insulating layer may be either photosensitive or non-photosensitive. The covering insulating layer may be formed of a plurality of layers, but in this case, it is preferable to use the same material. Further, as shown in FIG. 5B, the covering insulating layer includes a reinforcing layer 1002a having an opening in which the semiconductor element 100 is disposed, and a filling resin layer 1002b filled in the opening in which the semiconductor element 100 is disposed. , Can also consist of

  Moreover, as a semiconductor element, that whose terminal surface is a full grid or a peripheral pad can be used, for example. Further, the connection method with the wiring layer is not particularly limited, and flip chip connection, copper post connection, laser via connection, or the like can be used.

  The conductor used for the wiring layer and via is not particularly limited, but for example, a metal containing at least one selected from the group consisting of copper, silver, gold, nickel, aluminum, and palladium, or these are mainly used. An alloy as a component can be used. Of these, Cu is preferably used as the conductor from the viewpoint of electrical resistance and cost.

  The semiconductor-embedded substrate of the present invention may have a metal plate as a support. The material of the metal plate is not particularly limited. For example, a metal containing at least one selected from the group consisting of copper, silver, gold, nickel, aluminum, and palladium, or an alloy containing these as a main component. Can be used. Among these, it is preferable to use copper as the material of the metal plate from the viewpoint of electrical resistance value and cost. Moreover, since the metal plate also functions as an electromagnetic shield, it is expected to reduce unnecessary electromagnetic radiation.

  The wiring layer (surface side wiring layer) arranged on the electrode terminal surface side of the semiconductor element can be one or more layers, and is not particularly limited. One or more wiring layers can be provided not only on the electrode terminal surface side of the semiconductor element but also on the surface opposite to the electrode terminal surface. In this specification, the wiring layer provided on the surface opposite to the electrode terminal surface of the semiconductor element is also referred to as a back surface side wiring layer. FIG. 9 shows a configuration example in which a wiring layer is also provided on the back side of the semiconductor element. In FIG. 9, an interlayer via 1011 is provided in the covering insulating layer 1002. The interlayer via 1011 is electrically connected to the first back side wiring layer 1012. The first back-side insulating layer 1013 covers the first back-side wiring layer 1012. A second back side wiring layer 1015 is formed on the back side (the lower side of the figure) of the first back side insulating layer 1013. The first back surface side via 1014 is formed in the first back surface side insulating layer 1013, and the first back surface side via 1014 includes the first back surface side wiring layer 1012 and the second back surface side wiring layer. 1015 is electrically connected. The second back-side insulating layer 1016 covers the second back-side wiring layer 1015. A back side external connection terminal 1018 and a solder resist 1019 are provided on the back side (the lower side of the figure) of the second back side insulating layer. A second back-side via 1017 is provided in the second back-side insulating layer 1016, and the second back-side wiring layer 1015 and the back-side external connection terminal 1018 are connected by the second back-side via 1017. Electrically connected. By providing the wiring layers in both the front surface side and the back surface side of the semiconductor element 100, the degree of freedom in wiring design can be improved. In addition, since the symmetry of the structure is improved, the warpage of the substrate can be further reduced. The back surface side wiring layer can be electrically connected to the electrode terminal of the semiconductor element through an interlayer via provided in the covering insulating layer or the front surface side wiring layer.

(Embodiment 3)
Although FIG. 1 shows a form in which the semiconductor substrate 101 and the thermosetting resin layer 104 are in direct contact with each other, the present invention is not particularly limited to this, and metal ions are applied to the surface opposite to the circuit surface of the semiconductor substrate. A shielding barrier film can be provided. As shown in FIG. 3 or 4, a barrier film can be disposed between the thermosetting resin layer 104 and the semiconductor substrate 101, or on the back surface or side surface of the thermosetting resin layer.

  The barrier film 105 is composed of an inorganic film that does not allow metal ions such as copper to pass through, and has a function of protecting the circuit from the metal ions. Examples of the material of the barrier film include silicon oxide (SiO), silicon nitride (SiN), silicon carbonitride (SiCN), titanium nitride (TiN), and tantalum nitride (TaN). In addition, examples of the conductive barrier film include materials mainly containing Ti, Ta, Cr, Ni, W, Mo, or the like. The barrier film is not particularly limited, but can be formed using, for example, a sputtering method or a CVD method.

  By providing the barrier film, deterioration of device characteristics can be prevented from metal ions such as copper, potassium, and sodium. In particular, when a semiconductor-embedded substrate is used, metal ions may be contained in the resin. With this embodiment, these metal ions can be shielded on the back side of the semiconductor element.

  The thickness of the barrier film is not particularly limited, but is, for example, 40 to 3000 nm, and preferably 300 to 1000 nm.

  In FIG. 3, a thermosetting resin layer 104 is disposed on the back side of the semiconductor substrate 101, and FIG. 3A shows a configuration in which a barrier film 105 is provided between the thermosetting resin layer 104 and the semiconductor substrate 101. FIG. 3B shows a configuration in which a barrier film 105 is provided on the back surface of the thermosetting resin layer 104. In the present invention, since the semiconductor substrate is thinned from the back surface side, the circuit is easily affected by metal ions. Therefore, by forming a barrier film on the back side of the semiconductor substrate to prevent intrusion of metal ions, it is possible to reduce deterioration of element characteristics due to metal ions.

  FIG. 6 shows a substrate with a built-in semiconductor in which the semiconductor element shown in FIG. In FIG. 6A, a barrier film 105 is formed between the semiconductor element 100 and the thermosetting resin layer 104, and the semiconductor element 100 is disposed on the back-side insulating layer 1001 using an adhesive 1003. Yes. In addition, the semiconductor element 100 is built in the covering insulating layer 1002. In FIG. 6B, the semiconductor element 100 having the barrier film 105 is disposed on the support 1010 made of a metal plate with an adhesive 1003 interposed therebetween. In particular, as shown in FIG. 6B, when a semiconductor-embedded substrate including a support made of a metal plate is used, in this embodiment, metal ions derived from the metal plate are shielded by a barrier film arranged on the back side of the semiconductor element. It is effective because it can be done. FIG. 7 shows a semiconductor-embedded substrate in which the semiconductor element shown in FIG.

  In the semiconductor element shown in FIG. 3A, since the barrier film is provided on the back surface of the element, it is easy to form a dense barrier film, and the thickness of the barrier film itself can be reduced. When a conductive barrier film is provided, the shielding effect can be realized by setting the barrier film to the ground potential.

  In the semiconductor element shown in FIG. 3B, the distance from the barrier film to the circuit portion of the semiconductor element can be increased, and further improvement in barrier properties can be expected. When a conductive barrier film is provided, a shielding effect and stabilization of the power supply voltage of the semiconductor element can be realized by applying a potential such as a ground voltage or a power supply voltage. Furthermore, in FIG.3 (b), when the adhesiveness of a thermosetting resin layer and the adhesive agent 1003 is not acquired, or when reliability is low, the effect of the adhesive force improvement to both can be anticipated.

  In the semiconductor-embedded substrate shown in FIG. 6 or 7, when the barrier film is set to the ground potential or the power supply potential, a via is formed in the covering insulating layer 1002, and wiring for electrically connecting the via and the barrier film is formed. This can be achieved.

In the configuration shown in FIG. 6A, the barrier film can be set to the ground potential by using TSV (Through Silicon Via) formed in the semiconductor element. That is, in the structure shown in FIG. 3A, a semiconductor element in which the barrier film and the ground circuit in the electronic circuit are electrically connected using TSV can be obtained. That is, the semiconductor substrate can have a TSV inside, and the barrier layer having conductivity by the TSV can be electrically connected to the ground circuit formed on the circuit surface. TSV is not particularly limited, for example, can be formed by forming an opening by D-RIE (Deep-Reactive Ion Etching) method or a laser over methods, placing a conductive material in the opening. Examples of the method for arranging the conductive material in the opening include a metal melting method, an electrolytic plating method, an electroless plating method, a sputtering method, and a vapor deposition method.

  In particular, in FIG. 7B, when a support made of a metal plate is used, the barrier layer can be easily grounded by setting the support to a ground potential and using a conductive material for the adhesive 1003. It can be a potential.

  In FIG. 4, the thermosetting resin layer 104 is disposed on the back surface side and the side surface side of the semiconductor substrate 101, and FIG. 4A illustrates a barrier film provided between the thermosetting resin layer 104 and the semiconductor substrate 101. FIG. 4B shows a configuration in which a barrier film is provided on the back and side surfaces of the thermosetting resin layer 104. In the embodiment shown in FIG. 4, metal ions can be shielded on the side surface in addition to the back surface. In particular, in the embodiment shown in FIG. 4A, since the back surface and back surface of the semiconductor element are covered with the barrier film, metal ions can be shielded more effectively.

  FIG. 8 shows a semiconductor-embedded substrate in which the semiconductor element shown in FIG. As described above, the resin used for the semiconductor-embedded substrate may contain metal ions such as copper. By adopting the configuration shown in FIG. 8A, a circuit is formed from these metal ions by the barrier film. It can be effectively protected. In particular, as shown in FIG. 8B, when a semiconductor-embedded substrate including a support made of a metal plate is used, metal ions derived from the metal plate can be effectively shielded by a barrier film. Further, as described above, by setting the barrier film to a predetermined potential, the shielding effect and the stabilization of the power supply voltage can be more effectively achieved.

  In the semiconductor element shown in FIG. 4A, since the barrier film is provided on the back surface of the element, it is easy to form a dense barrier film, and the thickness of the barrier film itself can be reduced. When a conductive barrier film is provided, the shielding effect can be realized by setting the barrier film to the ground potential. In the configuration shown in FIG. 4A, the barrier film can be stably formed by using a sputtering method, a CVD method, or the like in a state where an element formed on the wafer is cut. In order to form the barrier film up to the side surface of the semiconductor element, it is desirable to make the semiconductor element as thin as possible.

  In the semiconductor element shown in FIG. 4B, the distance from the barrier film to the circuit portion of the semiconductor element can be increased, and further improvement in barrier properties can be expected. When a conductive barrier film is provided, a shielding effect and stabilization of the power supply voltage of the semiconductor element can be realized by applying a potential such as a ground voltage or a power supply voltage. Furthermore, in FIG.4 (b), when the adhesiveness of a thermosetting resin layer and the adhesive agent 1003 is not acquired, or when reliability is low, the effect of the adhesive force improvement to both can be anticipated. Further, in the configuration shown in FIG. 4B, the distance between the circuit of the semiconductor element and the barrier film can be increased compared to the configuration in FIG. 4A, and the conductive barrier film is set to a predetermined potential. In this case, it is possible to effectively prevent the occurrence of a circuit short circuit. This is because a test circuit or the like exists in the circuit portion of the semiconductor element, and a circuit short circuit may occur due to contact of the conductive barrier film.

  As described above, when the barrier film is set to a predetermined potential, for example, a via is formed in the covering insulating layer of the substrate with a built-in semiconductor, and wiring is provided to electrically connect the via to the barrier film. can do.

  In FIG. 4A, the ground circuit of the semiconductor element is formed so as to extend to the side surface, and is formed so as to be electrically connected to the side barrier layer, whereby the barrier film can be set to the ground potential. . That is, the electronic circuit formed on the circuit surface can include a ground circuit extending to the side surface of the semiconductor substrate, and the ground circuit can be in contact with the conductive barrier film. Further, as described above, the barrier film can be set to a predetermined potential by using TSV (Through Silicon Via) formed in the semiconductor element. That is, a semiconductor element in which a power supply circuit or a ground circuit in an electronic circuit is electrically connected using a TSV with the barrier film can be obtained.

  Further, in the semiconductor-embedded substrate having the semiconductor element shown in FIG. 4B, as shown in FIG. 17A, a via 8001 for electrically connecting the wiring layer 1005 and the barrier film 105 is provided as a covering insulating layer. It can also be achieved by providing it inside. In addition, as shown in FIG. 17B, when a support 1010 made of a metal plate is used, the barrier layer can be easily formed by setting the support to a ground potential and using a conductive material for the adhesive 1003. Can be a ground potential.

(Embodiment 4)
Moreover, as shown in FIG. 10, it is preferable that surface roughness Ra in the surface (back surface of a thermosetting resin layer) on the opposite side to the semiconductor substrate of the thermosetting resin layer 104 shall be 0.1-0.8 micrometer. . By setting the surface roughness on the back surface of the thermosetting resin layer 104 within this range, an adhesive such as an adhesive sheet and the semiconductor element can be more firmly bonded.

(Embodiment 5)
Moreover, as shown in FIG. 11, it is preferable to form a thermosetting resin layer so that it may become so thin that it goes to the outer peripheral edge part from the center part of a semiconductor element. With such a structure, for example, when the semiconductor element is bonded to the adhesive 202 disposed on the insulating layer 201, the air can be bonded to the outside. Therefore, it is possible to easily bond the semiconductor elements so that air is not contained therein. In particular, as shown in FIG. 11, if the thermosetting resin layer is thinned from the center portion of the semiconductor element toward the outer peripheral end portion by drawing a gentle curve, the air can be effectively pushed out to the outside at the time of bonding. Therefore, it is preferable. In particular, it is preferable that the central portion of the convex lens is thick and the outer peripheral end portion is thin.

  More specifically, the thermosetting resin layer can have a shape in which the thickness of the thermosetting resin layer decreases from the center toward the end in any cross section passing through the center of the semiconductor element and perpendicular to the circuit surface. For example, when the semiconductor element is rectangular, the center of the semiconductor element can be centered on the intersection of diagonal lines.

  The difference in thickness of the thermosetting resin layer between the central portion and the outer peripheral end portion of the semiconductor element is not particularly limited and can be adjusted as appropriate, and can be set to 3 to 20 μm, for example.

  Moreover, as a formation method of such a thermosetting resin layer, a molding method can be used, for example. For example, a thermosetting resin layer having a desired shape can be formed by applying a thermosetting resin to the back surface of the semiconductor element and then pressing the predetermined mold to cure the thermosetting resin.

  In FIG. 11, a semiconductor element can be mounted on the adhesive 202 under heating and pressure conditions. In the present invention, since the thermosetting resin layer does not deform under heating and pressure conditions, it is easy to control the film thickness even during bonding.

(Embodiment 6)
Moreover, as shown in FIG. 12, a thermosetting resin layer can also be formed so that it may become so thick that it goes to the outer peripheral edge part from the center part of a semiconductor element. By increasing the thickness of the thermosetting resin layer on the outer peripheral end side of the semiconductor element, the shrinkage stress applied to the semiconductor element can be improved, and the balance with the shrinkage stress due to the passivation film disposed on the circuit surface side of the semiconductor element. Can be easily maintained.

  In particular, when an organic resin such as polyimide is used as the passivation film, the shrinkage stress to the semiconductor element is increased and warping may occur. In that case, by forming an organic resin film on the back surface of the semiconductor element, shrinkage stress opposite to the shrinkage stress of the passivation film can be generated, and the warpage can be reduced. In that case, since the organic resin film is thickened from the central portion toward the outer peripheral edge as in the present embodiment, it is possible to effectively generate a shrinkage stress that is opposite to the shrinkage stress of the passivation film. , Warpage of the semiconductor element can be effectively reduced. In the present embodiment, it is particularly preferable that the central portion is thin and the outer peripheral end portion is thick like a concave lens.

  More specifically, the thermosetting resin layer can have a shape in which the thickness of the thermosetting resin layer increases from the center toward the end in any cross section passing through the center of the semiconductor element and perpendicular to the circuit surface. For example, when the semiconductor element is rectangular, the center of the semiconductor element can be centered on the intersection of diagonal lines.

  The difference in thickness of the thermosetting resin layer between the central portion and the outer peripheral end portion of the semiconductor element is not particularly limited and can be adjusted as appropriate, and can be set to 3 to 20 μm, for example.

  In the case of this embodiment, air may be contained inside when adhering to an adhesive or the like, so it is desirable to perform the adhering step in a vacuum.

  Moreover, as a formation method of such a thermosetting resin layer, a molding method can be used, for example. For example, a thermosetting resin layer having a desired shape can be formed by applying a thermosetting resin to the back surface of the semiconductor element and then pressing the predetermined mold to cure the thermosetting resin.

(Embodiment 7)
Further, as shown in FIGS. 13A to 13C, a convex portion is formed on the surface opposite to the surface in contact with the semiconductor substrate of the thermosetting resin layer (hereinafter also referred to as the back surface of the thermosetting resin layer). be able to. By forming a convex portion on the back surface of the thermosetting resin layer, the adhesive force with the holding tape can be reduced, and the semiconductor element can be easily peeled off from the holding tape when picking up with the pickup needle. .

  The convex portion can also be formed of a thermosetting resin layer as shown in FIGS. That is, a convex part can be formed by making the surface shape of the back surface side of a thermosetting resin layer into an uneven shape. Moreover, the convex part can also be formed using a resin material different from the thermosetting resin layer as shown in FIG.

  The shape of the convex portion is not particularly limited, but the horizontal cross-sectional shape (cross-sectional shape in the surface direction) can be a rectangular shape, a polygonal shape, a circular shape, an elliptical shape, or the like. The surface of the convex portion is preferably a flat surface. Further, the thickness, width, and interval of the convex portions can be adjusted as appropriate. For example, the thickness of the convex portion (h in FIG. 13A) can be set to 3 to 20 μm, for example.

  The number of the convex portions is not particularly limited, but one or more can be formed on the back side of the semiconductor element, and a plurality of the convex portions are preferably formed.

  The arrangement position of the convex portions is not particularly limited, and for example, the convex portions can be arranged on the back surface of the thermosetting resin layer in a lattice shape or a zigzag shape.

  Moreover, it is preferable to provide a convex part in the part pushed up with the pick-up needle used for a pickup as an arrangement position of a convex part. This is because the occurrence of cracks in the semiconductor element can be further reduced by improving the strength of the portion pushed up by the pickup needle by providing a convex portion. Moreover, when providing a convex part in the part which a pick-up needle contacts, it is preferable to comprise the elastic modulus of the convex part with 5-20 Mpa resin. This is because the impact of the pickup needle can be effectively absorbed by forming the convex portion with a resin having an elastic modulus of 5 to 20 MPa. The pick-up needles are usually arranged so as to push up near the corners (around the four corners) of the semiconductor element. Therefore, it is preferable to provide convex portions on the back side of the thermosetting resin layer at the four corners of the rectangular semiconductor element.

  Further, in the process of manufacturing the semiconductor element, a cured thermosetting resin layer is provided on the back surface of the semiconductor element, and the protrusion is provided in a portion of the thermosetting resin layer that is pushed up by the pickup needle at the time of pickup. It is preferable. By providing a convex portion on the portion of the thermosetting resin layer that is pushed up by the pick-up needle during pick-up, the strength against impact by the pick-up needle can be improved. Therefore, generation of cracks can be suppressed and a semiconductor element can be manufactured.

  The method for forming the projection is not particularly limited, and for example, a photolithography method, a molding method, dry etching, or wet etching can be used.

(Embodiment 8)
In order to reduce the warpage of the semiconductor element, a warpage control pattern may be provided on the back side of the thermosetting resin layer. This warpage control pattern can be appropriately selected in accordance with the balance of the residual stress of the passivation film and the thermosetting resin layer provided on the surface side of the semiconductor element. In other words, if a warp with the passivation film inside occurs without providing a warp control pattern, it is necessary to improve the rigidity and increase the amount of shrinkage on the thermosetting resin layer side, so it may be provided in a convex shape. desirable. As a measure for improving the rigidity, a lattice shape or a radial shape is effective. The size of the lattice shape, the angle of the radial shape, and the like can be appropriately selected according to the desired rigidity. On the other hand, since the countermeasure for increasing the contraction amount needs to generate a force toward the center of the semiconductor element, a dot-like arrangement including a radial shape, a polygonal shape, or a circular shape is effective. The radial angle, dot shape, and pitch can be appropriately selected according to the amount of contraction. However, with respect to the dot shape, the warpage canceling of the outer peripheral portion is easily achieved by increasing the size toward the outer periphery of the semiconductor element. The amount of protrusion from the convex surface is 3 μm or more and 30 μm or less, preferably 5 μm or more and 15 μm or less, and more preferably 7 μm or more and 10 μm or less. Next, when warping with the thermosetting resin inside occurs without providing a warp control pattern, it is necessary to improve the deformability of the thermosetting resin, so it may be provided in a concave shape. desirable. That is, by making the thermosetting resin easy to be partially deformed, the deformation toward the passivation film side is strengthened, and the warp control is effectively performed. In order to improve the ease of deformation, it is effective to superimpose a plurality of similar polygons or circles having a lattice shape, a radial shape, and a center position. The amount of protrusion from the concave surface is 3 μm or more and 30 μm or less, preferably 5 μm or more and 15 μm or less, and more preferably 7 μm or more and 10 μm or less. Resin can be used for the material of a curvature control pattern, and it is preferable that it is a thermosetting resin. Further, the warpage control pattern can be formed on the back surface of the thermosetting resin layer using a photolithography method.

(Embodiment 9)
Hereinafter, a method of manufacturing the semiconductor device having the configuration shown in FIG. 1 will be described with reference to FIG. In addition, this invention is not restrict | limited to the following manufacturing methods.

  First, as shown in FIG. 14A, a wafer 2001 on which a circuit 2002 and a passivation film 2003 are formed is prepared, and a first holding tape A is attached to the circuit surface side of the wafer 2001. In this embodiment, a silicon wafer is used as the semiconductor substrate.

  Next, as shown in FIG. 14B, the wafer 2001 is thinned from the back surface. As a thinning method, a method such as BSG, chemical etching, or CMP can be used.

  Next, as shown in FIG. 14C, a thermosetting resin layer 2004 is formed by applying and curing a thermosetting resin on the back surface of the thinned wafer 2001 '. Examples of the coating method include a spin coating method. For example, a polyimide resin can be used as the thermosetting resin.

  In the case where the barrier film is provided between the thermosetting resin layer 2004 and the semiconductor substrate, the barrier film is formed using a sputtering method, a CVD method, or the like before applying the thermosetting resin. In the case where the barrier film is provided on the back surface of the thermosetting resin layer 2004, the barrier film is formed using a sputtering method, a CVD method, or the like after the thermosetting resin layer 2004 is formed.

  Next, as shown in FIG. 14D, the first holding tape A is peeled off, and the second holding tape B is attached to the surface (back surface) opposite to the circuit surface.

  Next, as shown in FIG. 14E, dicing is performed according to the outer shape of the semiconductor element.

  Next, as shown in FIG. 14 (f), the semiconductor chip having the thermosetting resin layer formed on the back side is picked up from the second holding tape B using the pickup needle 2005.

  In the present invention, since the back side of the semiconductor element is reinforced with a cured thermosetting resin layer, it is possible to prevent the occurrence of cracks during pickup. Further, not only at the time of picking up, damage can be prevented against an impact in the transport process and the mounting process.

(Embodiment 10)
Hereinafter, a method of manufacturing the semiconductor device having the configuration shown in FIG. 2 will be described with reference to FIG. In addition, this invention is not restrict | limited to the following manufacturing methods.

  First, as shown in FIG. 15A, a wafer 2001 on which a circuit 2002 and a passivation film 2003 are formed is prepared, and a first holding tape C is attached to a surface (back surface) opposite to the circuit surface of the wafer 2001. wear. Then, a dicing groove is formed by dicing from the circuit surface side. The dicing groove is formed to be equal to or greater than the thickness of the final semiconductor element. In this embodiment, a silicon wafer is used as the semiconductor substrate.

  Next, as shown in FIG. 15B, the first holding tape C is peeled off, and the second holding tape D is attached to the circuit surface side.

  Next, as shown in FIG. 15C, the wafer 2001 is thinned from the back surface until it reaches the dicing groove. As a thinning method, a method such as BSG, chemical etching, or CMP can be used.

  Next, as shown in FIG. 15D, a thermosetting resin is applied to the back surface of the thinned wafer 2001 ′ and cured to form a thermosetting resin layer 2004. At this time, the thermosetting resin enters the dicing grooves, so that the thermosetting resin layer 2004 is also formed on the side surface of the semiconductor element. Examples of the coating method include a spin coating method. For example, a polyimide resin can be used as the thermosetting resin.

  In the case where the barrier film is provided on the back surface and the side surface of the semiconductor element, the barrier film may be formed using, for example, a sputtering method or a CVD method before applying the thermosetting resin.

  Next, as shown in FIG. 15E, the second holding tape D is peeled off, and the third holding tape E is attached to the back surface. Then, dicing is performed in accordance with the outer shape of the semiconductor element from the circuit surface side. At this time, dicing is performed so that the thermosetting resin layer 2004 remains on the side surface of the semiconductor element.

  At this time, a barrier film can be formed on the back and side surfaces of the thermosetting resin layer 2004 using, for example, a sputtering method or a CVD method.

  Next, as shown in FIG. 15 (f), a semiconductor chip having a thermosetting resin layer formed on the back surface and side surfaces is picked up from the third holding tape E using the pick-up needle 2005.

  The manufacturing method of this embodiment can form a thermosetting resin layer easily in the back surface and side surface of a semiconductor element.

(Embodiment 11)
Next, a method for manufacturing the semiconductor element-embedded substrate shown in FIG. 5A will be described with reference to FIG. FIG. 16 is a process cross-sectional view schematically showing a manufacturing process of the semiconductor-embedded substrate of the embodiment of FIG. In addition, this invention is not limited to the following manufacturing methods.

  First, as illustrated in FIG. 16A, the semiconductor element 100 in which the thermosetting resin layer 104 is formed on the back surface is disposed on the back surface insulating layer 1001 using an adhesive 1003. As the adhesive, for example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, or the like can be used.

  Next, as shown in FIG. 16B, a covering insulating layer 1002 is disposed on the back insulating layer 101 so as to cover the semiconductor element 100.

  Next, as illustrated in FIG. 16C, the element via 1004 is formed in the covering insulating layer 1002, and the wiring layer 1005 is formed on the covering insulating layer 1002.

  Next, as illustrated in FIG. 16D, a wiring insulating layer 1006 that covers the wiring layer 1005 is formed, and a wiring via 1007 is formed in the wiring insulating layer 1006. Then, an external connection terminal 1008 and a solder resist 1009 are formed on the wiring insulating layer 1006.

  As a method for forming the coating insulating layer and the wiring insulating layer, for example, a transfer molding method, a compression molding method, a printing method, a vacuum press, a vacuum lamination, a spin coating method, a die coating method, a curtain coating method and the like are provided.

  Further, in the present invention, the semiconductor element is reinforced with a cured thermosetting resin layer, and this thermosetting resin layer is not deformed by heat at the time of manufacturing a semiconductor-embedded substrate. Thus, a semiconductor-embedded substrate can be manufactured.

  As a method for forming element vias or wiring vias, electrolytic plating, electroless plating, a printing method, a molten metal suction method, or the like can be used.

  When the material used for the insulating layer has photosensitivity, the element via and the wiring via prepared hole can be formed by photolithography. When the material used for the insulating layer is non-photosensitive or the pattern resolution is low, the pilot hole can be formed by a laser processing method, a dry etching method, or a blast method.

  In addition, as an element via to be connected to the electrode terminal of the semiconductor element, a metal post for energization is provided on the electrode terminal in advance, the covering insulating layer 1002 is formed, and then the surface of the insulating material is shaved by polishing or the like. A method of forming the via by exposing the surface of the metal post may be used. Examples of the grinding method include buffing and CMP.

  The wiring layer can be formed using a metal such as Cu, Ni, Sn, or Au, for example, by a subtractive method, a semi-additive method, a full additive method, or the like.

  The subtractive method is disclosed, for example, in JP-A-10-51105. The subtractive method is a method of obtaining a desired wiring pattern by using a resist in which a copper foil provided on a substrate or a resin is formed in a desired pattern as an etching mask and removing the resist after the etching. The semi-additive method is disclosed, for example, in JP-A-9-64493. The semi-additive method is a method in which a power supply layer is formed, a resist is formed in a desired pattern, electrolytic plating is deposited in the resist opening, and the power supply layer is etched after removing the resist to obtain a desired wiring pattern. It is. The power feeding layer can be formed by, for example, electroless plating, sputtering, CVD, or the like. The full additive method is disclosed, for example, in JP-A-6-334334. In the full additive method, first, an electroless plating catalyst is adsorbed on the surface of a substrate or resin, and then a pattern is formed with a resist. Then, the catalyst is activated while leaving the resist as an insulating layer, and a metal is deposited in the opening of the insulating layer by an electroless plating method to obtain a desired wiring pattern.

  The external connection terminal 1008 may also serve as a signal wiring or a ground wiring. In this case, the external connection terminal can be formed by etching the solder resist so that a part of the signal wiring or the ground wiring is exposed. .

DESCRIPTION OF SYMBOLS 100 Semiconductor element 101 Semiconductor substrate 102 Circuit 103 Passivation film 104 Thermosetting resin layer (after hardening)
DESCRIPTION OF SYMBOLS 105 Barrier film 106 Convex part 1001 Back surface insulating layer 1002 Covering insulating layer 1003 Adhesive 1004 Element via | veer 1005 Wiring layer (surface side wiring layer)
1006 Wiring insulation layer 1007 Wiring via 1008 External connection terminal 1009 Solder resist 1010 Support body 1011 Interlayer via 1012 First backside wiring layer 1013 First backside insulating layer 1014 First backside via 1015 Second backside Wiring layer 1016 Second back side insulating layer 1017 Second back side via 1018 Back side external connection terminal 1019 Back side solder resist 2001 Wafer 2001 ′ Thinned wafer 2002 Circuit 2003 Passivation film 2004 Thermosetting resin layer 2005 Pickup needle

Claims (22)

A semiconductor element including a semiconductor substrate having a circuit surface,
The semiconductor element is characterized in that the semiconductor substrate is thinned, and a cured thermosetting resin layer is provided at least on a surface opposite to the circuit surface of the semiconductor substrate.   The semiconductor element according to claim 1, wherein the thermosetting resin layer is further provided on a side surface side of the semiconductor substrate.   The semiconductor element according to claim 1, wherein a barrier film that shields metal ions is provided on a surface of the semiconductor substrate opposite to the circuit surface.   The semiconductor element according to claim 3, wherein the barrier film is provided between the thermosetting resin layer and the semiconductor substrate.   The semiconductor element according to claim 3, wherein the barrier film is provided on a surface of the thermosetting resin layer opposite to the semiconductor substrate.   The semiconductor element according to claim 5, wherein the barrier film is also provided on a side surface of the thermosetting resin layer.   The semiconductor device according to claim 3, wherein the barrier film has conductivity.   The semiconductor element according to claim 7, wherein the barrier film is electrically connected to a power supply or ground circuit disposed on the circuit surface.   The semiconductor element according to claim 1, wherein the semiconductor substrate has a thickness of 10 to 100 μm.   The semiconductor element according to claim 1, wherein an elastic modulus of the thermosetting resin layer is 1 to 30 GPa.   The semiconductor element according to claim 1, wherein the thermosetting resin layer has a thickness of 3 to 30 μm.   The semiconductor element according to claim 1, further comprising a passivation film that protects the circuit surface on a circuit surface side of the semiconductor substrate.   The semiconductor element according to claim 1, wherein a surface of the thermosetting resin layer opposite to a surface in contact with the semiconductor substrate has a convex portion.   The semiconductor element according to claim 13, wherein the semiconductor element has a rectangular shape, and the protrusions are provided near respective corners of the semiconductor element.   The semiconductor element according to claim 1, wherein the thermosetting resin layer has a shape that becomes thinner from a central portion toward an end portion.   The semiconductor element according to claim 1, wherein the thermosetting resin layer has a shape that becomes thicker from a central portion toward an end portion.   17. The semiconductor element according to claim 1, wherein a surface roughness Ra of a surface opposite to a surface in contact with the semiconductor substrate of the thermosetting resin layer is 0.1 to 0.8 μm.   The semiconductor element according to claim 1, wherein a warp control pattern is formed on a surface of the thermosetting resin layer opposite to the semiconductor substrate.   The warpage control pattern has a lattice shape, a radial shape, a dot shape, a shape in which the centers of a plurality of similar shapes are overlapped, and has a convex shape or a concave shape from the surface of the thermosetting resin layer. The semiconductor device according to claim 18.   20. A substrate with a built-in semiconductor, comprising: a covering insulating layer containing the semiconductor element according to claim 1; and a wiring layer electrically connected to an electrode terminal of the semiconductor element disposed on the circuit surface side. A semiconductor-embedded substrate containing the semiconductor element according to claim 3,
A support made of a metal plate on the surface of the thermosetting resin layer opposite to the surface in contact with the semiconductor substrate;
A coating insulating layer containing the semiconductor element on the support;
A wiring layer facing the support with the covering insulating layer therebetween and electrically connected to electrode terminals provided on a circuit surface of the semiconductor element;
Semiconductor embedded substrate including A semiconductor-embedded substrate containing the semiconductor element according to claim 7,
A semiconductor-embedded substrate including a wiring layer having a ground or power supply wiring electrically connected to the barrier film.

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