JP3273113B2 - Multilayer wiring board - Google Patents

Multilayer wiring board

Info

Publication number
JP3273113B2
JP3273113B2 JP28382595A JP28382595A JP3273113B2 JP 3273113 B2 JP3273113 B2 JP 3273113B2 JP 28382595 A JP28382595 A JP 28382595A JP 28382595 A JP28382595 A JP 28382595A JP 3273113 B2 JP3273113 B2 JP 3273113B2
Authority
JP
Japan
Prior art keywords
weight
wiring board
parts
multilayer wiring
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP28382595A
Other languages
Japanese (ja)
Other versions
JPH09130044A (en
Inventor
祐二 飯野
孝浩 松岡
昭哉 藤崎
公一 永田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP28382595A priority Critical patent/JP3273113B2/en
Publication of JPH09130044A publication Critical patent/JPH09130044A/en
Application granted granted Critical
Publication of JP3273113B2 publication Critical patent/JP3273113B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子が収容
搭載される半導体素子収納用パッケージや、半導体素子
の他にコンデンサや抵抗体等の各種電子部品が搭載され
る混成集積回路装置等に用いられるセラミック多層配線
基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device housing package in which a semiconductor device is housed and mounted, and a hybrid integrated circuit device in which various electronic components such as capacitors and resistors are mounted in addition to the semiconductor device. The present invention relates to a ceramic multilayer wiring board to be used.

【0002】[0002]

【従来の技術】従来より、半導体素子収納用パッケージ
や混成集積回路装置等に用いられるセラミック多層配線
基板は、一般に、アルミナを主成分とするセラミック粉
末に有機物系バインダーを添加して混練した泥漿を、ド
クターブレード法等によってシート状に成形した後、複
数のセラミックグリーンシートを積層して焼成したアル
ミナ質焼結体から成る絶縁基体が用いられている。
2. Description of the Related Art Conventionally, a ceramic multilayer wiring board used for a package for accommodating a semiconductor element, a hybrid integrated circuit device, or the like generally uses a slurry obtained by adding an organic binder to a ceramic powder containing alumina as a main component and kneading it. An insulating substrate made of an alumina sintered body formed by laminating a plurality of ceramic green sheets after forming them into a sheet by a doctor blade method or the like is used.

【0003】係る絶縁基体には、その表面あるいは内部
に配線導体として、タングステン(W)やモリブデン
(Mo)等の高融点金属から成るメタライズ金属層が配
設され、更に各層の前記配線導体は絶縁基体内に設けた
前記同様の高融点金属から成るスルーホール導体で互い
に接続されている。
A metallized metal layer made of a refractory metal such as tungsten (W) or molybdenum (Mo) is provided on the surface or inside of the insulating base as a wiring conductor, and the wiring conductor of each layer is insulated. They are connected to each other by through-hole conductors made of the same high-melting point metal provided in the base.

【0004】前記多層配線基板を、例えば半導体素子収
納用パッケージに適用する場合は、その絶縁基体の凹部
底面に半導体素子をガラスあるいは樹脂、ロウ材等の接
着剤を介して接着固定するとともに、半導体素子の各電
極は凹部周辺に位置する配線導体にボンディングワイヤ
を介して電気的に接続され、金属やセラミックス等から
成る蓋体を前記凹部を塞ぐように前記接着剤と同様の封
止材を介して接合し、絶縁基体の凹部内に半導体素子を
気密に収容することにより最終製品としての半導体装置
とされてきた。
When the multilayer wiring board is applied to, for example, a package for accommodating a semiconductor element, the semiconductor element is bonded and fixed to the bottom surface of the concave portion of the insulating base via an adhesive such as glass, resin or brazing material. Each electrode of the element is electrically connected to a wiring conductor located around the concave portion via a bonding wire, and a cover made of metal, ceramics, or the like is interposed via a sealing material similar to the adhesive so as to cover the concave portion. And a semiconductor device as a final product by hermetically housing the semiconductor element in a concave portion of the insulating base.

【0005】近年、高周波化および高密度化が進むIC
やLSI等の半導体素子を搭載する多層配線基板は、半
導体素子の高速化と放熱を計ると共に該半導体素子をコ
ンパクトに搭載するため、例えば半導体素子の表面電極
を前記多層配線基板の配線用電極にハンダバンプ等によ
り直接接続するフリップチップ接続法等が採用されるよ
うになってきている。
[0005] In recent years, ICs with higher frequencies and higher densities have progressed.
A multi-layer wiring board on which a semiconductor element such as an LSI or the like is mounted. In order to increase the speed and radiate heat of the semiconductor element and to mount the semiconductor element compactly, for example, a surface electrode of the semiconductor element is used as a wiring electrode of the multilayer wiring board. A flip chip connection method of directly connecting with solder bumps or the like has been adopted.

【0006】前記フリップチップ接続法は、前述のよう
に半導体素子の表面電極を直接、多層配線基板の配線用
電極に接続することから高い平坦度が要求されており、
該平坦度を確保するために積層体の密度や焼成時の温度
分布を均一にする等の各種方法が講じられていた。
In the flip-chip connection method, a high flatness is required because the surface electrode of the semiconductor element is directly connected to the wiring electrode of the multilayer wiring board as described above.
In order to ensure the flatness, various methods have been taken such as making the density of the laminate and the temperature distribution during firing uniform.

【0007】しかしながら、前記電気絶縁性アルミナ質
焼結体とメタライズ金属層との熱膨張係数は、例えば室
温から500℃の温度範囲で、それぞれ約7.5×10
-6/℃と4.5〜5.4×10-6/℃程度と異なること
から、同時焼成すると焼成過程での収縮差に伴って多層
配線基板に反りやうねり等を生じ、例えば反りでは単位
長さあたり1.04μm/mmを越えるような変形が発
生し、平坦度の良好な高品質の配線基板を歩留り良く得
ることが困難であった。
However, the coefficient of thermal expansion between the electrically insulating alumina-based sintered body and the metallized metal layer is, for example, about 7.5 × 10 5 in a temperature range from room temperature to 500 ° C.
−6 / ° C. and about 4.5 to 5.4 × 10 −6 / ° C., the simultaneous firing causes warpage or undulation in the multilayer wiring board due to a difference in shrinkage in the firing process. Deformation exceeding 1.04 μm / mm per unit length occurred, and it was difficult to obtain a high-quality wiring board with good flatness and good yield.

【0008】そこで、係る問題を解消するために、治具
を用いた矯正方法や、無機材料の軟化温度より高く、絶
縁基体であるセラミック基板の焼成温度より低い温度領
域で予備焼結した後、荷重をかけて本焼成する方法等が
提案されている(特公平2−25277号公報、特開平
4−31368号公報参照)。
In order to solve the above problem, a straightening method using a jig, a preliminary sintering in a temperature range higher than the softening temperature of the inorganic material and lower than the firing temperature of the ceramic substrate as the insulating base, There has been proposed a method of performing main firing under a load (see Japanese Patent Publication No. 2-25277 and Japanese Patent Laid-Open Publication No. 4-31368).

【0009】[0009]

【発明が解決しようとする課題】しかしながら、前記提
案では多層配線基板の反りやうねり等の変形は低減され
るものの、予備焼結した後、更に本焼成するという複数
の焼成工程を要することから製造コストが著しく増大す
るという課題があった。
However, in the above-mentioned proposal, although the deformation such as warpage or undulation of the multilayer wiring board is reduced, a plurality of firing steps of pre-sintering and further firing are required. There was a problem that the cost was significantly increased.

【0010】[0010]

【発明の目的】本発明は前記課題に鑑み成されたもの
で、その目的は、複数の焼成工程を必要とせず、製造コ
ストが低くかつ反りやうねり等の変形を効果的に防止し
た、平坦度の良好な多層配線基板を提供することにあ
る。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has as its object to reduce the manufacturing cost and to effectively prevent deformation such as warpage or undulation without requiring a plurality of firing steps. An object of the present invention is to provide a multilayer wiring board having a good degree.

【0011】[0011]

【課題を解決するための手段】本発明の多層配線基板
は、アルミナ質焼結体の積層体から成る絶縁基体の表面
や内部にメタライズ金属層の配線パターンが形成されて
構成されたもので、該多層配線基板の少なくとも表層直
下に形成されたメタライズ金属層、即ちタングステン
(W)、モリブデン(Mo)の一種以上から成る高融点
金属とガラスから成る配線導体層が、該配線導体層の厚
さ方向の断面におけるガラス成分の内、シリカ(SiO
2 )、カルシア(CaO)、マグネシア(MgO)が示
す分布の最大含有値が、配線導体層の厚さに対して30
〜70%の範囲内にあり、該最大含有値が、前記高融点
金属100重量部に対してそれぞれ6.62〜7.58
重量部、1.23〜1.40重量部、0.95〜1.0
8重量部であることを特徴とするものである。
A multilayer wiring board according to the present invention comprises a wiring pattern of a metallized metal layer formed on the surface or inside of an insulating base made of a laminate of alumina-based sintered bodies. A metallized metal layer formed at least immediately below the surface layer of the multilayer wiring board, that is, a wiring conductor layer made of glass and a refractory metal made of at least one of tungsten (W) and molybdenum (Mo) has a thickness of the wiring conductor layer. Silica (SiO 2)
2 ), the maximum content of the distribution shown by calcia (CaO) and magnesia (MgO) is 30 with respect to the thickness of the wiring conductor layer.
And the maximum content is in the range of 6.62 to 7.58 with respect to 100 parts by weight of the refractory metal, respectively.
Parts by weight, 1.23 to 1.40 parts by weight, 0.95 to 1.0
8 parts by weight.

【0012】本発明の多層配線基板において、配線導体
層の厚さ方向の断面におけるガラス成分のシリカ(Si
2 )及びカルシア(CaO)、マグネシア(MgO)
が示す分布の各最大含有値が、配線導体層の厚さに対し
て30〜70%の範囲外で、かつその値が前記高融点金
属100重量部に対してそれぞれ6.62〜7.58重
量部、1.23〜1.40重量部、0.95〜1.08
重量部の範囲外である場合、即ち、前記最大含有値の位
置が30%未満、またはその値が前記各ガラス成分の下
限値未満の場合には、配線導体層を形成するメタライズ
金属層の焼結が不十分となり、逆に前記最大含有値の位
置が70%を越えるか、あるいはその値が前記各ガラス
成分の上限値を越えるとメタライズ金属層の過度の焼結
により、高融点金属自体の粒成長も起こりメタライズ金
属層の焼成収縮が大となり、多層配線基板に反りが生じ
る等の問題が発生する。
In the multilayer wiring board of the present invention, the glass component silica (Si) is used in a cross section of the wiring conductor layer in the thickness direction.
O 2 ) and calcia (CaO), magnesia (MgO)
Is outside the range of 30 to 70% with respect to the thickness of the wiring conductor layer, and the value is 6.62 to 7.58 with respect to 100 parts by weight of the refractory metal, respectively. Parts by weight, 1.23 to 1.40 parts by weight, 0.95 to 1.08
When the content is out of the range of parts by weight, that is, when the position of the maximum content value is less than 30% or the value is less than the lower limit value of each glass component, the firing of the metallized metal layer forming the wiring conductor layer is performed. If the maximum content exceeds 70%, or if the value exceeds the upper limit of each glass component, excessive sintering of the metallized metal layer causes the refractory metal itself to become insufficient. Grain growth also occurs, and firing shrinkage of the metallized metal layer becomes large, causing problems such as warpage of the multilayer wiring board.

【0013】従って、前記ガラス成分の各最大含有値が
示す位置は、配線導体層の厚さに対して30〜70%に
限定され、前記最大含有値は前記高融点金属100重量
部に対してそれぞれ6.62〜7.58重量部、1.2
3〜1.40重量部、0.95〜1.08重量部の範囲
内に特定される。
Accordingly, the position indicated by each maximum content value of the glass component is limited to 30 to 70% with respect to the thickness of the wiring conductor layer, and the maximum content value is defined with respect to 100 parts by weight of the high melting point metal. 6.62 to 7.58 parts by weight, 1.2 respectively
It is specified in the range of 3 to 1.40 parts by weight and 0.95 to 1.08 parts by weight.

【0014】また、絶縁基体と配線導体層を形成するメ
タライズ金属層との熱膨張差に起因6る応力は、多層配
線基板内部にクラックを生じる恐れがあることから、メ
タライズ金属層で吸収して絶縁基体に集中する応力をよ
り効果的に緩和するという点で、メタライズ金属層のヤ
ング率等の剛性は高いことが望ましい。
Further, the stress caused by the difference in thermal expansion between the insulating base and the metallized metal layer forming the wiring conductor layer is absorbed by the metallized metal layer because cracks may be generated inside the multilayer wiring board. The metallized metal layer desirably has high rigidity such as Young's modulus in that the stress concentrated on the insulating base is more effectively reduced.

【0015】更に、前記メタライズ金属層はタングステ
ン(W)、モリブデン(Mo)等の高融点金属の一種以
上であればいずれでも良く、焼結後に多孔質となるよう
にメタライズ金属層を形成することにより、前記応力集
中の低減効果をより大きくすることも可能である。
The metallized metal layer may be any one or more of high melting point metals such as tungsten (W) and molybdenum (Mo). The metallized metal layer is formed so as to be porous after sintering. Accordingly, the effect of reducing the stress concentration can be further increased.

【0016】[0016]

【作用】本発明の多層配線基板は、アルミナ質焼結体か
ら成る絶縁基体の表面や内部にメタライズ金属層の配線
パターンを有する多層配線基板であり、該多層配線基板
の少なくとも表層直下に形成されたタングステン
(W)、モリブデン(Mo)の一種以上から成る高融点
金属とガラスから成る配線導体層の厚さ方向の断面にお
いて、ガラス成分のシリカ(SiO2 )及びカルシア
(CaO)、マグネシア(MgO)が示す分布の各最大
含有値の位置が、配線導体層の厚さに対して30〜70
%の範囲内にあり、かつ前記ガラス成分の最大含有値が
それぞれ前記高融点金属100重量部に対して6.62
〜7.58重量部、1.23〜1.40重量部、0.9
5〜1.08重量部の範囲内であることから、メタライ
ズ層とアルミナ質焼結体との収縮の整合が良くなり、焼
成過程での収縮差による多層配線基板に反りやうねり等
の変形が生じなくなるとともに、前記熱膨張差に起因し
て発生する応力も緩和され、その結果、メタライズ金属
層を絶縁基体に強固に取着させておくことも可能とな
る。
The multilayer wiring board of the present invention is a multilayer wiring board having a wiring pattern of a metallized metal layer on the surface or inside of an insulating substrate made of an alumina sintered body, and formed at least immediately below the surface layer of the multilayer wiring board. In a cross section in the thickness direction of a wiring conductor layer made of glass and a high melting point metal made of at least one of tungsten (W) and molybdenum (Mo), silica (SiO 2 ), calcia (CaO), and magnesia (MgO ) Is 30 to 70 with respect to the thickness of the wiring conductor layer.
% And the maximum content of the glass component is 6.62 with respect to 100 parts by weight of the high melting point metal.
-7.58 parts by weight, 1.23-1.40 parts by weight, 0.9
Since the content is within the range of 5 to 1.08 parts by weight, the matching of shrinkage between the metallized layer and the alumina-based sintered body is improved, and deformation such as warpage or undulation of the multilayer wiring board due to a difference in shrinkage in the firing process is achieved. As a result, the stress generated due to the difference in thermal expansion is reduced, and as a result, the metallized metal layer can be firmly attached to the insulating base.

【0017】[0017]

【発明の実施の形態】次に、本発明の多層配線基板を図
面に基づき詳細に説明する。図1は、本発明の多層配線
基板を半導体素子がフリップチップ接続法で収容搭載さ
れる半導体素子収納用パッケージに適用した場合の一実
施例を示す斜視図であり、図2は図1の半導体素子収納
用パッケージに半導体素子を搭載した状態を示す要部断
面図である。
Next, a multilayer wiring board of the present invention will be described in detail with reference to the drawings. FIG. 1 is a perspective view showing an embodiment in which the multilayer wiring board of the present invention is applied to a semiconductor element housing package in which semiconductor elements are housed and mounted by a flip-chip connection method, and FIG. It is principal part sectional drawing which shows the state which mounted the semiconductor element in the element storage package.

【0018】図1及び図2において、1はメタライズ金
属層から成る配線導体層3を絶縁基体2中に一体的に形
成した多層配線基板であり、各層の配線導体層3は絶縁
基体6を貫通して設けたスルーホール導体4で互いに接
続されている。
1 and 2, reference numeral 1 denotes a multilayer wiring board in which a wiring conductor layer 3 made of a metallized metal layer is integrally formed in an insulating base 2, and each of the wiring conductor layers 3 penetrates through the insulating base 6. Are connected to each other by through-hole conductors 4 provided.

【0019】また、図2に示す半導体素子を搭載した状
態の半導体素子収納用パッケージは、半導体素子5の表
面電極を絶縁基体2の上面中央部にスルーホール導体4
で引き出された図1に示す配線用電極8にハンダバンプ
6で直接接続されており、そこから各層の配線導体層3
を接続するスルーホール導体4を介して下面に導出され
ている。
In the package for mounting a semiconductor element shown in FIG. 2 with the semiconductor element mounted thereon, the surface electrode of the semiconductor element 5 is provided at the center of the upper surface of the insulating base 2 by a through-hole conductor 4.
1 is directly connected to the wiring electrode 8 shown in FIG.
Through the through-hole conductor 4 for connecting to the lower surface.

【0020】更に、絶縁基体2の下面に導出された部位
には、外部電気回路と接続する外部リード端子7が電気
的に接続されて、外部リード端子7に半導体素子5の各
電極が電気的に導通するようになっており、最終的に前
記半導体素子5の上部には、封止材を介して金属やセラ
ミックス等から成る蓋体(不図示)を接合し、半導体素
子5を絶縁基体2の上面中央部に気密に搭載することと
なる。
Further, an external lead terminal 7 connected to an external electric circuit is electrically connected to a portion led out to the lower surface of the insulating base 2, and each electrode of the semiconductor element 5 is electrically connected to the external lead terminal 7. Finally, a lid (not shown) made of metal, ceramics, or the like is joined to the upper portion of the semiconductor element 5 via a sealing material, so that the semiconductor element 5 is electrically connected to the insulating base 2. It is mounted air-tight at the center of the upper surface of the.

【0021】本発明の多層配線基板は、タングステン
(W)、モリブデン(Mo)の一種以上から成る高融点
金属とガラスから成るメタライズ金属層で形成された少
なくとも表層直下の配線導体層3が、その厚さ方向の断
面に現れる前記ガラス成分の最大含有値の位置が配線導
体層3の厚さに対して30〜70%の範囲内にあり、前
記ガラス成分のそれぞれの最大含有値が、前記高融点金
属100重量部に対して6.62〜7.58重量部、
1.23〜1.40重量部、0.95〜1.08重量部
の範囲内にあるものである。
In the multilayer wiring board of the present invention, at least the wiring conductor layer 3 immediately below the surface layer formed of a metalized metal layer made of glass and a refractory metal made of at least one of tungsten (W) and molybdenum (Mo) is used. The position of the maximum content value of the glass component appearing in the cross section in the thickness direction is within a range of 30 to 70% with respect to the thickness of the wiring conductor layer 3, and the maximum content value of each of the glass components is higher than the high content. 6.62 to 7.58 parts by weight based on 100 parts by weight of the melting point metal;
1.23 to 1.40 parts by weight, 0.95 to 1.08 parts by weight.

【0022】[0022]

【実施例】本発明の配線基板を評価するに際し、先ず、
アルミナ質成形体として、Al23 90〜96重量%
に対して、SiO2 、MgO、CaO等を4〜10重量
%添加混合した各原料粉末に、周知の有機バインダー、
可塑剤、溶剤を添加混合して泥漿を調製し、該泥漿を周
知のドクターブレード法やカレンダーロール法等のテー
プ成形技術により厚さ約500μmの絶縁基体用のセラ
ミックグリーンシートにそれぞれ成形した。
DESCRIPTION OF THE PREFERRED EMBODIMENTS In evaluating the wiring board of the present invention, first,
As alumina formed body, Al 2 O 3 90~96 wt%
On the other hand, a known organic binder was added to each raw material powder obtained by adding and mixing 4 to 10% by weight of SiO 2 , MgO, CaO and the like.
A slurry was prepared by adding and mixing a plasticizer and a solvent, and the slurry was formed into a ceramic green sheet for an insulating substrate having a thickness of about 500 μm by a well-known tape forming technique such as a doctor blade method or a calendar roll method.

【0023】次に、粒径が1乃至5μmのW、Mo、及
びMoの含有量が20重量%、30重量%のタングステ
ン(W)−モリブデン(Mo)の各高融点金属を97.
9重量%と、Al2 3 を2.0重量%、Nb2 5
0.1重量%に、粘結剤や界面活性剤等の有機溶剤及び
溶媒を添加混練し、メタライズ金属層用のペースト試料
を得た。
Next, W, Mo having a particle diameter of 1 to 5 μm, and tungsten (W) -molybdenum (Mo) having a content of 20% by weight and 30% by weight of molybdenum metal having a melting point of 97% were used.
9% by weight, Al 2 O 3 to 2.0% by weight, Nb 2 O 5 to 0.1% by weight, kneading and kneading an organic solvent such as a binder and a surfactant and a solvent, and kneading the mixture. A paste sample was obtained.

【0024】かくして得られたメタライズ金属層用のペ
ースト試料を、前記セラミックグリーンシートの一方の
外表面全面にスクリーン印刷法により印刷した後、セラ
ミックグリーンシートを縦70mm、横70mmの正方
形に切断し、これを窒素と水素から成る還元雰囲気中、
1480〜1600℃の温度範囲で焼成し、アルミナ質
焼結体から成る絶縁基体表面に厚さ約20μmのメタラ
イズ金属層を被着形成した評価用試料を作製した。
After the paste sample for a metallized metal layer thus obtained is printed on the entire outer surface of one of the ceramic green sheets by a screen printing method, the ceramic green sheet is cut into a square having a length of 70 mm and a width of 70 mm. In a reducing atmosphere consisting of nitrogen and hydrogen,
The sample was fired in a temperature range of 1480 to 1600 ° C., and an evaluation sample in which a metallized metal layer having a thickness of about 20 μm was formed on the surface of an insulating substrate made of an alumina sintered body was prepared.

【0025】[0025]

【表1】 [Table 1]

【0026】先ず前記評価用試料を用いて、該評価用試
料のメタライズ金属層表面をダイヤモンド針を装着した
接触型表面粗さ計で対角線方向に触針してその反り形状
を計測し、単位長さあたりの反りを算出してその最大値
を求めた。
First, using the evaluation sample, the surface of the metallized metal layer of the evaluation sample is diagonally contacted with a contact-type surface roughness meter equipped with a diamond needle, and the warped shape is measured. The warpage was calculated and the maximum value was calculated.

【0027】次に、反り形状の計測を終えた評価用試料
を切断し、その断面を角度を付けて研磨した後、メタラ
イズ金属層の研磨面を10等分してそれぞれEPMAに
より各位置でのSiO2 、CaO、MgOの含有量を定
量分析し、その分布を測定した。
Next, the evaluation sample after the measurement of the warped shape is cut, and the cross section thereof is polished at an angle. Then, the polished surface of the metallized metal layer is divided into 10 equal parts, and EPMA is applied at each position. The contents of SiO 2 , CaO, and MgO were quantitatively analyzed and the distribution was measured.

【0028】尚、EPMA分析の基準物質として、評価
用試料のアルミナ組成と純W、純Moを採用した。
As a reference substance for the EPMA analysis, the alumina composition, pure W and pure Mo of the evaluation sample were used.

【0029】また、評価用試料のメタライズ金属層表面
にニッケル(Ni)を被覆し、その上に鉄−ニッケル系
のリードピンを銀ろうにて接合した後、該リードピンを
10mm/minの引張速度で引っ張り、剥離した時の
荷重をメタライズ強度として評価した。
Further, the surface of the metallized metal layer of the sample for evaluation was coated with nickel (Ni), and an iron-nickel lead pin was bonded thereon with a silver solder, and then the lead pin was pulled at a tensile speed of 10 mm / min. The load at the time of pulling and peeling was evaluated as metallized strength.

【0030】一方、前記メタライズ金属層を被着形成せ
ずに前記同様にして焼成した絶縁基体に相当するアルミ
ナ質焼結体を用いて嵩密度を測定した。
On the other hand, the bulk density was measured using an alumina-based sintered body corresponding to an insulating substrate fired in the same manner as described above without forming the metallized metal layer.

【0031】[0031]

【表2】 [Table 2]

【0032】[0032]

【表3】 [Table 3]

【0033】[0033]

【表4】 [Table 4]

【0034】[0034]

【表5】 [Table 5]

【0035】表から明らかなように、SiO2 、Ca
O、MgOの各最大含有値が配線導体層の厚さに対して
30%未満、あるいは70%を越えるか、前記最大含有
値がそれぞれの本願請求の範囲外となる試料番号1、
4、5、10、11、13、14、17は、反りが最大
値で1.04μm/mm以上となるのに対して、本発明
の試料はいずれも1.03μm/mm以下となってい
る。
As is clear from the table, SiO 2 , Ca
Sample No. 1 in which the maximum content of O and MgO is less than 30% or more than 70% with respect to the thickness of the wiring conductor layer, or the maximum content is outside the scope of the claims of the present application.
4, 5, 10, 11, 13, 14, and 17 have a maximum warpage of 1.04 μm / mm or more, whereas the samples of the present invention have a warpage of 1.03 μm / mm or less. .

【0036】尚、本発明は前述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更が可能である。
It should be noted that the present invention is not limited to the above-described embodiment, and various changes can be made without departing from the gist of the present invention.

【0037】[0037]

【発明の効果】本発明の多層配線基板によれば、多層配
線基板に形成されたメタライズ金属層から成る配線導体
層が、その厚さ方向の断面におけるガラス成分の内、シ
リカ(SiO2 )、カルシア(CaO)、マグネシア
(MgO)が示す分布の最大含有値が、配線導体層の厚
さに対して30〜70%の範囲内にあり、前記それぞれ
の最大含有値が、メタライズ金属層中の高融点金属10
0重量部に対して6.62〜7.58重量部、1.23
〜1.40重量部、0.95〜1.08重量部の範囲内
であることから、一回の焼成で低コストで反りやうねり
等の変形を効果的に防止でき、平坦度の良好な多層配線
基板を得ることができる。
According to the multilayer wiring board of the present invention, the wiring conductor layer formed of the metallized metal layer formed on the multilayer wiring board is made of silica (SiO 2 ), The maximum content value of the distribution represented by calcia (CaO) and magnesia (MgO) is in the range of 30 to 70% with respect to the thickness of the wiring conductor layer, and the maximum content value of each of the distributions in the metalized metal layer is High melting point metal 10
6.62 to 7.58 parts by weight, 1.23 parts by weight with respect to 0 parts by weight
Since it is within a range of from 1.40 parts by weight and 0.95 to 1.08 parts by weight, deformation such as warpage or undulation can be effectively prevented at a low cost by one firing, and good flatness can be obtained. A multilayer wiring board can be obtained.

【0038】更に、焼成時にメタライズ金属層と絶縁基
体との間に両者の熱膨張係数の相違に起因する熱応力が
発生しても、これが多層配線基板の内部に残留すること
はほとんどなく、その結果、配線基板に外力や熱衝撃力
が印加されても絶縁基体にクラックが発生することはな
く、配線導体に断線等を生じるのを有効に防止すること
ができ、同時に前記配線導体を絶縁基体に強固に取着さ
せておくことが可能となる。
Further, even if a thermal stress is generated between the metallized metal layer and the insulating substrate during firing due to the difference in the thermal expansion coefficient between the metalized metal layer and the insulating substrate, the thermal stress hardly remains in the multilayer wiring board. As a result, even if an external force or a thermal shock force is applied to the wiring board, no crack is generated in the insulating base, and it is possible to effectively prevent the wiring conductor from being disconnected or the like. It can be firmly attached to the vehicle.

【0039】その結果、半導体素子の高速化と放熱が有
効に実現できると共に、該半導体素子をコンパクトに搭
載することができ、高密度実装が要求されている各種制
御機器や情報通信機器等をはじめとする用途に極めて有
用である。
As a result, the speeding up and heat dissipation of the semiconductor element can be effectively realized, and the semiconductor element can be mounted compactly, such as various control equipment and information communication equipment which are required to be mounted at high density. It is extremely useful for the use of

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の多層配線基板を半導体素子がフリップ
チップ接続法で収容搭載される半導体素子収納用パッケ
ージに適用した場合の一実施例を示す斜視図である。
FIG. 1 is a perspective view showing an embodiment in which a multilayer wiring board of the present invention is applied to a semiconductor element housing package in which semiconductor elements are housed and mounted by a flip chip connection method.

【図2】図1の半導体素子収納用パッケージに半導体素
子を搭載した状態を示す要部断面図である。
FIG. 2 is a cross-sectional view illustrating a state where a semiconductor element is mounted on the semiconductor element storage package of FIG. 1;

【符号の説明】[Explanation of symbols]

1 多層配線基板 2 絶縁基体 3 配線導体層 Reference Signs List 1 multilayer wiring board 2 insulating base 3 wiring conductor layer

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平7−122681(JP,A) (58)調査した分野(Int.Cl.7,DB名) H05K 3/46 H01L 23/12 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-7-122681 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H05K 3/46 H01L 23/12

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】アルミナ質焼結体から成る絶縁基体の表面
あるいは内部に、高融点金属であるタングステン
(W)、モリブデン(Mo)の一種以上とガラスから成
る配線導体層を形成した多層配線基板であって、前記配
線導体層の厚さ方向の断面におけるガラス成分のシリカ
(SiO2 )、カルシア(CaO)、マグネシア(Mg
O)の分布が、配線導体層の厚さに対して30〜70%
の範囲で最大含有値を示し、該最大含有値が高融点金属
100重量部に対してそれぞれ6.62〜7.58重量
部、1.23〜1.40重量部、0.95〜1.08重
量部の範囲内であることを特徴とする多層配線基板。
1. A multilayer wiring board having a wiring conductor layer made of glass and at least one of tungsten (W) and molybdenum (Mo), which are refractory metals, formed on the surface or inside of an insulating substrate made of an alumina sintered body. And a glass component of silica (SiO 2 ), calcia (CaO), and magnesia (Mg) in a cross section in the thickness direction of the wiring conductor layer.
O) distribution is 30 to 70% with respect to the thickness of the wiring conductor layer.
In the range of 6.62 to 7.58 parts by weight, 1.23 to 1.40 parts by weight and 0.95 to 1.40 parts by weight, respectively, based on 100 parts by weight of the high melting point metal. A multilayer wiring board characterized by being in the range of 08 parts by weight.
JP28382595A 1995-10-31 1995-10-31 Multilayer wiring board Expired - Fee Related JP3273113B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28382595A JP3273113B2 (en) 1995-10-31 1995-10-31 Multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28382595A JP3273113B2 (en) 1995-10-31 1995-10-31 Multilayer wiring board

Publications (2)

Publication Number Publication Date
JPH09130044A JPH09130044A (en) 1997-05-16
JP3273113B2 true JP3273113B2 (en) 2002-04-08

Family

ID=17670647

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28382595A Expired - Fee Related JP3273113B2 (en) 1995-10-31 1995-10-31 Multilayer wiring board

Country Status (1)

Country Link
JP (1) JP3273113B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4041268B2 (en) * 2000-07-05 2008-01-30 京セラ株式会社 Wiring board manufacturing method

Also Published As

Publication number Publication date
JPH09130044A (en) 1997-05-16

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