JP3450119B2 - Metallized composition and wiring board using the same - Google Patents
Metallized composition and wiring board using the sameInfo
- Publication number
- JP3450119B2 JP3450119B2 JP06793496A JP6793496A JP3450119B2 JP 3450119 B2 JP3450119 B2 JP 3450119B2 JP 06793496 A JP06793496 A JP 06793496A JP 6793496 A JP6793496 A JP 6793496A JP 3450119 B2 JP3450119 B2 JP 3450119B2
- Authority
- JP
- Japan
- Prior art keywords
- metallized
- wiring board
- weight
- insulating substrate
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- C—CHEMISTRY; METALLURGY
- C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
- C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
- C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
- C04B41/009—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone characterised by the material treated
-
- C—CHEMISTRY; METALLURGY
- C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
- C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
- C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
- C04B41/45—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements
- C04B41/50—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements with inorganic materials
- C04B41/51—Metallising, e.g. infiltration of sintered ceramic preforms with molten metal
- C04B41/5133—Metallising, e.g. infiltration of sintered ceramic preforms with molten metal with a composition mainly composed of one or more of the refractory metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、アルミナ質セラミ
ックスを用いた絶縁基体用のメタライズ組成物及びそれ
を用いた配線基板に関するもので、特に絶縁基体とメタ
ライズ配線層の同時焼成可能温度範囲でほぼ一定の焼成
収縮率を示すメタライズ組成物と、それを用いた配線基
板として、アルミナ質セラミックスから成る絶縁基体と
配線層とを同時に焼成する多層配線基板や半導体素子収
納用パッケージ等、とりわけ半導体素子がコンパクトに
収容搭載でき、更にコンデンサや抵抗体等の各種電子部
品をも密に搭載することができる平坦度が良好で低コス
トの配線基板に適用されるものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metallized composition for an insulating substrate using alumina-based ceramics and a wiring board using the same, and more particularly to a metallized composition for an insulating substrate in a temperature range in which simultaneous firing of the insulating substrate and the metallized wiring layer is possible. A metallized composition exhibiting a constant firing shrinkage ratio and a wiring board using the same are used as a wiring board, such as a multilayer wiring board for simultaneously firing an insulating base made of alumina ceramics and a wiring layer, a package for housing a semiconductor element, and particularly a semiconductor element. The present invention is applied to a low-cost wiring board that can be compactly housed and mounted, and that various electronic components such as capacitors and resistors can be densely mounted and that has good flatness.
【０００２】[0002]
【従来の技術】従来より、半導体素子収納用パッケージ
や混成集積回路装置等に用いられる配線基板は、アルミ
ナ質セラミックスから成る絶縁基体の表面あるいは内部
にＷやＭｏ等の高融点金属から成るメタライズ配線層が
設けられ、該メタライズ配線層はスルーホール導体で互
いに接続されており、例えば半導体素子収納用パッケー
ジに適用する場合には、前記絶縁基体の凹部底面に半導
体素子が接着固定され、該半導体素子はボンディングワ
イヤを介して前記メタライズ配線層と電気的に接続さ
れ、更に前記凹部を塞ぐように蓋体を接合して前記半導
体素子が絶縁基体の凹部内に気密に収容されて最終製品
となっていた。2. Description of the Related Art Conventionally, a wiring board used for a package for housing a semiconductor element, a hybrid integrated circuit device or the like is a metallized wiring made of a refractory metal such as W or Mo on the surface or inside of an insulating substrate made of alumina ceramics. A layer is provided, and the metallized wiring layers are connected to each other by through-hole conductors. For example, when applied to a package for housing a semiconductor element, the semiconductor element is bonded and fixed to the bottom surface of the concave portion of the insulating base. Is electrically connected to the metallized wiring layer through a bonding wire, and a lid is joined so as to close the recess, and the semiconductor element is hermetically housed in the recess of the insulating base body to form a final product. It was
【０００３】近年、高周波化および高密度化が進むＩＣ
やＬＳＩ等の半導体素子を搭載する配線基板は、半導体
素子の高速化と放熱性を良好ならしめるとともに該半導
体素子をコンパクトに搭載するため、例えば、半導体素
子の表面電極を前記配線基板の配線用電極にハンダバン
プ等により直接接続するフリップチップ接続法等が採用
されるようになってきている。In recent years, ICs are becoming higher in frequency and higher in density.
A wiring board on which a semiconductor element such as a semiconductor device or an LSI is mounted in order to improve the speed and heat dissipation of the semiconductor element and to mount the semiconductor element compactly. For example, the surface electrode of the semiconductor element is used for wiring the wiring board. A flip-chip connection method or the like in which the electrodes are directly connected by solder bumps or the like has been adopted.
【０００４】前記フリップチップ接続法は、前述のよう
に半導体素子の表面電極を直接、配線基板の配線用電極
に接続することから高い平坦度が要求されており、該平
坦度を確保するために配線基板を構成する積層体の密度
や焼成時の温度分布を均一にする等の各種方法が講じら
れてきた。In the flip-chip connection method, a high flatness is required because the surface electrode of the semiconductor element is directly connected to the wiring electrode of the wiring substrate as described above, and in order to secure the flatness. Various methods have been taken such as making the density of the laminate constituting the wiring board and the temperature distribution during firing uniform.
【０００５】しかしながら、前記電気絶縁性アルミナ質
焼結体とメタライズ配線層との熱膨張係数は、例えば、
室温から５００℃の温度範囲で、それぞれ約７．５×１
０-6／℃と４．５〜５．４×１０-6／℃程度を示し、そ
の値が大きく異なることから、同時焼成すると焼成過程
での収縮差に伴って配線基板に反りやうねり等を生じ、
例えば反りでは長さ１ｍｍ当たり１．０４μｍを越える
ような変形が発生し、平坦度の良好な高品質の配線基板
を歩留り良く得ることが困難であった。However, the coefficient of thermal expansion between the electrically insulating alumina sintered body and the metallized wiring layer is, for example,
Approximately 7.5 x 1 each in the temperature range from room temperature to 500 ° C
0 -6 / ° C and 4.5-5.4 × 10 -6 / ° C are shown, and the values are very different. Therefore, when co-firing, the wiring board is warped or undulated due to the difference in shrinkage in the firing process. Results in
For example, the warpage causes a deformation of more than 1.04 μm per 1 mm in length, and it is difficult to obtain a high-quality wiring board having a good flatness with a good yield.
【０００６】そこで、係る問題を解消するために、治具
を用いて矯正する方法や、無機材料の軟化温度より高く
絶縁基体であるセラミック基板の焼成温度より低い温度
で予備焼結した後、荷重をかけて本焼成する方法等、各
種提案がなされている（特公平２−２５２７７号公報、
特開平４−３１３６８号公報参照）。Therefore, in order to solve such a problem, a method of straightening using a jig or pre-sintering at a temperature higher than the softening temperature of the inorganic material and lower than the firing temperature of the ceramic substrate, which is an insulating substrate, is used, and then the load is applied. Various proposals have been made, such as a method for performing main firing by heating (Japanese Patent Publication No. 2-25277).
See Japanese Patent Laid-Open No. 4-31368).
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、前記提
案では多層配線基板の反りやうねり等の変形は低減され
るものの、治具の取り扱いが煩雑でかつ該治具の維持管
理や、あるいは予備焼結した後、更に本焼成するという
複数の焼成工程を要すること等、いずれも製造コストが
著しく増大するという課題があった。However, in the above proposal, although the deformation of the multilayer wiring board such as warpage and undulation is reduced, the handling of the jig is complicated and the maintenance or pre-sintering of the jig is required. After that, there is a problem that the manufacturing cost is remarkably increased, because a plurality of firing steps of further main firing are required.
【０００８】[0008]
【発明の目的】本発明は前記課題に鑑みなされたもの
で、その目的は絶縁基体とメタライズ層とを同時焼成で
き、焼成治具や複数の焼成行程を必要とせず、製造コス
トが低く、かつ反りやうねり等の変形を効果的に防止で
きるメタライズ組成物及びそれを用いた平坦度の良好な
配線基板を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object thereof is to enable simultaneous firing of an insulating substrate and a metallized layer, a firing jig and a plurality of firing steps are not required, and the manufacturing cost is low. It is an object of the present invention to provide a metallized composition that can effectively prevent deformation such as warpage and undulation, and a wiring board using the same and having good flatness.
【０００９】[0009]
【課題を解決するための手段】本発明者等は、Ａｌ2Ｏ3
を含有する（９９重量％以上のアルミナ含有量を除く）
絶縁基体にＷまたはＭｏの少なくとも一種を主成分とす
るメタライズ配線層を形成するためのメタライズ組成物
として、Ｔｉ、Ｖ、Ｎｂ、Ｔａの各窒化物のいずれか一
種を０．１〜０．５重量％含有させ、残部がタングステ
ン（Ｗ）またはモリブデン（Ｍｏ）の少なくとも一種か
らなるものとすることにより、前記目的が達成されるこ
とを知見したものである。The present inventors have found that Al 2 O 3
Contains (excluding alumina content of 99% by weight or more)
As a metallized composition for forming a metallized wiring layer containing at least one of W and Mo as a main component on an insulating substrate, 0.1 to 0.5 of any one of nitrides of Ti, V, Nb, and Ta is used. % By weight with the balance being tungsten
At least one of molybdenum (W) or molybdenum (Mo)
It has been found that the above-mentioned object can be achieved by the following.
【００１０】また、かかる知見から本発明の配線基板
は、Ａｌ2Ｏ3を含有する（９９重量％以上のアルミナ含
有量を除く）絶縁基体に、Ｔｉ、Ｖ、Ｎｂ、Ｔａの各窒
化物のいずれか一種を０．１〜０．５重量％含有し、残
部がＷまたはＭｏの少なくとも一種から成るメタライズ
配線層を有するとともに、平坦度が１．０３μｍ／ｍｍ
以下であることを特徴とするものである。Further, from the above knowledge, the wiring substrate of the present invention has an insulating substrate containing Al 2 O 3 (excluding an alumina content of 99% by weight or more) and Ti, V, Nb and Ta.
0.1 to 0.5% by weight of any one of the compounds,
Has a metallized wiring layer made of at least one of W and Mo, and has a flatness of 1.03 μm / mm
It is characterized by the following.
【００１１】[0011]
【作用】本発明によれば、メタライズ組成物として主成
分のＷまたはＭｏの高融点金属に、Ｔｉ、Ｖ、Ｎｂ、Ｔ
ａの各窒化物のいずれか一種を０．１〜０．５重量％含
有させることにより、前記窒化物はＷまたはＭｏの粒子
間に介在して該高融点金属の焼結性を制御するように作
用し、その結果、メタライズ層の焼成収縮率が絶縁基体
とメタライズ配線層の同時焼成可能温度範囲でほぼ一定
の焼成収縮率を示すこととなる。According to the present invention, the refractory metal of W or Mo, which is the main component of the metallized composition, is added to Ti, V, Nb and T.
By containing 0.1 to 0.5% by weight of any one of the respective nitrides of a, the nitride is interposed between W or Mo particles to control the sinterability of the refractory metal. As a result, the firing shrinkage of the metallized layer exhibits a substantially constant firing shrinkage within the temperature range in which the insulating substrate and the metallized wiring layer can be simultaneously fired.
【００１２】[0012]
【発明の実施の形態】以下、本発明のメタライズ組成物
及びそれを用いた配線基板について詳細に述べる。BEST MODE FOR CARRYING OUT THE INVENTION The metallized composition of the present invention and a wiring board using the same are described in detail below.
【００１３】本発明のメタライズ組成物は、Ｔｉ、Ｖ、
Ｎｂ、Ｔａの各窒化物のいずれか一種を０．１〜０．５
重量％含有し、残部がＷ、Ｍｏの一種以上から成るもの
で、また、本発明の配線基板は係るメタライズ組成物
を、Ａｌ2Ｏ3を含有する（９９重量％以上のアルミナ含
有量を除く）絶縁基体の表面もしくはその内部に配線層
として印刷形成し、同時焼成してメタライズ配線層を被
着形成したものである。The metallized composition of the present invention comprises Ti, V,
0.1 to 0.5 of any one of Nb and Ta nitrides
Containing by weight%, the balance being those consisting of W, one or more kinds of Mo, also a wiring board according metallized compositions of the present invention, except for the Al 2 O 3 containing (99% or more by weight of alumina content ) A wiring layer is printed and formed on the surface of or inside the insulating substrate, and a metallized wiring layer is formed by co-firing.
【００１４】本発明におけるメタライズ組成物中の高融
点金属としてはＷまたはＭｏが挙げられ、双方を混合す
ることも可能である。The refractory metal in the metallized composition according to the present invention includes W or Mo, and it is possible to mix both.
【００１５】また、本発明のメタライズ組成物において
含有させるＴｉ、Ｖ、Ｎｂ、Ｔａの窒化物は、その含有
量が０．１重量％未満であるとメタライズ配線層の焼成
収縮率が絶縁基体とメタライズ配線層の同時焼成可能温
度範囲で前述のように大きく異なり、反りやうねり等の
変形を効果的に防止することができないことから、前記
窒化物の含有量は０．１重量％以上に限定される。If the Ti, V, Nb, and Ta nitrides contained in the metallized composition of the present invention are less than 0.1% by weight, the firing shrinkage of the metallized wiring layer will be higher than that of the insulating substrate. The content of the nitride is limited to 0.1% by weight or more because the metallized wiring layer has a large difference in the temperature range that can be co-fired as described above, and deformation such as warpage or undulation cannot be effectively prevented. To be done.
【００１６】逆に、前記窒化物の含有量が０．５重量％
を越えると、該窒化物がＡｌ2 Ｏ3を含有する絶縁基体
中に拡散し、該絶縁基体表面を変色させて外観不良を起
こす他、メタライズ配線層の電気抵抗値が増大する恐れ
があることから、前記窒化物の含有量は０．１〜０．５
重量％の範囲に限定される。On the contrary, the content of the nitride is 0.5% by weight.
If it exceeds the range, the nitride may diffuse into the insulating substrate containing Al 2 O 3 , discolor the surface of the insulating substrate to cause poor appearance, and the electrical resistance of the metallized wiring layer may increase. Therefore, the content of the nitride is 0.1 to 0.5.
It is limited to the range of% by weight.
【００１７】また、前記窒化物の粒径が高融点金属の
Ｗ、Ｍｏの粒径より大きくなると、該窒化物がＷもしく
はＭｏの粒子間に均一に分散しなくなり、その結果、不
均質な組織のメタライズ配線層が形成され、焼成収縮率
も場所によって異なる恐れがあり、添加する窒化物の粒
径は前記高融点金属の粒径よりも小さいものにしておく
ことが好ましい。If the grain size of the nitride is larger than the grain sizes of W and Mo of the refractory metal, the nitride is not uniformly dispersed between the grains of W or Mo, and as a result, the heterogeneous structure is produced. The metallized wiring layer is formed, and the firing shrinkage may vary depending on the location. The grain size of the added nitride is preferably smaller than that of the refractory metal.
【００１８】次に、本発明のメタライズ組成物を用いた
配線基板を図面に基づき具体的に説明する。Next, a wiring board using the metallized composition of the present invention will be specifically described with reference to the drawings.
【００１９】図１は本発明の配線基板を半導体素子がフ
リップチップ接続法で収容搭載される半導体素子収納用
パッケージに適用した場合の一実施例を示す斜視図であ
り、図２は図１の半導体素子収納用パッケージに半導体
素子を搭載した状態を示す要部断面図である。FIG. 1 is a perspective view showing an embodiment in which the wiring board of the present invention is applied to a semiconductor element housing package in which semiconductor elements are housed and mounted by a flip chip connection method, and FIG. It is a principal part sectional view which shows the state which mounted the semiconductor element in the package for semiconductor element accommodation.
【００２０】図１及び図２において、１は高融点金属を
主成分とするメタライズ配線層３を絶縁基体２中に一体
的に形成した配線基板であり、各層のメタライズ配線層
３は絶縁基体２を貫通して設けたスルーホール導体４で
互いに接続されている。In FIGS. 1 and 2, reference numeral 1 is a wiring board in which a metallized wiring layer 3 containing a refractory metal as a main component is integrally formed in an insulating substrate 2, and each layer of metallized wiring layer 3 is an insulating substrate 2. Are connected to each other by through-hole conductors 4 penetrating through.
【００２１】また、図２に示す半導体素子を搭載した状
態の半導体素子収納用パッケージは半導体素子５の表面
電極を絶縁基体２の上面中央部にスルーホール導体４で
引き出された図１に示す配線用電極６にハンダバンプ７
で直接接続されており、そこから各層のメタライズ配線
層３を接続するスルーホール導体４を介して下面に導出
されている。Further, in the semiconductor element accommodating package in which the semiconductor element shown in FIG. 2 is mounted, the wiring shown in FIG. 1 in which the surface electrode of the semiconductor element 5 is drawn out to the central portion of the upper surface of the insulating substrate 2 by the through-hole conductor 4. Solder bump 7 on electrode 6
And is led to the lower surface via the through-hole conductor 4 connecting the metallized wiring layer 3 of each layer.
【００２２】かくして絶縁基体２の下面に導出された部
位には、外部電気回路と直接接続する外部リード端子８
が電気的に接続されて、外部リード端子８に半導体素子
５の各電極が電気的に導通するようになっており、最終
的に前記半導体素子５の上部には、封止材を介して金属
やセラミックス等から成る蓋体（不図示）を接合し、半
導体素子５を絶縁基体２の上面中央部に気密に搭載する
こととなる。Thus, the external lead terminal 8 directly connected to the external electric circuit is provided at the portion led out to the lower surface of the insulating substrate 2.
Are electrically connected to each other so that the electrodes of the semiconductor element 5 are electrically connected to the external lead terminals 8. Finally, a metal is provided on the upper portion of the semiconductor element 5 via a sealing material. A lid (not shown) made of, for example, ceramics or the like is joined, and the semiconductor element 5 is hermetically mounted on the central portion of the upper surface of the insulating base 2.
【００２３】[0023]
【実施例】次に、本発明のメタライズ組成物とそれを用
いた配線基板を評価するに際し、先ず、出発原料として
粒径１〜３μｍのＷ、Ｍｏ粉末と、前記粒径より小さい
粒径のＴｉ、Ｖ、Ｎｂ、Ｔａの窒化物粉末を表１に示す
割合にそれぞれ秤量し、これら原料粉末に有機溶剤と溶
媒を添加して混練機で１０時間混練してペースト状のメ
タライズ用試料を作製した。EXAMPLES Next, in evaluating the metallized composition of the present invention and a wiring board using the same, first, as a starting material, W and Mo powders having a particle size of 1 to 3 μm and a particle size smaller than the above particle size were used. Nitride powders of Ti, V, Nb, and Ta were weighed in the proportions shown in Table 1, and an organic solvent and a solvent were added to these raw material powders and kneaded with a kneader for 10 hours to prepare a paste-like sample for metallization. did.
【００２４】一方、絶縁基体用のアルミナ質成形体とし
て、Ａｌ2 Ｏ3 が９２重量％に対して、ＳｉＯ2 、Ｍｇ
Ｏ、ＣａＯ等の焼結助剤を８重量％添加混合した原料粉
末に、周知の有機バインダー、可塑剤、溶剤を添加して
泥漿を調製し、該泥漿を周知のドクターブレード法やカ
レンダーロール法等のテープ成形技術により、厚さ約３
００μｍのセラミックグリーンシートに成形した。On the other hand, as an alumina-based compact for an insulating substrate, Al 2 O 3 is contained in an amount of 92% by weight, and SiO 2 and Mg
A well-known organic binder, a plasticizer, and a solvent are added to a raw material powder obtained by adding and mixing 8% by weight of a sintering aid such as O or CaO to prepare a sludge, and the sludge is well-known by a doctor blade method or a calendar roll method. With tape forming technology such as
It was molded into a ceramic green sheet of 00 μm.
【００２５】かくして得られたペースト状のメタライズ
用試料を、前記セラミックグリーンシートの一方の外表
面全面に、あるいは所定の配線パターン状にスクリーン
印刷法により印刷し、これらを複数枚積層圧着した後、
該積層体を縦７０ｍｍ、横７０ｍｍの正方形に切断し、
これを窒素と水素ガスから成る還元雰囲気中、１５３０
〜１５６０℃の温度範囲で焼成し、アルミナ質焼結体
（９９重量％以上のアルミナ含有量を除く）から成る絶
縁基体表面とその内部に厚さ約２０μｍのメタライズ配
線層を形成した評価用の配線基板試料を作製した。The paste-like sample for metallization thus obtained is printed on the entire one outer surface of the ceramic green sheet or in a predetermined wiring pattern by a screen printing method, and a plurality of these are laminated and pressure-bonded.
The laminate is cut into a square having a length of 70 mm and a width of 70 mm,
1530 in a reducing atmosphere of nitrogen and hydrogen gas
Alumina-based sintered body that is fired in a temperature range of 1560 ° C
A wiring board sample for evaluation was prepared in which a metallized wiring layer having a thickness of about 20 μm was formed on the surface of an insulating substrate made of (excluding an alumina content of 99% by weight or more) and inside thereof.
【００２６】尚、メタライズ組成物中に前記窒化物を全
く含有させない試料を用いて前記同様にして作製した配
線基板試料を比較例とした。A wiring board sample prepared in the same manner as above using a sample in which the nitride was not contained in the metallized composition was used as a comparative example.
【００２７】先ず、前記評価用の配線基板試料を用い
て、該配線基板試料表面の中央部、２０ｍｍ角の部分の
平坦度をダイヤモンド針を装着した接触型表面粗さ計で
対角線方向に反り形状を計測し、単位長さ当たりの反り
（μｍ／ｍｍ）を算出してその最大値を平坦度として評
価した。First, using the above wiring board sample for evaluation, the flatness of the central portion of the surface of the wiring board sample, 20 mm square, was curved in a diagonal direction with a contact type surface roughness meter equipped with diamond needles. Was measured, the warp per unit length (μm / mm) was calculated, and the maximum value was evaluated as the flatness.
【００２８】また、前記配線基板試料の外表面前面に形
成したメタライズ配線層表面にニッケル（Ｎｉ）を被覆
し、該Ｎｉ被覆層上に鉄−ニッケル系のリードピンを銀
ロウにて接合した後、該リードピンを１０ｍｍ／ｍｉｎ
の引っ張り速度で引っ張り、該リードピンが剥離した時
の荷重をメタライズ強度として評価した。Further, after nickel (Ni) is coated on the surface of the metallized wiring layer formed on the front surface of the outer surface of the wiring board sample, an iron-nickel lead pin is bonded onto the Ni coating layer with silver solder, 10 mm / min for the lead pin
The metallization strength was evaluated as the load when the lead pin was peeled off at the pulling speed of.
【００２９】[0029]
【表１】 [Table 1]
【００３０】表から明らかなように、メタライズ組成物
中に窒化物を全く含有させていない比較例である試料番
号１、１７、２３は、いずれも平坦度が１．０５μｍ／
ｍｍ以上と大であり、窒化物の含有量が０．１重量％未
満の試料番号２、７、１２、１８、２７、３２、あるい
は同含有量が０．５重量％を越える試料番号６、１１、
１６、２２、３１、３６では平坦度が１．０４μｍ／ｍ
ｍ以上を示しており、本願の目的を達成し得ない。As is apparent from the table, the sample Nos. 1, 17, and 23, which are comparative examples in which the metallized composition does not contain any nitride, have a flatness of 1.05 μm /
mm or more and sample numbers 2, 7, 12, 18, 27, 32 having a nitride content of less than 0.1% by weight, or sample number 6 having a content of more than 0.5% by weight, 11,
16, 22, 31, 36 have a flatness of 1.04 μm / m
Since it is more than m, the object of the present application cannot be achieved.
【００３１】それに対して、本願発明に係る試料はいず
れも平坦度が１．０３μｍ／ｍｍ以下と極めて優れてい
ることが分かる。On the other hand, it can be seen that all the samples according to the present invention have an excellent flatness of 1.03 μm / mm or less.
【００３２】[0032]
【発明の効果】本発明のメタライズ組成物及びそれを用
いた配線基板によれば、Ｔｉ、Ｖ、Ｎｂ、Ｔａの各窒化
物のいずれか一種を０．１〜０．５重量％含有し、残部
がＷ、Ｍｏの一種以上から成るメタライズ組成物であっ
て、配線基板として前記メタライズ組成物をＡｌ2Ｏ3を
含有する（９９重量％以上のアルミナ含有量を除く）絶
縁基体の表面もしくはその内部に配線層として印刷形成
し、同時焼成してメタライズ配線層を形成したことか
ら、焼成治具や複数の焼成行程を必要とせず、絶縁基体
とメタライズ配線層との同時焼成が可能で、低い製造コ
ストで配線基板の反りやうねり等の変形を効果的に防止
でき、平坦度の良好な配線基板を得ることができる。According to the metallized composition of the present invention and the wiring board using the same , nitriding of each of Ti, V, Nb and Ta is performed.
0.1-0.5% by weight of any one of the substances, the balance
Is a metallized composition comprising one or more of W and Mo, and the surface or the inside of an insulating substrate containing Al 2 O 3 (excluding an alumina content of 99% by weight or more) as a wiring substrate. Since a metallized wiring layer was formed by printing as a wiring layer on the above and simultaneously fired to form a metallized wiring layer, it is possible to fire the insulating substrate and the metallized wiring layer at the same time without requiring a firing jig or a plurality of firing steps. It is possible to effectively prevent deformation of the wiring board such as warpage and undulation at a cost, and to obtain a wiring board having good flatness.
【図１】本発明のメタライズ組成物を用いた配線基板
を、半導体素子がフリップチップ接続法で収容搭載され
る半導体素子収納用パッケージに適用した場合の一実施
例を示す斜視図である。FIG. 1 is a perspective view showing an example in which a wiring board using the metallized composition of the present invention is applied to a semiconductor element housing package in which a semiconductor element is housed and mounted by a flip chip connection method.
【図２】図１の半導体素子収納用パッケージに半導体素
子を搭載した状態を示す要部断面図である。FIG. 2 is a cross-sectional view of essential parts showing a state in which a semiconductor element is mounted on the semiconductor element storage package of FIG.
１ 配線基板 ２ 絶縁基体 ３ メタライズ配線層 1 wiring board 2 Insulating substrate 3 Metallized wiring layer
Claims (2)
量％以上のアルミナ含有量を除く）絶縁基体にタングス
テン（Ｗ）またはモリブデン（Ｍｏ）の少なくとも一種
を主成分とするメタライズ配線層を形成するためのメタ
ライズ組成物であって、チタン（Ｔｉ）、バナジウム
（Ｖ）、ニオブ（Ｎｂ）、タンタル（Ｔａ）の各窒化物
のいずれか一種を０．１〜０．５重量％含有し、残部が
タングステンまたはモリブデンの少なくとも一種からな
ることを特徴とするメタライズ組成物。1. A metallized wiring layer containing, as a main component, at least one of tungsten (W) and molybdenum (Mo) on an insulating substrate containing alumina (Al 2 O 3 ) (excluding an alumina content of 99% by weight or more). A metallization composition for forming a metal, containing 0.1 to 0.5% by weight of any one of titanium (Ti), vanadium (V), niobium (Nb), and tantalum (Ta) nitrides. A metallized composition, the balance of which is at least one of tungsten and molybdenum.
量％以上のアルミナ含有量を除く）絶縁基体に、チタン
（Ｔｉ）、バナジウム（Ｖ）、ニオブ（Ｎｂ）、タンタ
ル（Ｔａ）の各窒化物のいずれか一種を０．１〜０．５
重量％含有し、残部がタングステン（Ｗ）またはモリブ
デン（Ｍｏ）の少なくとも一種から成るメタライズ配線
層を有するとともに、平坦度が１．０３μｍ／ｍｍ以下
であることを特徴とする配線基板。2. An insulating substrate containing alumina (Al 2 O 3 (excluding an alumina content of 99% by weight or more)), and titanium.
(Ti), vanadium (V), niobium (Nb), tantalum
0.1 to 0.5 of any one of the respective nitrides of Ta.
% By weight, balance tungsten (W) or molybdenum
A wiring board having a metallized wiring layer made of at least one of dens (Mo) and having a flatness of 1.03 μm / mm or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06793496A JP3450119B2 (en) | 1996-03-25 | 1996-03-25 | Metallized composition and wiring board using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06793496A JP3450119B2 (en) | 1996-03-25 | 1996-03-25 | Metallized composition and wiring board using the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09255457A JPH09255457A (en) | 1997-09-30 |
| JP3450119B2 true JP3450119B2 (en) | 2003-09-22 |
Family
ID=13359262
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP06793496A Expired - Fee Related JP3450119B2 (en) | 1996-03-25 | 1996-03-25 | Metallized composition and wiring board using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3450119B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100613256B1 (en) * | 2001-12-22 | 2006-09-25 | 재단법인 포항산업과학연구원 | Composition of metallizing paste for alumina and metallizing method |
| JP2006093394A (en) * | 2004-09-24 | 2006-04-06 | Kyocera Corp | Wiring board |
-
1996
- 1996-03-25 JP JP06793496A patent/JP3450119B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09255457A (en) | 1997-09-30 |
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