JPS59208722A - 半導体集積回路装置用合せマ−ク - Google Patents

半導体集積回路装置用合せマ−ク

Info

Publication number
JPS59208722A
JPS59208722A JP58082507A JP8250783A JPS59208722A JP S59208722 A JPS59208722 A JP S59208722A JP 58082507 A JP58082507 A JP 58082507A JP 8250783 A JP8250783 A JP 8250783A JP S59208722 A JPS59208722 A JP S59208722A
Authority
JP
Japan
Prior art keywords
single crystal
island
integrated circuit
alignment mark
alignment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58082507A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6347331B2 (enrdf_load_stackoverflow
Inventor
Hisashi Mizuide
水出 久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP58082507A priority Critical patent/JPS59208722A/ja
Publication of JPS59208722A publication Critical patent/JPS59208722A/ja
Publication of JPS6347331B2 publication Critical patent/JPS6347331B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Element Separation (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP58082507A 1983-05-13 1983-05-13 半導体集積回路装置用合せマ−ク Granted JPS59208722A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58082507A JPS59208722A (ja) 1983-05-13 1983-05-13 半導体集積回路装置用合せマ−ク

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58082507A JPS59208722A (ja) 1983-05-13 1983-05-13 半導体集積回路装置用合せマ−ク

Publications (2)

Publication Number Publication Date
JPS59208722A true JPS59208722A (ja) 1984-11-27
JPS6347331B2 JPS6347331B2 (enrdf_load_stackoverflow) 1988-09-21

Family

ID=13776417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58082507A Granted JPS59208722A (ja) 1983-05-13 1983-05-13 半導体集積回路装置用合せマ−ク

Country Status (1)

Country Link
JP (1) JPS59208722A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6077421A (ja) * 1983-10-05 1985-05-02 Fujitsu Ltd 位置合わせ方法
JPS60160122A (ja) * 1984-01-30 1985-08-21 Rohm Co Ltd サーマルプリントヘッドの製造方法
JPH025508A (ja) * 1988-06-24 1990-01-10 Sony Corp 半導体基板

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50153862U (enrdf_load_stackoverflow) * 1974-06-07 1975-12-20

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50153862U (enrdf_load_stackoverflow) * 1974-06-07 1975-12-20

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6077421A (ja) * 1983-10-05 1985-05-02 Fujitsu Ltd 位置合わせ方法
JPS60160122A (ja) * 1984-01-30 1985-08-21 Rohm Co Ltd サーマルプリントヘッドの製造方法
JPH025508A (ja) * 1988-06-24 1990-01-10 Sony Corp 半導体基板

Also Published As

Publication number Publication date
JPS6347331B2 (enrdf_load_stackoverflow) 1988-09-21

Similar Documents

Publication Publication Date Title
US20120302040A1 (en) Method of fabrication of a three-dimensional integrated circuit device using a wafer scale membrane
CN109216169B (zh) 半导体晶片背面图案与正面图案精确对准的方法
JPH0329310A (ja) 半導体ウェハ
JPS59208722A (ja) 半導体集積回路装置用合せマ−ク
KR970007397B1 (ko) 실리콘웨이퍼
JP2006339481A (ja) 接合基板の切断方法およびチップ
US20240090333A1 (en) Method for manufacturing piezoelectric transducer
CN112838072A (zh) 用于背面光刻工艺的对准方法
JP2838273B2 (ja) 接合ウエーハの製造方法
JPH07142572A (ja) 半導体装置の製造方法
JP3176155B2 (ja) 誘電体分離ウェーハのマスク合わせパターン
JPH04113619A (ja) ウェーハおよびその製造方法
JPS60167426A (ja) 半導体結晶ウエハ−
JPH05335197A (ja) 半導体結晶基板の位置合わせ方法と合わせマーク形状
JPS616824A (ja) 半導体基板目合せ法
JPH04230052A (ja) 半導体基板及びその製造方法
JPH05166772A (ja) 誘電体分離ウェハの製造方法
JPH04307735A (ja) 半導体装置の製造方法
TW563237B (en) Method of removing mask alignment mark material
JPH03243844A (ja) Tem観察用試料の作製方法
JPS60254728A (ja) 半導体装置製造用フオトマスク
JPS59165421A (ja) 半導体装置の位置合わせマ−ク
JPS6177339A (ja) 誘電体分離基板の製造方法
JPH04199619A (ja) 半導体装置用ウエハの製造方法
JPS62128138A (ja) 半導体装置