JPS59194198U - digital signal storage - Google Patents
digital signal storageInfo
- Publication number
- JPS59194198U JPS59194198U JP8775183U JP8775183U JPS59194198U JP S59194198 U JPS59194198 U JP S59194198U JP 8775183 U JP8775183 U JP 8775183U JP 8775183 U JP8775183 U JP 8775183U JP S59194198 U JPS59194198 U JP S59194198U
- Authority
- JP
- Japan
- Prior art keywords
- digital signal
- signals
- signal storage
- write
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案装置の一実施例のブロック系統図、第２
図Ａ−Ｅは本考案装置の動作説明用信号波形図、第３図
はデジタルビデオ信号の画素情報を示す図である。
１〜３・・・ダイナミックＲＡＭ、４・・・水晶発振器
、５・・・分周回路、６・・・デジタルビデオ信号源、
７・・・カウンタ。Figure 1 is a block system diagram of one embodiment of the device of the present invention;
AE is a signal waveform diagram for explaining the operation of the device of the present invention, and FIG. 3 is a diagram showing pixel information of a digital video signal. 1 to 3... Dynamic RAM, 4... Crystal oscillator, 5... Frequency divider circuit, 6... Digital video signal source,
7...Counter.
Claims (1)
メモリに書込むデジタル信号記憶装置において、該サン
プリング信号を分周し、全て該サンプリング信号の周波
数よりも低い同じ周波数で、夫々書込みタイミングが異
なりしかも全体としての書込め周期が一定の複数の書込
み信号を取出す回路と、該複数の書込み信号により該デ
ジタル信号を時分割的に一定の周期で順次書込まれる複
数のメモリとよりなるデジタル信号記憶装置。In a digital signal storage device that writes a digital signal into a memory using a sampling signal of a predetermined frequency, the sampling signal is frequency-divided, and all the signals are written at the same frequency lower than the frequency of the sampling signal, but each write timing is different, and the overall A digital signal storage device comprising: a circuit for extracting a plurality of write signals having a constant write cycle; and a plurality of memories into which the digital signals are sequentially written in a time-sharing manner at a constant cycle by the plurality of write signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8775183U JPS59194198U (en) | 1983-06-08 | 1983-06-08 | digital signal storage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8775183U JPS59194198U (en) | 1983-06-08 | 1983-06-08 | digital signal storage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59194198U true JPS59194198U (en) | 1984-12-24 |
| JPS634318Y2 JPS634318Y2 (en) | 1988-02-03 |
Family
ID=30217667
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8775183U Granted JPS59194198U (en) | 1983-06-08 | 1983-06-08 | digital signal storage |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59194198U (en) |
-
1983
- 1983-06-08 JP JP8775183U patent/JPS59194198U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS634318Y2 (en) | 1988-02-03 |
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