JPS5918671A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To contrive to largely improve the performance by determining the channel length of a FET in self-alignment by a method wherein two bit memory cells are arranged in point symmetry on a semiconductor substrate and set as a pair, and the occupation area of a MOS capacitor is increased by combining the structures of multi layer electrode wiring. CONSTITUTION:A field oxide film 2 is provided on the P type Si substrate 1, and the capacitor electrode 4 in common to all the bits of a P doped poly Si is formed via gate oxide films 3. The film 3 is removed by etching with the electrode 4 as the mask, thus a gate oxide film 5, poly Si gate electrodes 61, 62... are formed newly, the electrodes 61, 62... are changed low resistant by phosphorus diffusion, and then an N<+> source and drain are formed in self-alignment. Covered with a CVD oxide film 9, bit lines 101... which are connected to the drain are formed, word lines 121, 122... which are connected to the gate electrodes 61... are provided via an oxide film 11 and covered with a protection film, and accordingly the device is completed. Since a pair of cells by two pieces is set in lay-out with point symmetric pattern with a gate joint as the center, and the contact point between the bit and word lines is separated from a channel and then decided as the center of symmetry, the reliability is high without the short-circuit between the diffused layer and the contact point.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device in which a 1-bit memory cell is configured by one MOS transistor and one MOS capacitor.

[Technical background of the invention and its problems 3: Dynamic RA in which a 1-bit memory cell is configured by a transistor (one MOS) and one MOS capacitor
In the case of M, the stored data is stored in the MOS capacitor in the form of charge. Therefore, the amount of charge stored in the MOS capacitor of the memory cell greatly influences the performance of the dynamic RAM. The charge ff1Q of the MOS capacitor is M
Assuming that the capacitance of the OS capacitor is 01 and the write voltage is (■), Q=CV, so as the write voltage V is lowered, Q becomes smaller. The only way to compensate for this is to increase the capacitance C.

Possible means for increasing the capacitance of a MOS capacitor include increasing the area, decreasing the thickness of the insulating film, and selecting an insulating film with a high dielectric constant. However, M.O.
Increasing the area of the S capacitor leads to an increase in the chip size of the dynamic RAM under the same design rule, resulting in a decrease in product yield and an increase in cost. Furthermore, making the insulating film extremely thin causes reliability problems such as a drop in breakdown voltage. As an insulating film with a high dielectric constant,
5isN4, which has a dielectric constant nearly twice that of 5i02, has been considered as a substitute for 5i02, but it is not practical due to the complicated manufacturing process and large leakage current. Regarding Tsukuda's insulating film, no suitable material compatible with the current Bi process has been found.

For the above reasons, it will be essential to make efforts to increase the 17i] product of MOS capacitors within a limited memory cell area. In this sense, the two-layer polysilicon process is a structure in which the gate of the MOS transistor is formed with a second-layer polysilicon film, which is partially overlapped with the canopy electrode made of the first-layer polysilicon film, so it is This is advantageous in that the area occupied by the capacitor within the cell area can be increased. However, in this case, the effective channel length of the MOS transistor is determined by the alignment accuracy of the first layer polysilicon and the second layer polysilicon. For this reason, there is a problem in that a sufficient margin for alignment accuracy must be provided, and since the effective channel length of the Mos+ transistor varies, a sufficient design margin must be provided for sense sensitivity.

[Purpose of the invention]

The present invention reduces the occupancy of MOS canocciters in memory cells compared to conventional methods by combining an improved memory cell layout and a multilayer electrode wiring structure.

It is an object of the present invention to provide a semiconductor memory device which has an increased area and which can significantly improve performance by determining the expired channel length of a MOS transistor by zero matching.

[Summary of the invention]

In the present invention, first, 2-bit memory cells are arranged point-symmetrically on a semiconductor substrate to form a large number of memory cell arrays. The layout of one set of memory cells is schematically shown in FIG. 1 using an equivalent circuit. The gates of the two MO8I transistors Ql and Q2 are commonly connected, and around this common connection point, a memory cell consisting of a MOS transistor Q and a MOS capacitor C3, a MOS transistor Q, and a MOS capacitor C1 are connected.
Memory cells consisting of are arranged point-symmetrically on the pattern. The drains of the MOS transistors Ql and Q2 are connected to bit lines B (B1, B,) running parallel to the Y direction, and the gates are connected to a word line W orthogonal to the bit lines.

FIG. 2 shows an arrangement of multiple sets of memory cells that is closer to the actual layout. In FIG. 2, the area surrounded by broken lines is the element formation area. In the present invention, M.O.
One electrode of the S capacitor, ie, the electrode on the ground end side in FIG. 2, is continuously provided on all bits by the first layer electrode film.

The gate voltage of the MOS transistors is continuously arranged for two MOS transistors in each set by the second layer electrode film. At this time, as will be described in detail later, the effective channel length is determined in a self-aligned manner by ensuring that the gate electrode does not overlap the M08 capacitor electrode in the channel length direction. Then, the third layer electrode film is used to arrange a bit line B (Bs, B2...) that contacts the drain of the MOS transistor and runs in the Y direction, and the fourth layer electrode film is used to arrange the point-symmetrical arrangement of the memory cells. A word line W (W, .

Wt,...) are arranged.

As is clear from the figure, in the memory cell arrangement, not only one set of memory cells is arranged point-symmetrically with respect to its gate electrode common connection portion, but also adjacent sets are point-symmetrically arranged.

〔Effect of the invention〕

According to the present invention, unlike the conventional two-layer polysilicon process, a set of memory cells is arranged symmetrically with respect to the common connection part of the gate electrode, and the bit line is formed in the first layer instead of the diffusion layer. By using a layered electrode film, the area of the M08 capacitor within one memory cell can be made sufficiently large. In addition, by using a diffusion layer as a bit line, the stray capacitance of the bit line is reduced.For these reasons, the performance of MOS dynamic RAM is improved, and the effective channel length of the MOS transistor is self-aligned. This reduces cell-to-cell variation in sense sensitivity and improves product yield.Furthermore, the word line is formed from the first layer electrode film, and the contact position is set at the point of one set of memory cells. By locating the symmetrical center position, that is, the position where the second layer electrode film is continuously arranged, even if the contact hole position is shifted due to mask misalignment, the electrode film will not penetrate into the element forming area. Improved reliability.

[Embodiments of the invention]

The present invention will be explained in detail below. Figure 3 (al ~ (el is a plan view showing the manufacturing process of one embodiment), Figure 4 (al ~ (d
) are respectively shown in Fig. 3 (at~(dl)).
-A' cross-sectional view;
'It is a sectional view. To explain according to the manufacturing process, first
A type silicon substrate I is prepared, and a field oxide film 2 is formed using, for example, a well-known selective oxidation method using a Si, N, or film mask (FIGS. 3(a) and 4(a)). next,
A first gate oxide film 3 is formed by thermal oxidation, a first layer polysilicon film (first layer electrode film) is deposited, phosphorus is diffused into this film at a high concentration, and patterning is performed to cover all bits. MOS capacitor' electrodes 4 are continuously formed (FIGS. 3(b) and 4(b)). Next, the first gate oxide film 3 is removed by etching using the capacitor electrode 4 as a mask, a second gate a film 5 is formed again by thermal oxidation, and a third layer polysilicon film a (ILE 21@electrode film) is deposited. By patterning this, MO
8I - transistor gate) [pole 6 (61 + 62 r
), and conducts phosphorus diffusion to lower the resistance of the gate electrode 6 and the gate electrode 6. At the same time, a self-aligned n+ drain 7 and source 8 are formed on the gate electrode 6 (the third
Figure (C), Figure 4 (C)). Then, the entire surface is covered with a CVPM film 9, contact poles are made in this, a third layer polycrystalline silicon film (third layer electrode film) is deposited, phosphorus is diffused into this film, and then patterned to form a MOS). The bit line that contacts the drain 7 of the transistor
+ ”t v...) (Fig. 3(d),
Figure 4(d)). After that, the entire surface is covered with the CVD oxide film 11 again.
Then, a contact hole is made in this and the P and L films (
A word line 12 that contacts the gate electrode 6 of the MOS transistor is formed by depositing and patterning a first layer electrode film).
(12I, 12□,...) (Figure 5)
. Finally, a protective film is applied to complete the process.

The effects obtained by this embodiment are as follows.

(1) In the conventional two-layer polysilicon process, the drain expansion 6r>+ was used as it is as a bit line, so 1
There is a limit to the increase in the area of the F/10S capacitor within the memory cell. Furthermore, soft errors caused by alpha rays also pose a problem in that sense failure occurs when the bit line is in a floating state. In this actual Fj example, by using the third layer polysilicon film as the bit line, the area occupied by the ^408 capacitor can be increased, and bit stray capacitance can be reduced, resulting in high performance with good sense sensitivity. Dynamic RAM is obtained.

(2) According to this embodiment, since the effective channel length of the MO3I-transistor is determined by self-alignment, it is possible to reduce cell-by-cell variations in sense sensitivity due to variations in the effective channel length, and therefore improve product yield. Improvements will be made.

(3) In this embodiment, the memory cells are not arranged in a line-symmetrical pattern, which is commonly used in the past, but in a point-symmetrical pattern centered on the common connection of the four gate poles of the transistor (MOS) in which two memory cells form a set. layout and MO
The contact position between the gate electrode of the S transistor and the word line is set at the symmetrical center of the gate electrode common connection part apart from the channel region. For this reason,
Even if the contact hole position is slightly shifted due to mask misalignment or the like, there is no risk of short-circuiting of the contact electrode in the diffusion layer region ζ, thus improving the reliability of the product.

In Embodiment 6, a polysilicon film and an Al film were used as the third layer electrode film that becomes the bit line and the M4 layer electrode film that becomes the word line, respectively. yi (A high melting point metal such as No. 1 or its silicide film may also be used.

[Brief explanation of the drawing]

FIG. 1 is a diagram schematically showing the arrangement of a set of memo 1" cells in the present invention using an equivalent circuit, and FIG. Figures 3(a) to 3(e) are plan views showing the manufacturing process of the memory cell array according to an embodiment of the present invention, and FIGS. ) ~(d)
Its A-A' sectional view corresponding to FIG. 5 (and FIG. 3 (
It is the B-Bl sectional view corresponding to el. Ql, Qt...MOS transistor, CI+C2・
・・MOS capacitor, B (Bl, B2 ・・)・・
・Bit line, W (Wl, B2,...)... "Hood line, 1... P-type silicon substrate, 2... Field acid film, 4... MOS capacitor electrode (jf,
1 layer po 13 shi 1) feces film), 6 (61+6t y...
・)...Gate electrode (second layer polysilicon film), 7
...Drain, 8...Source, 10 (10,,1
0,,...)... Binod line (third layer polysilicon film), 12C121-122, -')"'word @ (
Al film). Applicant's agent Patent attorney Takehiko Suzue Figure 3 (a) Figure 3 (b) Figure 3v! I (C) Figure 3 (d) Figure 3 (e) (d) Figure 4

Claims (2)

[Claims] (1) In a semiconductor memory device in which a 1-bit memory cell is configured by one MOS transistor and one MOS capacitor, 2-bit memory cells are arranged point-symmetrically on a 3° semiconductor substrate to form a large number of sets. One electrode of the MOS capacitor is arranged continuously for all bits by means of the first layer electrode film.
The gate electrode of the MO8I-transistor of one set of memory cells is arranged so as to be continuous on the field region by the second layer electrode film and so as not to overlap the MOS capacitor electrode in the channel length direction, and the gate electrode of the MO8I transistor of one set of memory cells is arranged so as to be continuous on the field region by the second layer electrode film and so as not to overlap the MOS capacitor electrode in the channel length direction. 1 set of notes by
□A bit line ′ running in parallel is arranged in contact with the drain of each MO8l-transistor of the recell, and is contacted with each set of gate electrodes at the center position of the point symmetry on the field region. A semiconductor memory device characterized in that a word line made of a fourth layer electrode film running in orthogonal directions is provided. (2) The first to third layer electrode films are polysilicon films, and the fourth layer electrode film is an AIJ film.
The semiconductor storage device described in 1.