JPS59182572A - 薄膜トランジスタとその製造方法 - Google Patents

薄膜トランジスタとその製造方法

Info

Publication number
JPS59182572A
JPS59182572A JP58057552A JP5755283A JPS59182572A JP S59182572 A JPS59182572 A JP S59182572A JP 58057552 A JP58057552 A JP 58057552A JP 5755283 A JP5755283 A JP 5755283A JP S59182572 A JPS59182572 A JP S59182572A
Authority
JP
Japan
Prior art keywords
gate
tantalum
aluminum
oxide
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58057552A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0563947B2 (https=
Inventor
Koji Nomura
幸治 野村
Kuni Ogawa
小川　久仁
Atsushi Abe
阿部　惇
Koji Nitta
新田　恒治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58057552A priority Critical patent/JPS59182572A/ja
Priority to EP84901397A priority patent/EP0139764B1/en
Priority to US06/678,547 priority patent/US4602192A/en
Priority to PCT/JP1984/000145 priority patent/WO1984003992A1/ja
Priority to DE8484901397T priority patent/DE3480243D1/de
Publication of JPS59182572A publication Critical patent/JPS59182572A/ja
Publication of JPH0563947B2 publication Critical patent/JPH0563947B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]

Landscapes

  • Thin Film Transistor (AREA)
JP58057552A 1983-03-31 1983-03-31 薄膜トランジスタとその製造方法 Granted JPS59182572A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP58057552A JPS59182572A (ja) 1983-03-31 1983-03-31 薄膜トランジスタとその製造方法
EP84901397A EP0139764B1 (en) 1983-03-31 1984-03-29 Method of manufacturing thin-film integrated devices
US06/678,547 US4602192A (en) 1983-03-31 1984-03-29 Thin film integrated device
PCT/JP1984/000145 WO1984003992A1 (en) 1983-03-31 1984-03-29 Thin-film integrated device
DE8484901397T DE3480243D1 (en) 1983-03-31 1984-03-29 Method of manufacturing thin-film integrated devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58057552A JPS59182572A (ja) 1983-03-31 1983-03-31 薄膜トランジスタとその製造方法

Publications (2)

Publication Number Publication Date
JPS59182572A true JPS59182572A (ja) 1984-10-17
JPH0563947B2 JPH0563947B2 (https=) 1993-09-13

Family

ID=13058963

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58057552A Granted JPS59182572A (ja) 1983-03-31 1983-03-31 薄膜トランジスタとその製造方法

Country Status (1)

Country Link
JP (1) JPS59182572A (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01286432A (ja) * 1988-05-13 1989-11-17 Nippon Telegr & Teleph Corp <Ntt> 絶縁膜の欠陥の検出方法
JPH0234926A (ja) * 1988-07-25 1990-02-05 Matsushita Electric Ind Co Ltd 薄膜トランジスタの製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01286432A (ja) * 1988-05-13 1989-11-17 Nippon Telegr & Teleph Corp <Ntt> 絶縁膜の欠陥の検出方法
JPH0234926A (ja) * 1988-07-25 1990-02-05 Matsushita Electric Ind Co Ltd 薄膜トランジスタの製造方法

Also Published As

Publication number Publication date
JPH0563947B2 (https=) 1993-09-13

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