JPS59178770A - Semiconductor device of high withstand voltage - Google Patents

Abstract

PURPOSE:To obtain the titled device of excellent high frequency characteristic by a method wherein the periphery of an emitter region is surrounded by a high impurity concentration region of the same conductivity type as that of a semiconductor of one conductivity type, and a low impurity concentration region of the reverse conductivity type is provided on the surface of a collector region, when the emitter and collector regions of the reverse conductivity type are provided in the surface layer part of said semiconductor substrate, thus being formed into a lateral transistor. CONSTITUTION:An N<+> type buried layer 2 is diffusion-formed in the surface layer part of the P type Si substrate 1, and an N type layer 4 serving as the base is epitaxially grown over the entire surface including said layer and then formed in an island form by P type isolating diffused regions 3. Then, a P type emitter region 5a positioned at the center by sandwiching the base region composed of the layer 4 and a P type collector region 5b which surrounds said emitter are provided. At this time, the periphery of the P type emitter region 5a is kept surrounded by a P<+> type well region 9, and a thin P<-> type layer 501 having a stretch-out part 502 is provided on the surface of the region 5b. An electrode 8a mounted on the region 5a is extended on an insulation film 7 so as to cover the region 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a pnp transistor that is incorporated into a semiconductor integrated circuit (hereinafter abbreviated as IC), and particularly to a lateral pnp transistor.

[Background technology]

In a high-voltage bipolar IC, in order to increase the breakdown voltage of an npn transistor, the resistivity of an evitaginal layer serving as a collector layer must be increased. Therefore, in lateral transistors formed on the same chip, a depletion layer tends to extend into the base, resulting in a decrease in breakdown voltage due to punch-through.

In order to prevent punch-through of the (lateral pnp) transistor and increase its withstand voltage, pattern countermeasures alone will have to increase the pace width (WB shown in Figure 1), decrease the DC current amplification factor brg, and increase the frequency. The characteristics deteriorated.

In the conventional improved example, as shown in the cross-sectional structure of Fig. 2, a highly concentrated n-type diffusion layer 9 (hereinafter referred to as n-well region) is formed around the emitter diffusion to prevent a drop in breakdown voltage due to punch-through. is.

However, this structure also had the following drawbacks.

(1) The emitter electrode 8a shown in FIGS. 1 and 2 has an overmetal structure extending to the top of the collector diffusion region 5b to improve reliability in order to prevent a drop in breakdown voltage due to charge spillage. Even if punch-through could be suppressed by the n-well 9, electric field concentration occurred in the vicinity of the collector diffusion 5b directly under the emitter electrode 8a due to this over-metal structure, resulting in breakdown, and the withstand voltage could not be made that high.

(2) N-well 9 introduced to suppress punch-through
As a result, the injection efficiency of the emitter was lowered, leading to the (f) lowering of the hFE.In particular, as shown in the plan view of FIG. In this structure, a highly concentrated n-well was required to prevent punch-through, resulting in a further decrease in hrw.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks and to provide a semiconductor integrated circuit in which a high-voltage lateral PNP transistor with good frequency characteristics coexists.

[Summary of the invention]

In order to achieve the above object, the high voltage semiconductor device of the present invention has an emitter region and a collector region of a conductivity type opposite to that of the base body, which are provided apart from each other in the main surface region of a semiconductor base body of a − conductivity type. In a lateral transistor having the above substrate as a base region, a high impurity concentration region of the same conductivity type as the base region is provided around the emitter region, and a low impurity concentration region of the opposite conductivity type to the base region is provided around the surface of the collector region. It is characterized by having a concentration region.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. Third
The figure shows a cross-sectional structure, and the emitter electrode 8a is
It extends over the low impurity p-type layer 501 formed by ion implantation around the surface of the collector diffusion layer 5b. A p-type layer 50 directly below the emitter electrode 8a, which is different from the example in FIG.
In No. 1, the electric field concentration is alleviated by pinch-on, and breakdown is suppressed. Since this p-type layer 501 also works as a collector, the base width of the lateral pnp
However, it is the WB shown in FIG. 3, not the wider Wp. Therefore, a decrease in hFg can be prevented. Emitter electrode 8
Since a has an overmetal structure that extends to the collector, there is no problem in terms of reliability. By adopting this structure, punch-through is suppressed in the n-well 9,
In addition, breakdown on the collector 5b can be prevented, making it possible to improve the breakdown voltage. Furthermore, the base width can be shortened, and high frequency characteristics can also be improved.

Here, the p-type layer 502 in FIG. 3 is the collector diffusion layer 5b.
In order to prevent breakdown on the surface of the collector layer 5b, the same p-type layer as in 501 is extended beyond the collector layer 5b.

FIG. 4 shows another embodiment in which a field plate 802 is formed on the collector layer 5b instead of the p-type layer 50-2 in FIG. 3 to prevent breakdown near the surface of the collector layer 5b. It is something.

FIG. 5 shows a plan view a and its cross-sectional structure in another embodiment. The emitter 5a is characterized by an elongated shape. By elongating the shape of the emitter 5a, the impurity concentration of the n-well 9 to suppress punch-through can be reduced to 1/2 compared to the structure in which the emitter 5a is surrounded by the collector 5b concentrically as shown in FIG. Since it is possible to do the following, it is possible to prevent the emitter injection efficiency from decreasing. At the same time, since the peripheral length of the emitter can be made longer than that of a concentric emitter for the same transistor size, a collector current amplification port can also be designed.

This will be explained in detail below using FIG. 6.

FIG. 6(a) is a plan view of a concentric lateral PNP showing the area between the collector and emitter.

Consider a one-dimensional model of a sector-shaped pnp (pnp) transistor shown by GHIJ between BB'. Here, NA is the impurity concentration of the collector, NDl is the impurity concentration of the epitaxial layer, and NDl is the impurity concentration in the N well. Assuming that when a voltage V is applied between the collector and the base, the depletion layer extends to the n-well, the following formula holds true from the condition of charge balance between the collector and base.

N nz > N Dl t2 rl , l-, r2 tt-ro QNA= t2-δ・qND2tl-r
o-qNAχt1・δ・qND2'1 = ND2 2 Here, the impurity concentration NDI of the epitaxial layer is smaller than the impurity concentration ND2 of the n-well by more than C orders, and it can be seen that the required impurity concentration at the same applied voltage V is from the same figure. Ru. Same figure (
In order to realize the condition C) with an actual pattern, the emitter can be made into an elongated pattern. However, since the relationship at both ends of the elongated emitter is as shown in FIG. 6(b), the base width must be increased in order to maintain the withstand voltage. Fifth
This corresponds to the portion indicated by W in the plan view of the figure.

The collector current of the lateral pnp is the emitter peripheral length L
Since it is proportional to E, in order to obtain a large current, it is sufficient to lengthen LE. Figure 7 shows the patterns of the collector and emitter parts of the lateral PNP. Figure 7 (a) is a concentric pattern with three emitters, and Figure 7 (b) is a diagram with elongated emitters. It is.

Comparing the same transistor size, the emitter peripheral length is as shown in Fig. 7(a) when the number of emitters is 3 or more.
The one in FIG. 7(b) is longer. For example, if we use the values shown in Figure 7, we can see that case (b) is long. The conditions under which an elongated emitter has a longer peripheral length than an emitter with a concentric structure can be determined by calculation. However, W=Wp +X
K and Toshida. Each symbol is divided by the length shown in Figure 7.

When C+ =10 ttmz XE ==20 μm, if Wp is 15 μm or more, it becomes nz3.

That is, in practical terms, the Wp of the lateral pnp is 15 μm or more, so when three circular emitters are arranged horizontally on a thin plate, the elongated emitters can have a longer peripheral length.

As described above with reference to FIGS. 6 and 7, the impurity concentration in the n-well 9 can be lowered by using an elongated emitter rather than a circular emitter, and the emitter injection efficiency can therefore be increased. Furthermore, since the emitter peripheral length also becomes longer, the current can also be increased. n without increasing the base width
Since the withstand voltage is increased in the well, there is less deterioration in frequency characteristics.

FIG. 8 shows another example in which the present invention is applied to IC structures having different epitaxial layer thicknesses. Element isolation is performed at a thin portion of the epitaxial layer. This is an advantageous structure when obtaining a high withstand voltage of 150μ or more.

FIG. 9 is an example of FIG. 8, with the p-type low impurity concentration layer 502 removed. By overmetalizing the emitter 5a with the second layer of At12, electric field concentration at the edge of the collector layer 5b is prevented, and the improvement effect of the present invention is obtained as in the other embodiments.

〔Effect of the invention〕

According to the present invention, it is possible to improve the breakdown voltage without reducing the frequency characteristics of the lateral PNP.

For example, when realizing a 250V ICi, npn
) In order to ensure the breakdown voltage of the transistor, the epitaxial layer has a resistance of 30 Ωα or more, so the base width of the lateral PNP is 50 μm or more on the mask in the conventional structure. Therefore, the gain-bandwidth product fT of the lateral pnp is I M
Hz or less, resulting in poor frequency characteristics. However, by using the sound of the present invention, the base width can be shortened to 20 μm while maintaining the withstand voltage of 250 V, so one gun can have a power rating of 4 to 5 MH.
It has the effect of increasing performance several times as much as Z. Further, according to the present invention, it is possible to provide a structure that does not cause problems such as reliability and breakdown voltage deterioration due to spilled charge.

[Brief explanation of the drawing]

Figures 1 (a) and (b) are a plan view and a cross-sectional view of a conventional lateral PNP, and Figure 2 is a cross-sectional structural diagram showing an improved example of the conventional structure.
3 to 4 are cross-sectional structural diagrams showing an embodiment of the present invention, FIG. 5 is a plan view and a cross-sectional structural diagram showing an embodiment of the present invention,
6 and 7 are diagrams for explaining the present invention in detail, and FIGS. 8 and 9 are cross-sectional structural diagrams showing other embodiments of the present invention. 1...p-type substrate, 2...n-type high impurity concentration buried layer,
3...p-type isolation diffusion layer, 4...n-type epitaxial layer, 5a, 5b・-n-type diffusion layer, 501, 502
-'p-type ion implantation layer, 6...n-type diffusion layer, 7...
Oxide film, 8a, 8b, 8c...aluminum electrode, 9...
・N-well diffusion layer, 10...n-type diffusion layer, 11...
Interlayer insulating film, 12... Second layer aluminum electrode, 41...
・Thick nfi shrimp 1st ward (phantom (Tono A' Y 2nd ward 3 ward 1- straw 4- RO closed otsu shi≧) 7th (2) H-1112ba1NP-fγXef (sword +) C1-110) 41 ト(-2(しし'tCI)＋ノE--113 目茅 9 Old

Claims (1)

[Claims] 1. An emitter region and a collector region of the opposite conductivity type to the base body are provided in the main surface region of an α-type conductive semiconductor base body, and the base body is used as a pace region. A lateral transistor having a high impurity concentration region having the same conductivity type as the base region around the emitter region,
A high breakdown voltage semiconductor device comprising a low impurity concentration region of a conductivity type opposite to that of the base body around the surface of a collector region. 2. In the semiconductor device according to claim 1,
1. A semiconductor device characterized in that an emitter electrode extends through an insulator onto a low impurity concentration region of a conductivity type opposite to that of the base body surrounding the collector. 3. A semiconductor device according to claim 1 or claim 2, wherein the width of the emitter region is approximately equal to the width of the main operating region of the opposing collector region.