JPH11121459A - Semiconductor device and reduction of collector resistance thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can improve its high frequency characteristics and reliability, by suppressing an increase in a collector resistance and thermal runaway caused by an increase in the number of electrodes. SOLUTION: In a bipolar semiconductor integrated circuit as the semiconductor device, a collector region of a second conduction type is formed on a semiconductor substrate of a first conduction type, a base region 7 of the first conduction type is provided in the collector region, and an emitter region 8 of the second conduction type is formed in the base region 7. In this case, the base region 7 is surrounded at its 4 sides by a collector pulling part 5 of the second conduction type having a high concentration and also by a collector electrode 11 electrically connected to the pulling part 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for reducing its collector resistance, and more particularly to a bipolar transistor having a reduced collector resistance.

[0002]

2. Description of the Related Art Referring to FIGS.
A conventional technique described in Japanese Patent Publication No. 36 will be described. Japanese Patent Application Laid-Open No. 7-249636 describes a PNP transistor.

[0003] The same can be clearly said for the NPN transistor. FIG. 6 shows that an N-type epitaxial layer 22 is formed on a P-type silicon semiconductor substrate 1 and then a high-concentration N-type impurity diffusion buried region 23 (N ⁺ B
L). In the element isolation region 24, a deep N ⁺ impurity diffusion region 2 is provided as a base electrode lead region.
5, a P-type collector electrode lead-out region 26 and a P-type emitter electrode lead-out region 27 are formed, and a base electrode (B), a collector electrode (C), and an emitter electrode (E) are attached to each region.

In FIG. 7, a P-type impurity diffusion buried region 40 serving as a collector region in an element isolation region 34 is formed on an N-type impurity diffusion buried region 33 at a distance therefrom.
P-type impurity diffusion region 4 as a collector electrode extraction region
1 is formed in contact with the collector region 40. Then, the collector electrode extraction region 41 and the emitter region 4
3, a collector electrode (C), an emitter electrode (E), and a base electrode (B) made of Al or the like are attached to the base electrode lead region 44, respectively.

[0005] However. In these methods, there is only one collector electrode lead-out region 41, so that the collector resistance could not be sufficiently reduced. Therefore, as one means for solving this problem, Japanese Patent Laid-Open Publication No.
A method disclosed in Japanese Patent Application Laid-Open No. 4 (Kokai) No. 4 has been proposed. This will be described below with reference to FIG.

FIG. 8A is a plan view, and FIG.
FIG. 8A is a sectional view taken along line XX, and FIG. 8C is a sectional view taken along line YY. Also, here, 61 is a base electrode, 62 is an emitter electrode, 63 is a collector electrode, 64 is a surface protective film, 65 is an isolation oxide film, 66 is an emitter region, 67 is a base region, and 68 is a collector region (epitaxial layer). ), 69 is a buried layer, 70 is a high-concentration region of the collector pull-up portion, 71
Is a P-type semiconductor substrate, and 72 is a capacitance reducing insulating film.

By using this method, the collector resistance rsc ″ in the YY direction shown in FIG. 8C can be made much smaller than the collector resistance rsc ′ shown in FIG. In order to further reduce the collector resistance, as shown in FIG.
Are all enclosed.

However, as shown in FIG. 8 or 9, when the number of emitter electrodes is increased, for example, a current imbalance occurs between the central portion and the vicinity of the collector electrodes at both ends, thereby deteriorating high-frequency characteristics and increasing reliability. There was a drawback of lowering. Furthermore, the above-described means still has a drawback that the collector resistance cannot be sufficiently reduced.

[0009]

An object of the present invention is to provide a novel semiconductor device which improves the above-mentioned disadvantages of the prior art, reduces the collector resistance and improves the high-frequency characteristics, and a method of reducing the collector resistance. It is. Another object of the present invention is to provide a semiconductor device and a method of reducing the collector resistance of the semiconductor device, in which the current imbalance in the element is eliminated, thereby eliminating the problem of thermal runaway and improving the reliability. is there.

[0010]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object. That is, as a first aspect of the semiconductor integrated circuit according to the present invention, a collector region of the second conductivity type is arranged on the semiconductor substrate of the first conductivity type, and a base region of the first conductivity type is provided in the collector region, and In a bipolar semiconductor integrated circuit having a second conductivity type emitter region formed in the base region, four sides of the base region are surrounded by a high-concentration second conductivity type collector pull-up portion, and A semiconductor integrated circuit, wherein four sides of the region are surrounded by a collector electrode that is connected to the collector pull-up portion of the second conductivity type. A semiconductor integrated circuit, wherein four sides of a region are surrounded by a base electrode, and as a third aspect, the emitter electrode is formed on one side of the collector electrode, and the other side is formed. Is a semiconductor integrated circuit according to claim of the base electrode is formed on.

In a fourth aspect, a collector region of the second conductivity type is disposed on the semiconductor substrate of the first conductivity type, a base region of the first conductivity type is provided in the collector region, and a base region of the base material is provided in the base region. A semiconductor integrated circuit in which a second conductivity type emitter region is formed, wherein four sides of the base region are surrounded by a high-concentration second conductivity type collector pull-up portion, and four sides of the base region are formed in the same direction. Forming a unit cell which is surrounded by a collector electrode conducting to a collector pull-up portion of the second conductivity type, and an emitter electrode is drawn out on one side of the semiconductor integrated circuit, and a base electrode is drawn out on the other side;
A semiconductor integrated circuit in which the unit cells are arranged so that the emitter electrodes of the unit cells face each other, the respective emitter electrodes are connected, and an emitter electrode is arranged between the unit cells; A fifth aspect is a semiconductor integrated circuit in which, in addition to the above configuration, four sides of the emitter region are surrounded by a base electrode.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to FIG. This example is an example in which four sides of the base region are surrounded by a collector pulling portion. FIG. 1 is a plan view, and FIG.
FIG. 2B is a sectional view taken along the line Y-Y, and FIG. 3 is a plan view when the number of electrodes is increased.

Here, 1 is a silicon semiconductor substrate, 2 is a buried layer, 3 is a collector region (epitaxial layer), 4 is an element isolation region, 5 is a U-shaped connecting the buried layer 2 and a collector electrode. High-concentration collector pull-up portion, 6 a surface protective film formed on the wafer, 7 a base region,
8 is an emitter region formed in the base region 7, 9 is an emitter first electrode formed on the emitter region 8, 10 is a base first electrode formed on the base region 7, and 11 is the same as the collector pulling portion 5. A collector electrode formed in a V-shape and in contact with the collector pull-up portion 5; 12 is an interlayer insulating film formed on the surface protection film 6; 13 is a through-hole contact formed in the interlayer insulating film 12; The hole contact 13 is provided on the first emitter electrode and also on the first base electrode. Reference numeral 14 denotes an emitter second electrode connected to the emitter first electrode via a through-hole contact 13;
A second base electrode connected to the first base electrode via 3;
Reference numeral 16 denotes a collector pad opening formed on the collector electrode.

Referring to FIG. 2, first, a buried layer 2 is formed on a silicon semiconductor substrate 1 and an epitaxial layer 3 is grown. Thereafter, an element isolation region 4 is formed, and a high-concentration collector pull-up portion 5 is formed. Next, a surface protection film 6 is formed on the silicon semiconductor substrate 1, and a base region 7 and an emitter region 8 are formed by a photoresist method, etching, ion implantation, or the like. Then, an emitter first electrode 9 is formed on the emitter region 8, and a base first electrode 10 and a collector electrode 11 are formed on the base region 7.

After the interlayer insulating film 12 is formed, a through-hole contact 13 is formed by a photoresist method and etching. Thereafter, the emitter second electrode 14, the base second electrode 15, and the collector electrode are formed on the interlayer insulating film 12. A pad opening 16 is formed. The emitter second electrode 14
The second base electrode 15 and the second base electrode 15 are formed in a square shape and arranged to face each other with the collector electrode interposed therebetween. or,
A case where the number of electrodes is increased will be described with reference to FIG. Taking the case where the number of emitters is four as an example, the layout is as shown in FIG.

Here, the even number of unit cells formed in FIG. 1 are arranged symmetrically with respect to the second emitter electrode formed in the center, and the through-hole contact portion 13 of the second emitter electrode 14 is formed in the center. The unit cell is arranged so as to be located in the vicinity of the second emitter electrode formed in the above. Therefore, the emitter second electrode 14 has a fish bone shape. The base is pulled out from around the unit cell by the base first electrode 10, the through-hole contact portion 13 and the base second electrode 15, and the collector is drawn to the collector electrode 11
With one layer.

When the number of emitters is six or eight, the number of unit cells is increased in the same manner and the emitter cells are arranged in a bone shape.

[0018]

Next, embodiments of the present invention will be described in detail with reference to the drawings. 1 to 5 show the structure of a semiconductor device according to the present invention and a method of reducing the collector resistance thereof. In the figures, a collector region 3 of a second conductivity type is arranged on a semiconductor substrate 1 of a first conductivity type. In a bipolar semiconductor integrated circuit in which a base region 7 of the first conductivity type is formed in the collector region 3 and an emitter region 8 of the second conductivity type is formed in the base region 7, the four sides of the base region 7 are raised. The semiconductor integrated circuit is surrounded by the collector pull-up portion 5 of the second conductivity type and the base region 7 is surrounded by the collector electrode 11 conducting to the collector pull-up portion 5 of the second conductivity type. Further, a semiconductor integrated circuit in which four sides of the emitter region 8 are surrounded by a base electrode 7 is shown, and the emitter electrode 14 is formed on one side so as to sandwich the collector electrode 11, Square state where the base electrode 15 is formed on the side of the is shown.

In FIG. 3, a collector region 3 of the second conductivity type is disposed on the semiconductor substrate 1 of the first conductivity type, and a base region 7 of the first conductivity type and a base region 7 of the first conductivity type are disposed in the collector region 3. A semiconductor integrated circuit in which a second conductivity type emitter region is formed in a source region, wherein four sides of the base region are surrounded by a high-concentration second conductivity type collector pull-up portion; Four sides of the base region 7 are surrounded by a collector electrode 11 which is electrically connected to the second conductive type collector pulling portion 5,
In addition, a unit cell in which the emitter electrode 14 is drawn out on one side of the semiconductor integrated circuit with the collector electrode 11 interposed therebetween and the base electrode 15 is drawn out on the other side is formed, and the emitter electrodes 14 of this unit cell are mutually connected. A semiconductor integrated circuit in which the unit cells are arranged to face each other and the respective emitter electrodes 14 are connected is shown.

The first embodiment of the present invention will be described with reference to FIGS. 1 to 3. First, the specific resistance is about 20 to 40 Ω ·
N ⁺ buried layer 2 formed by arsenic implantation or antimony diffusion in P-type silicon semiconductor substrate 1 having an N-type impurity concentration of 1 × 10 ^{15 to} 1 × 10 ¹⁶ cm ⁻³ and a thickness of 1.0 to 2. A 5 μm epitaxial layer 3 is grown. next,
An element isolation region 4 is formed on the silicon semiconductor substrate 1 by a selective oxidation method generally called a LOCOS method, and a high-concentration collector pull-up portion 5 is formed by a photoresist method and ion implantation. At this time, the collector pulling portion 5 has a shape surrounding the base region 7.

Then, a surface protective film 6, for example, an oxide film of 500 to 1000 ° is formed on the silicon semiconductor substrate 1, and a P-type base region 7 and an N ⁺ -type Emitter region 8
To form Then, the first emitter electrode 9, the first base electrode 10, and the collector electrode 11 are formed respectively. At this time, Au, Al, and a barrier metal may be used as the electrode material, and plating, sputtering, or the like is used as the forming method.

Next, the interlayer insulating film 1 is formed by a plasma nitride film.
After the formation of the second electrode 2, a through hole contact 13 is formed by a photoresist method and etching, and a second emitter electrode 14 and a second base electrode 15 are formed. Finally, a collector pad opening 16 for the collector electrode is formed by a photoresist method and etching, and the shapes shown in FIGS. 1 to 3 are obtained. The case where the number of electrodes is increased with reference to FIG. 3 will be described.
When the number of emitters increases as in the transistor cell of
The above-mentioned transistor is considered as one unit cell, and the number is increased instead of increasing in a vertical stack type.

That is, in the present invention, since the unit cells are arranged two by two in line symmetry, at this time, the emitter second electrode 14 and its through-hole contact 13 face the center of each other and the emitter second electrode 14 Becomes the fish bone. The base is pulled out from the surroundings by the base first electrode 10, the through-hole contact 13, and the base second electrode 15, and the collector is drawn from the collector electrode 11.
With one layer. The same applies to the case where the number of emitters is six or eight.

Next, a second embodiment of the present invention will be described with reference to FIGS. Also in this example,
N formed by implantation of arsenic or diffusion of antimony into a P-type silicon semiconductor substrate 1 having a specific resistance of about 20 to 40 Ω · cm.
⁺ N-type impurity concentration in the buried layer 2 is 1 × 10 ^{15 to} 1 × 10
An epitaxial layer 3 having a thickness of ¹⁶ cm ^-3 and a thickness of 1.0 to 2.5 μm is grown.

Next, as in the first embodiment, a high-concentration collector pull-up portion 5 is formed by a photoresist method and ion implantation. Then, a surface protection film 6, for example, an oxide film of 500 to 1000 ° is formed on the silicon semiconductor substrate 1, and a P-type base region 7 and an N ⁺ -type emitter region 8 are formed by a photoresist method, etching, ion implantation method, or the like.
To form At this time, the first base electrode 10 formed on the base region 7 surrounds the emitter region 8.

Then, the first emitter is formed on the emitter region 8.
An electrode 9, a square-shaped base first electrode 10 on the base region 7, and a square-shaped collector electrode 11 on the collector pulling portion 5 are formed. The following is the same as in the first embodiment. By surrounding the first base electrode 10 with the emitter region 8, the base resistance can be reduced, the current imbalance can be prevented, the high-frequency characteristics can be improved, and
Reliability is improved.

That is, in the present invention, the four sides of the base region 7 are surrounded by the high-concentration second-conductivity-type collector pull-up portion 5 and the four sides of the base region 7 are surrounded by the second-conductivity-type collector pull-up portion 5. The collector current flows uniformly in the device because it is surrounded by the collector electrode 11 formed in a square shape that is conductive to the element. Therefore, the collector resistance is reduced. Further, according to the present invention, instead of the configuration as shown in FIG. 8 having a high collector resistance, the four sides of the base region 7 are surrounded by the high-concentration second conductivity type collector pull-up portion 5 and the four sides of the base region 7 are formed. Is surrounded by a collector electrode 11 conducting to the collector pull-up portion 5 of the second conductivity type, an emitter second electrode 14 is drawn out to one side of the semiconductor integrated circuit, and a base second electrode 15 is drawn to the other side. Are formed, and an even number of unit cells are arranged so that the emitter second electrodes 14 of the unit cells face each other.
Since the electrodes 14 are connected and the second emitter electrodes 14 are arranged as if they were fish-bones, the collector resistance of the unit cell is small, so that the collector resistance of the semiconductor integrated circuit shown in FIG. 3 is also small.

[0028]

According to the present invention, since the configuration is as described above, even when the number of emitter electrodes is increased, the collector resistance is reduced and the high frequency characteristics are improved. Further, since no current imbalance occurs, thermal runaway does not occur and reliability is improved.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor integrated circuit according to the present invention.

2A is a sectional view taken along line XX of FIG. 1, and FIG. 2B is a sectional view taken along line YY of FIG.

FIG. 3 is a plan view in which the unit cells of FIG. 1 are arranged in a fish bone shape.

FIG. 4 is a plan view of a semiconductor integrated circuit according to another embodiment of the present invention.

5A is a sectional view taken along line XX of FIG. 4, and FIG. 5B is a sectional view taken along line YY of FIG.

FIG. 6 is a sectional view showing a conventional example.

FIGS. 7A and 7B are other views showing a conventional example.

8A, 8B, and 8C are another plan view, an XX sectional view, and a YY sectional view showing a conventional example, respectively.

FIGS. 9A and 9B are another plan view and a cross-sectional view showing a conventional example, respectively.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 silicon semiconductor substrate 2 buried layer 3 collector 4 element isolation region 5 high-concentration collector pull-up portion 6 surface protective film 7 base region 8 emitter region 9 emitter first electrode 10 base first electrode 11 collector electrode 12 interlayer insulating film 13 through Hole contact 14 Emitter second electrode 15 Base second electrode 16 Collector pad opening

Claims (7)

[Claims] A collector region of a second conductivity type is disposed on a semiconductor substrate of a first conductivity type, a base region of a first conductivity type in the collector region, and a second conductivity type in a base region thereof. In the bipolar semiconductor integrated circuit in which the emitter region is formed, four sides of the base region are surrounded by a high-concentration second conductivity type collector pull-up portion, and four sides of the base region are covered by the second conductivity type collector. A semiconductor integrated circuit, wherein the semiconductor integrated circuit is surrounded by a collector electrode conducting to a pull-up portion. 2. The semiconductor integrated circuit according to claim 1, wherein four sides of said emitter region are surrounded by a base electrode. 3. The semiconductor integrated circuit according to claim 1, wherein the emitter electrode is formed on one side of the collector electrode, and a base electrode is formed on the other side. 4. A collector region of a second conductivity type is disposed on a semiconductor substrate of a first conductivity type, a base region of a first conductivity type in the collector region, and an emitter of a second conductivity type in the base region. A semiconductor integrated circuit having a region formed therein, wherein four sides of the base region are surrounded by a high-concentration second-conductivity-type collector pull-up portion, and four sides of the base region are raised by the second-conductivity-type collector. Forming a unit cell which is surrounded by a collector electrode which conducts to a portion, and an emitter electrode is drawn out on one side of the semiconductor integrated circuit, and a base electrode is drawn out on the other side, and the emitter electrode of this unit cell is formed. Wherein an even number of the unit cells are arranged so as to face each other, the respective emitter electrodes are connected, and an emitter electrode is arranged between the unit cells. Integrated circuit. 5. The semiconductor integrated circuit according to claim 4, wherein four sides of said emitter region are surrounded by a base electrode. 6. A collector region of a second conductivity type is disposed on a semiconductor substrate of a first conductivity type, a base region of a first conductivity type in the collector region, and a second conductivity type in a base region of the second conductivity type. In the bipolar semiconductor integrated circuit in which the emitter region is formed, four sides of the base region are surrounded by a high-concentration second conductivity type collector pull-up portion, and four sides of the base region are covered by the second conductivity type collector. A collector resistance reducing method for a semiconductor integrated circuit, wherein a collector resistance is reduced by surrounding the collector electrode with a collector electrode that is electrically connected to a pull-up portion. 7. The method according to claim 6, wherein four sides of the emitter region are surrounded by a base electrode.