JP2518413B2 - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

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Publication number
JP2518413B2
JP2518413B2 JP1205926A JP20592689A JP2518413B2 JP 2518413 B2 JP2518413 B2 JP 2518413B2 JP 1205926 A JP1205926 A JP 1205926A JP 20592689 A JP20592689 A JP 20592689A JP 2518413 B2 JP2518413 B2 JP 2518413B2
Authority
JP
Japan
Prior art keywords
collector
base
electrode
integrated circuit
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1205926A
Other languages
Japanese (ja)
Other versions
JPH0369124A (en
Inventor
紳一 宮崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP1205926A priority Critical patent/JP2518413B2/en
Publication of JPH0369124A publication Critical patent/JPH0369124A/en
Application granted granted Critical
Publication of JP2518413B2 publication Critical patent/JP2518413B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路に関し、特に高周波特性に優
れたパワー用バイポーラICに関する。
The present invention relates to a semiconductor integrated circuit, and more particularly to a power bipolar IC excellent in high frequency characteristics.

〔従来の技術〕[Conventional technology]

従来、高周波バイポーラICでは、その製法の容易さあ
るいは工程の簡単さによって、いわゆる櫛形(インター
ディジタル)電極が採用されている。これは、特に大電
流を取扱うパワーICにおいても例外ではない。
Conventionally, in a high-frequency bipolar IC, a so-called comb-shaped (interdigital) electrode has been adopted because of its easy manufacturing method or simple process. This is not an exception, especially in power ICs that handle large currents.

通常のパワーICでの平面図及び構造断面図の一例を、
第6図(a)、(b)、(c)に示す。
An example of a plan view and a structural sectional view of a normal power IC,
It is shown in FIGS. 6 (a), (b) and (c).

同図(a)は平面図、同図(b)はそのX−X断面
図、同図(c)はそのY−Y断面図である。
The figure (a) is a top view, the figure (b) is the XX sectional view, and the figure (c) is the YY sectional view.

ただし第6図では、簡単のため中央部を簡略化してい
る。1はベース電極、2はエミッタ電極、3はコレクタ
電極、4は表面保護用膜で例えば酸化膜、5は分離用酸
化膜、6はエミッタ、7はベース、8はコレクタ(エピ
タキシャル層)、9は埋込層、10はコレクタ引上げ部、
11はP形半導体基板である。
However, in FIG. 6, the central portion is simplified for simplification. 1 is a base electrode, 2 is an emitter electrode, 3 is a collector electrode, 4 is a surface protection film, for example, an oxide film, 5 is an isolation oxide film, 6 is an emitter, 7 is a base, 8 is a collector (epitaxial layer), 9 Is a buried layer, 10 is a collector pulling part,
Reference numeral 11 is a P-type semiconductor substrate.

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

一方、大電力化を図るためには、大電流を流すことが
必要になるが、電極1本当りに流せる電流は、電極の材
質やその寸法で制限されるため、電極の数を増やさざる
を得ない。
On the other hand, in order to increase the power consumption, it is necessary to flow a large current, but the current that can be passed per electrode is limited by the material and size of the electrode, so the number of electrodes must be increased. I don't get it.

しかしながら、従来のICでは第6図に示すように、相
対するコレクタ電極3を有することで、コレクタ抵抗r
SCの低減を図っているが、大電力化のために電極の本数
を増やしていくと、必然的にコレクタ抵抗rSCが増大す
るばかりでなく、例えば、中央部とコレクタ電極3の近
傍とでは、コレクタ抵抗rSCが大きく異なることから電
流のアンバランスが生じ、熱暴走等の問題も生じる。
However, in the conventional IC, as shown in FIG. 6, by having the collector electrodes 3 facing each other, the collector resistance r
Although SC is being reduced, when the number of electrodes is increased to increase the power, not only the collector resistance r SC inevitably increases, but, for example, in the central portion and the vicinity of the collector electrode 3, Since the collector resistances r SC are greatly different, current imbalance occurs and problems such as thermal runaway occur.

又、従来の構造では、第6図(c)に示すように、ベ
ース電極1は表面保護用膜4の例えば酸化膜上に配置さ
れるが、この表面保護用膜4にはエミッタ、ベース、コ
レクタのコンタクトを通例、同時に開孔するため、微細
エミッタ形成のためにはできるだけ薄いことが望ましい
が、後述するベース電極の容量低減のためにコレクタ周
辺のみ厚くすると、微細エミッタの形成が困難となる。
Further, in the conventional structure, as shown in FIG. 6 (c), the base electrode 1 is arranged on, for example, an oxide film of the surface protection film 4, and the surface protection film 4 includes an emitter, a base, Since the contacts of the collector are usually opened at the same time, it is desirable to be as thin as possible for forming a fine emitter. However, if the thickness of only the periphery of the collector is increased to reduce the capacitance of the base electrode described later, it becomes difficult to form the fine emitter. .

これを回避するには、コレクタコンタクト用マスクを
1枚追加する必要があり、工程が長くなってしまう。一
方、パワーICともなると、電極数が相当多く、そのた
め、引きまわすベース電極の長さが無視できないほど長
くなるため、表面保護用膜4の厚さが薄いと、耐コレク
タ容量CPが非常に大きくなる。
In order to avoid this, it is necessary to add one more mask for collector contact, which makes the process longer. On the other hand, when it comes to a power IC, the number of electrodes is considerably large, and therefore the length of the base electrode to be drawn around becomes too long to be ignored. Therefore, when the thickness of the surface protection film 4 is thin, the collector resistance C P becomes extremely high. growing.

又、パワー用ICのベース面積が大きいため、コレクタ
・ベース接合容量CJC自体が大きいことから、実際のコ
レクタ・ベース容量CCB=CJC+CPは極めて大きいものと
なり、前述したコレクタ抵抗rSCをも考慮すると、しゃ
断周波数fTや電力利得(例えば|S21e|2)は大きく劣化
してしまい、高周波特性の優れたICを実現できないとい
う欠点がある。
Further, since a large base area of the IC for power, since the collector-base junction capacitance C JC itself is large, the actual collector-base capacitance C CB = C JC + C P becomes extremely large, the collector resistance r SC described above In consideration of the above, the cutoff frequency f T and the power gain (for example, | S 21e | 2 ) are greatly deteriorated, and there is a drawback that an IC having excellent high frequency characteristics cannot be realized.

上述した従来のパワーICに対し、本発明はベース領域
の少なくとも三方を高濃度のコレクタ引上げ部で外囲
し、且つベース領域との間に厚い絶縁層膜を設けること
により、コレクタ抵抗rSCを低減するとともに均一化
し、且つベース電極の対コレクタ容量を低減するという
相違点を有する。
In contrast to the conventional power IC described above, according to the present invention, at least three sides of the base region are surrounded by the high-concentration collector pull-up portion, and a thick insulating layer film is provided between the base region and the collector resistance r SC . The difference lies in that the capacitance is reduced and made uniform, and the capacitance of the base electrode with respect to the collector is reduced.

〔課題を解決するための手段〕[Means for solving the problem]

本発明は、第1導電型半導体基板上に第2導電型のコ
レクタ領域を有し、前記コレクタ領域内に第1導電型の
ベース、及び該ベース内に第2導電型のエミッタを有す
るバイポーラ半導体集積回路において、前記ベース領域
の少なくとも三辺を高濃度の第2導電型コレクタ引上げ
部で外囲し、且つコレクタ引上げ部で外囲された少なく
とも一辺でベース領域とコレクタ引上げ部間とを少なく
とも5000Å以上の厚さの絶縁膜で分離し、前記ベース領
域の第1の個所に接続したベース電極が前記絶縁膜上を
延在して前記ベース領域の第2の個所に接続している半
導体集積回路である。
The present invention provides a bipolar semiconductor having a second conductivity type collector region on a first conductivity type semiconductor substrate, a first conductivity type base in the collector region, and a second conductivity type emitter in the base. In the integrated circuit, at least three sides of the base region are surrounded by a high-concentration second-conductivity-type collector pull-up part, and at least one side surrounded by the collector pull-up part has a distance of at least 5000Å between the base region and the collector pull-up part. A semiconductor integrated circuit in which a base electrode separated by an insulating film having the above thickness and connected to a first portion of the base region extends over the insulating film and is connected to a second portion of the base region. Is.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.

第1図(a)、(b)、(c)は本発明の第1の実施
例を示す。本例は、ベース領域の3辺をコレクタ引上げ
部で外囲した例であり、図(a)に平面図、図(b)に
そのX−X断面図、図(c)にそのY−Y断面図を示
す。又、第1図では簡単のため、中央部は省略してい
る。
1 (a), (b), and (c) show a first embodiment of the present invention. This example is an example in which three sides of the base region are surrounded by a collector pull-up portion. A plan view is shown in FIG. 10A, an X-X cross-sectional view thereof is shown in FIG. A sectional view is shown. Further, in FIG. 1, the central portion is omitted for simplicity.

ここで1はベース電極、2はエミッタ電極、3はコレ
クタ電極、4は表面保護用膜で例えば酸化膜であり、5
は分離用酸化膜、6はエミッタ、7はベース、8はコレ
クタ(エピタキシャル層)、9は埋込層、10はコレクタ
引上げ部の高濃度領域、11はP型半導体基板、12は容量
低減用絶縁膜である。
Here, 1 is a base electrode, 2 is an emitter electrode, 3 is a collector electrode, 4 is a surface protection film, for example, an oxide film, and 5
Is an isolation oxide film, 6 is an emitter, 7 is a base, 8 is a collector (epitaxial layer), 9 is a buried layer, 10 is a high-concentration region of the collector pulling portion, 11 is a P-type semiconductor substrate, and 12 is for capacitance reduction. It is an insulating film.

12の容量低減用絶縁膜としては、誘電率の低い物質、
例えば酸化膜が望ましく、又その形成方法としては、熱
酸化でもよいし、Siのエッチング後、酸化膜を埋設する
等の方法でもよい。その厚みと幅は容量低減には5000Å
以上が望ましく、エピタキシャル厚、電極幅等を勘案し
て決定すればよい。
As the capacitance reducing insulating film 12, a material having a low dielectric constant,
For example, an oxide film is desirable, and the method of forming the oxide film may be thermal oxidation or a method of burying the oxide film after etching S i . Its thickness and width are 5000Å for capacity reduction
The above is desirable, and it may be determined in consideration of the epitaxial thickness, the electrode width, and the like.

本実施例によれば、図(b)に示すコレクタ抵抗
rSC′より図(c)に示すY−Y方向のコレクタ抵抗
rSC″は遥かに小さくできるから、全体としてコレクタ
抵抗rSCも小さく、且つ全てのエミッタの位置に拘わら
ずバランスよくトランジスタ動作をさせることができ
る。
According to this embodiment, the collector resistance shown in FIG.
Collector resistance in the Y-Y direction shown in Fig. (c) from r SC '
Since r SC ″ can be made much smaller, the collector resistance r SC is also small as a whole, and a balanced transistor operation can be performed regardless of the positions of all the emitters.

又、より一層、コレクタ抵抗を下げる目的で、第2図
(a)、(b)の平面図及びそのY−Y断面図で示す第
2の実施例のように、コレクタ引上げ部10でベース領域
7を全て外囲してもよい。
Further, in order to further reduce the collector resistance, as in the second embodiment shown in the plan views of FIGS. 2A and 2B and the Y-Y sectional view thereof, the collector pull-up portion 10 is used to form the base region. All 7 may be enclosed.

又、ベース電極1を引出す際の容量低減のために、容
量低減用絶縁膜12で四方を外囲してもよい。又、コレク
タ引上げ部10の不純物濃度として、1×1018/cm3程度
以上あれば充分効果を発揮しうる。
In addition, in order to reduce the capacitance when the base electrode 1 is drawn out, a capacitance reducing insulating film 12 may surround all four sides. Further, if the impurity concentration of the collector pulling portion 10 is about 1 × 10 18 / cm 3 or more, the effect can be sufficiently exhibited.

第3図は本発明の第3の実施例の平面図で、更にコレ
クタ抵抗低減を図るために、コレクタ引上げ部10を3箇
所とした場合である。勿論、必要に応じて、コレクタ引
上げ部10を4箇所以上とることも同様に可能である。
FIG. 3 is a plan view of the third embodiment of the present invention, in which the collector pull-up portions 10 are provided at three locations in order to further reduce the collector resistance. Of course, if necessary, the collector pull-up portions 10 may be provided in four or more places as well.

第4図の平面図は、バラスト抵抗付きのパワーICに本
発明を応用した第4の実施例である。本来、バラスト抵
抗13を使用すると、抵抗による負帰還で利得の低下を招
き、又、バランスをとるための抵抗値の設計が難しいと
いった点でパワーICには不向きであるが、ICの安定化の
ために敢えて使用せざるを得ない場合も、本発明を適用
することでバラスト抵抗の値は一定でよく、しかも、小
さい抵抗値で充分安定化に寄与するから、利得の減少も
小さくすることが可能となる。
The plan view of FIG. 4 shows a fourth embodiment in which the present invention is applied to a power IC with a ballast resistor. Originally, if the ballast resistor 13 is used, it is not suitable for a power IC because it causes a decrease in gain due to negative feedback due to the resistance and it is difficult to design a resistance value for balancing. Therefore, even if it is unavoidable to use it, the value of the ballast resistance may be constant by applying the present invention, and since a small resistance value contributes to sufficient stabilization, the decrease in gain can be reduced. It will be possible.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明は、コレクタ抵抗を低減
し、更にベース電極のコレクタに対する浮遊容量をも低
減するから、従来構造に比べ安定な動作を実現すると共
に、高周波特性も大きく改善できる。
As described above, according to the present invention, the collector resistance is reduced and the stray capacitance of the base electrode with respect to the collector is also reduced. Therefore, stable operation can be realized and the high frequency characteristics can be greatly improved as compared with the conventional structure.

第5図は本発明の第1図に示す構造のトランジスタ
と、第6図に示す従来構造のトランジスタとの高周波特
性を、しゃ断周波数fT及び電力利得|S21e|2について、
実測、比較したグラフであり、両者のトランジスタは設
計ルール、エミッタサイズ、本数等は全て同一である。
A transistor having the structure shown in FIG. 1 in Fig. 5 the present invention, the high frequency characteristics of the transistor of the conventional structure shown in FIG. 6, cut-off frequency f T and power gain | About 2, | S 21e
It is a graph obtained by actual measurement and comparison, and both transistors have the same design rule, emitter size, number, and the like.

第5図より、従来構造のトランジスタに比べ、fTで約
2GHZ、|S21e|2で約1dBの改善がなされ、しかも、fTが最
大になるコレクタ電流Icmaxは、約10mA以上向上してい
ることがわかる。これらのデータは、本発明の有効性を
充分明らかにするものである。
From Fig. 5, it can be seen that f T is about
It can be seen that 2GH Z and | S 21e | 2 improve by about 1 dB, and the collector current I c max at which f T becomes maximum is improved by about 10 mA or more. These data fully demonstrate the effectiveness of the present invention.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の第1の実施例で、図(a)は平面図、
図(b)はそのX−X断面図、図(c)はそのY−Y断
面図、第2図は本発明の第2の実施例で、図(a)は平
面図、図(b)はそのY−Y断面図、第3図は本発明の
第3の実施例の平面図、第4図は本発明の第4の実施例
の平面図、第5図は従来構造と本発明の構造のトランジ
スタの高周波特性の比較(実測)を示すグラフ、第6図
は従来構造の例を示す図で、図(a)は平面図、図
(b)はそのX−X断面図、図(c)はそのY−Y断面
図である。 1……ベース電極、2……エミッタ電極、3……コレク
タ電極、4……表面保護用膜、5……分離用酸化膜、6
……エミッタ、7……ベース、8……コレクタ(エピタ
キシャル層)、9……埋込層、10……コレクタ引上げ
部、11……P型半導体基板、12……容量低減用絶縁膜。
1 is a first embodiment of the present invention, FIG. 1 (a) is a plan view,
Figure (b) is its XX cross section, Figure (c) is its YY cross section, Figure 2 is a second embodiment of the present invention, Figure (a) is a plan view, and Figure (b). FIG. 3 is a plan view of a third embodiment of the present invention, FIG. 4 is a plan view of a fourth embodiment of the present invention, and FIG. 5 is a conventional structure and the present invention. FIG. 6 is a graph showing comparison (measurement) of high frequency characteristics of transistors having a structure, FIG. 6 is a diagram showing an example of a conventional structure, FIG. 6A is a plan view, FIG. c) is the YY sectional view. 1 ... Base electrode, 2 ... Emitter electrode, 3 ... Collector electrode, 4 ... Surface protection film, 5 ... Separation oxide film, 6
...... Emitter, 7 …… Base, 8 …… Collector (epitaxial layer), 9 …… Buried layer, 10 …… Collector pull-up part, 11 …… P-type semiconductor substrate, 12 …… Capacitance reduction insulating film.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】第1導電型半導体基板上に第2導電型のコ
レクタ領域を有し、前記コレクタ領域内に第1導電型の
ベース、及び該ベース内に第2導電型のエミッタを有す
るバイポーラ半導体集積回路において、前記ベース領域
の少なくとも三辺を高濃度の第2導電型コレクタ引上げ
部で外囲し、且つコレクタ引上げ部で外囲された少なく
とも一辺でベース領域とコレクタ引上げ部間とを少なく
とも5000Å以上の厚さの絶縁膜で分離し、前記ベース領
域の第1の個所に接続したベース電極が前記絶縁膜上を
延在して前記ベース領域の第2の個所に接続しているこ
とを特徴とする半導体集積回路。
1. A bipolar having a second conductivity type collector region on a first conductivity type semiconductor substrate, a first conductivity type base in the collector region, and a second conductivity type emitter in the base. In a semiconductor integrated circuit, at least three sides of the base region are surrounded by a high-concentration second-conductivity-type collector pulling-up portion, and at least one side surrounded by the collector pulling-up portion extends at least between the base region and the collector pulling-up portion. The base electrode, which is separated by an insulating film with a thickness of 5000 Å or more and is connected to the first part of the base region, extends over the insulating film and is connected to the second part of the base region. A characteristic semiconductor integrated circuit.
JP1205926A 1989-08-08 1989-08-08 Semiconductor integrated circuit Expired - Fee Related JP2518413B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1205926A JP2518413B2 (en) 1989-08-08 1989-08-08 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1205926A JP2518413B2 (en) 1989-08-08 1989-08-08 Semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPH0369124A JPH0369124A (en) 1991-03-25
JP2518413B2 true JP2518413B2 (en) 1996-07-24

Family

ID=16515028

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1205926A Expired - Fee Related JP2518413B2 (en) 1989-08-08 1989-08-08 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JP2518413B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100857769B1 (en) * 2008-01-11 2008-09-09 주식회사 동양이지텍 Ground equipment with microcomputer for electric field-shielding of hot-water boiler mat

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5396766A (en) * 1977-02-04 1978-08-24 Nec Corp Semiconductor device

Also Published As

Publication number Publication date
JPH0369124A (en) 1991-03-25

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