JPS59172745A - 半導体装置の電極形成方法 - Google Patents
半導体装置の電極形成方法Info
- Publication number
- JPS59172745A JPS59172745A JP58048115A JP4811583A JPS59172745A JP S59172745 A JPS59172745 A JP S59172745A JP 58048115 A JP58048115 A JP 58048115A JP 4811583 A JP4811583 A JP 4811583A JP S59172745 A JPS59172745 A JP S59172745A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- chromium
- copper
- electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58048115A JPS59172745A (ja) | 1983-03-22 | 1983-03-22 | 半導体装置の電極形成方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58048115A JPS59172745A (ja) | 1983-03-22 | 1983-03-22 | 半導体装置の電極形成方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59172745A true JPS59172745A (ja) | 1984-09-29 |
| JPH0473292B2 JPH0473292B2 (OSRAM) | 1992-11-20 |
Family
ID=12794313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58048115A Granted JPS59172745A (ja) | 1983-03-22 | 1983-03-22 | 半導体装置の電極形成方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59172745A (OSRAM) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0652590A1 (en) * | 1993-11-05 | 1995-05-10 | Casio Computer Co., Ltd. | Method of fabricating a semiconductor device with a bump electrode |
| US5511435A (en) * | 1993-10-04 | 1996-04-30 | Casio Computer Co., Ltd. | Apparatus for measuring vehicle running condition |
| US6723628B2 (en) | 2000-03-27 | 2004-04-20 | Seiko Epson Corporation | Method for forming bonding pad structures in semiconductor devices |
| US6812123B2 (en) | 2000-03-27 | 2004-11-02 | Seiko Epson Corporation | Semiconductor devices and methods for manufacturing the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54101263A (en) * | 1978-01-26 | 1979-08-09 | Nec Corp | Semiconductor device |
| JPS57170555A (en) * | 1981-03-30 | 1982-10-20 | Ibm | Solder supporting pad |
-
1983
- 1983-03-22 JP JP58048115A patent/JPS59172745A/ja active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54101263A (en) * | 1978-01-26 | 1979-08-09 | Nec Corp | Semiconductor device |
| JPS57170555A (en) * | 1981-03-30 | 1982-10-20 | Ibm | Solder supporting pad |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5511435A (en) * | 1993-10-04 | 1996-04-30 | Casio Computer Co., Ltd. | Apparatus for measuring vehicle running condition |
| EP0652590A1 (en) * | 1993-11-05 | 1995-05-10 | Casio Computer Co., Ltd. | Method of fabricating a semiconductor device with a bump electrode |
| US5538920A (en) * | 1993-11-05 | 1996-07-23 | Casio Computer Co., Ltd. | Method of fabricating semiconductor device |
| US5705856A (en) * | 1993-11-05 | 1998-01-06 | Casio Computer Co., Ltd. | Semiconductor device |
| US6723628B2 (en) | 2000-03-27 | 2004-04-20 | Seiko Epson Corporation | Method for forming bonding pad structures in semiconductor devices |
| US6812123B2 (en) | 2000-03-27 | 2004-11-02 | Seiko Epson Corporation | Semiconductor devices and methods for manufacturing the same |
| US7091609B2 (en) * | 2000-03-27 | 2006-08-15 | Seiko Epson Corporation | Semiconductor devices including an alloy layer and a wetting layer on an interlayer dielectric |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0473292B2 (OSRAM) | 1992-11-20 |
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