JPS59159547A - 半導体素子の保護方法 - Google Patents

半導体素子の保護方法

Info

Publication number
JPS59159547A
JPS59159547A JP58033771A JP3377183A JPS59159547A JP S59159547 A JPS59159547 A JP S59159547A JP 58033771 A JP58033771 A JP 58033771A JP 3377183 A JP3377183 A JP 3377183A JP S59159547 A JPS59159547 A JP S59159547A
Authority
JP
Japan
Prior art keywords
resin
flow
semiconductor element
semiconductor
stop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58033771A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0345538B2 (enExample
Inventor
Toshihiro Nomura
野村　敏裕
Kazuyuki Shimada
和之 嶋田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58033771A priority Critical patent/JPS59159547A/ja
Publication of JPS59159547A publication Critical patent/JPS59159547A/ja
Publication of JPH0345538B2 publication Critical patent/JPH0345538B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/40—Fillings or auxiliary members in containers, e.g. centering rings
    • H10W76/42—Fillings
    • H10W76/47—Solid or gel fillings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP58033771A 1983-03-03 1983-03-03 半導体素子の保護方法 Granted JPS59159547A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58033771A JPS59159547A (ja) 1983-03-03 1983-03-03 半導体素子の保護方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58033771A JPS59159547A (ja) 1983-03-03 1983-03-03 半導体素子の保護方法

Publications (2)

Publication Number Publication Date
JPS59159547A true JPS59159547A (ja) 1984-09-10
JPH0345538B2 JPH0345538B2 (enExample) 1991-07-11

Family

ID=12395708

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58033771A Granted JPS59159547A (ja) 1983-03-03 1983-03-03 半導体素子の保護方法

Country Status (1)

Country Link
JP (1) JPS59159547A (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4999319A (en) * 1986-03-19 1991-03-12 Fujitsu Limited Method of manufacturing semiconductor device having package structure
US5087961A (en) * 1987-01-28 1992-02-11 Lsi Logic Corporation Semiconductor device package
WO2002043135A1 (fr) * 2000-11-22 2002-05-30 Niigata Seimitsu Co., Ltd. Dispositif semi-conducteur et procede de fabrication associe

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56129738U (enExample) * 1980-02-29 1981-10-02

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56129738U (enExample) * 1980-02-29 1981-10-02

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4999319A (en) * 1986-03-19 1991-03-12 Fujitsu Limited Method of manufacturing semiconductor device having package structure
US5087961A (en) * 1987-01-28 1992-02-11 Lsi Logic Corporation Semiconductor device package
WO2002043135A1 (fr) * 2000-11-22 2002-05-30 Niigata Seimitsu Co., Ltd. Dispositif semi-conducteur et procede de fabrication associe

Also Published As

Publication number Publication date
JPH0345538B2 (enExample) 1991-07-11

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