CN105321909B - 电子装置及封装电子装置的方法 - Google Patents

电子装置及封装电子装置的方法 Download PDF

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CN105321909B
CN105321909B CN201410582016.8A CN201410582016A CN105321909B CN 105321909 B CN105321909 B CN 105321909B CN 201410582016 A CN201410582016 A CN 201410582016A CN 105321909 B CN105321909 B CN 105321909B
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packaging body
electronic installation
semiconductor device
circuit board
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CN105321909A (zh
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蔡佳龙
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Himax Display Inc
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Abstract

本发明公开一种电子装置及封装电子装置的方法,该电子装置包含:一电路板;一半导体装置,设置于该电路板上;一保护材料,设置于该半导体装置上方;多条接合线,分别连接于该半导体装置上的多个第一连接垫以及该电路板上的多个第二连接垫之间;一第一封装体,由一第一材料所形成,用来封装每一条接合线的一部分线体,以及封装多个第二接合点,其中,该些第二接合点由该些接合线与该些第二连接垫连接所形成;以及一第二封装体,由一第二材料所形成,该第二材料不同于该第一材料,该第二封装体用来封装多个第一接合点,该些第一接合点由该些接合线与该些第一连接垫连接所形成。

Description

电子装置及封装电子装置的方法
技术领域
本发明涉及电子元件的封装,尤其是涉及一种使用不同封装体,对一电子装置的打线接合(wire bond)进行封装的部分圆顶封装(partial glob-top encapsulation)的技巧,以及相关方法。
背景技术
所谓的圆顶封装(glob-top encapsulation)是一种表面涂覆(conformalcoating)封装技术,其可用于保护Chip-on-board(COB)组装元件的裸管芯(bare die)以及接线。在COB组装中,裸管芯直接黏合在电路板上,而裸管芯又以打线接合的方式,与电路板上的连接垫(contact pad)电连接。圆顶封装技术通过将封胶材料,例如:环氧树脂(epoxy)或硅氧树酯(silicone),涂覆在裸管芯、金属导线、接合点上,并将其固化后形成封装体,从而提供一层屏障来阻绝应力、污染物、热冲击、以及湿气。
在某些光学相关的应用上,如液晶覆硅(Liquid Crystal on Silicon,LCoS)显示装置,其在裸管芯,或者是硅背板(silicon backplane)的上方会覆盖一层保护玻璃(保护玻璃)。并且,封装体只覆盖管芯的部分区域,而未覆盖整个保护玻璃。这种封装方式被称作为部分圆顶封装(partial glob-top encapsulation)。在这种技术中,有时候由于保护玻璃的边缘与管芯的侧边并未切齐,因此可能在管芯的转角处形成一凹口,进而产生对封装体的断裂韧性(fracture toughness)有不良影响的凹口效应(notch effect)。
请参考图1,该图绘示一种现有的部分圆顶封装技术。其中,管芯110通过金属导线130,电连接至一电路板120。而在管芯110的上方则有一层保护玻璃,并且,由封胶材料经过固化处理形成的封装体150,覆盖在金属导线130与接合点160上。一般来说,为了抵抗外在应力,封装体150必需足够坚硬,然而,由于保护玻璃140的侧面142并未与管芯110的侧面112切齐,因此凹口170会在管芯110的转角处形成。如此一来便容易引发凹口效应(notcheffect),这个效应会使得封装体150变脆。这是因为应力会集中在凹口170,因此造成封装体150的疲劳性破坏。当封装体150越硬时,这个效应越明显。
最简单的解决方法就是使用较软的封胶材料来形成封装体150,然而,这样可能会使封装体150的保护性不足,而无法抵抗外部应力,以至于金属导线130与接合点160对于物理破坏的耐受度较差。因此,有必要提供一种创新的方式来解决以上的问题。
发明内容
有鉴于此,本发明的目的在于提供一种混合式的封装技术,主要通过在接线的不同侧使用不同的封装体来包覆接合线以及接合点。
为达上述目的,本发明的一实施例提供一电子装置,该电子装置包含:一电路板;一半导体装置,设置于该电路板上;一保护材料,设置于该半导体装置上方;多条接合线,分别连接于该半导体装置上的多个第一连接垫以及该电路板上的多个第二连接垫之间;一第一封装体,由一第一材料所形成,用来封装每一条接合线的一部分线体,以及封装多个第二接合点,其中,该些第二接合点由该些接合线与该些第二连接垫连接所形成;以及一第二封装体,由一第二材料所形成,该第二材料不同于该第一材料,该第二封装体用来封装多个第一接合点,其中该些第一接合点由该些接合线与该些第一连接垫连接所形成。
本发明的另一实施例一种封装一电子装置的方法。该电子装置具有一电路板,且一半导体装置设置于该电路板上,并且通过多条接合线与该电路板电连接。一保护材料设置于该半导体装置的上方。该方法包含:将一第一材料涂覆在该电路板上的多个第二接合点,以及每一条接合线的一部分线体,并且将该第一材料固化,形成一第一封装体,该第二接合点连接于该些接合线;以及将一第二材料涂覆在该半导体装置上的多个第一接合点,并且将该第二材料固化,形成一第二封装体,其中该第一接合点连接于该些接合线。
附图说明
图1为现有的圆顶封装技术的示意图;
图2为本发明电子装置的一实施例的示意图;
图3为图2的电子装置的一侧视图;
图4为本发明的一实施例的封装一电子装置的方法的流程图。
符号说明
100、200 电子装置
110 裸管芯
112、142 侧面
120、220 电路板
130 金属导线
140 保护玻璃
150、252、254 封装体
160 接合点
170 凹口
210 半导体装置
230 接合线
232、234 连接垫
240 保护材料
262、264 接合点
280 半导体装置的表面区域
290 空间
具体实施方式
请参考图2,该图绘示本发明的一实施例的电子装置200。如图所示,半导体装置210黏合在电路板220上。在本发明不同实施例中,电路板220可为一般的印刷电路板或者是软性印刷电路板(flexible printed circuit)。半导体装置210可能为裸管芯或者是液晶覆硅装置的硅背板,而电子装置200可能是一个液晶覆硅装置,或者是一个COB组装元件。保护材料240设置在半导体装置210的上方,其可为一保护玻璃。
半导体装置210与电路板220之间以多条金属接合线(bonding wires)230(如:铝线)相连。多个第一接合点264,由接合线230的第一端分别与半导体装置210上的连接垫234电连接(例如:焊接)所形成。多个第二接合点262,由接合线230的第二端分别与电路板220上的连接垫232电连接所形成。
第一封装体252由第一材料所形成,第一材料不同于形成第二封装体254的第二材料。再者,第一封装体252比第二封装体254更为坚硬。第一封装体252与第二封装体254分别覆盖在第二接合点262以及第一接合点264上。第一封装体252将每一条接合线230的大部分线体封装起来,此外,每一条接合线230靠近第一接合点264的第二端则由第二封装体254所封装。
由于第一封装体252将每一条接合线230的大部分线体封装,基于异质材料接合(heterogeneous materials joint)的原因,必须将材料间的热膨胀系数(coefficient ofthermal expansion,CTE)的匹配纳入考虑。也就是,第一封装体252的热膨胀系数必须不大于接合线230的热膨胀系数,否则,将会形成内部应力,对接合线230产生拉扯的现象。举例来说,若接合线230为铝线,并且热膨胀系数为24ppm/K,那么第一封装体252的热膨胀系数必定不能超过24ppm/K。在一实施例中,第一封装体252优选地具有介于5ppm/K与24ppm/K之间的热膨胀系数。
第一封装体252通过紫外光(ultraviolet)照射该第一材料后固化而形成。在紫外光固化过程中,第一材料可能会发生固化收缩(curing shrinkage)的现象。为了避免固化收缩造成应力产生在接合线230上、第二接合点262上,或者是半导体装置210上,第一材料的固化收缩率必须不大于0.3%。
另外,为了对第二接合点262与接合线230提供良好保护,第一封装体252必须具备一定的硬度。优选地,第一封装体252的萧氏硬度(shore hardness)大于80D,从而提升对物理性破坏或外部应力的耐受度。另外,第一封装体252的玻璃转移温度(glass transitiontemperature)大于85℃,进而确保第一封装体252在多数的情况下都有较低的热膨胀系数。
第二封装体254仅包覆接合线230的第二端、第一接合点264,并且覆盖在半导体装置210的表面区域280上。第二封装体254的萧氏硬度小于第一封装体252。优选地,第二封装体254的萧氏硬度介于35D与70D之间。第二封装体254可为第一接合点264、接合线230的第二端、以及半导体装置210提供绝缘以及隔湿的效果。第一封装体252则可以保护以及强化接合线230以及第二接合点262。
相较于现有技术,第一封装体252的形状小于封装体150,因此第一封装体252有较小的受力面积,因此受到外部应力的影响也比较小。举例来说,由保护材料240所产生的应力便不会直接施加在第一封装体252上;然而,在单一封装体的技术中,保护玻璃产生的应力却会直接施加在封装体上。因此,本发明的第一封装体252较不易破裂。另外,在第一封装体252内部,对接合线230进行拉扯的内部应力也比较少。由于半导体装置210的转角处由具有不同硬度的封装体所覆盖,而非单一封装体,所以凹口效应可被消除。这是因为硬度较低的封装体可以吸收部分的外部应力。
图3为图2所示的电子装置的斜视图。如图所示,第二封装体254不仅覆盖于第一接合点264,以及接合线230的第二端,而且延伸于半导体装置210与保护材料240之间。相似地,第一封装体252不仅覆盖于第二接合点262,以及接合线230的大部分线体,而且延伸于半导体装置210以及电路板220之间。
图4为本发明封装一电子装置的方法的一实施例的流程图。该方法可用来封装如图2所示的电子装置200,或者是任何具有相似结构的电子装置。为了解释上的方便,以下将结合电子装置200进行本发明方法的解释。然而,这并非本发明方法在应用上的限制。
首先,在步骤410中,一第一材料被涂覆在第二接合点262与接合线230上,并进行紫外光固化程序来固化第一材料,形成一第一封装体252,从而封装第二接合点262以及接合线230。详细地说,第一材料一开始被涂覆在第二接合点262以及接合线230的周遭。基于毛细现象,第一材料会沿着接合线230上升,直到充满接合线230下方的空间290。之后,第一材料就固化成第一封装体252。
在步骤420中,第二材料被涂覆在未被第一封装体252覆盖的第一接合点264以及半导体装置210的表面区域280上。同样地,紫外光固化程序被进行,以固化第二材料,形成第二封装体254,从而覆盖第一接合点264、接合线230的第二端以及表面区域280。
总结来说,混合式封装技巧拥有比使用单一封装体的封装更佳的可靠度,对于环境(热与湿气)或外力都有优选耐受度。此外,在接合线一端的接合点上使用较硬的封装体,并且在另一端的接合点上使用较软的封装体,可以形成一种不会脆裂的可靠封装。其中,较硬的封装体可以保护接合线免于遭受物理性破坏,如:外力与热冲击,而较软的封装体则可吸收外部应力,避免凹口效应的发生。
以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。

Claims (22)

1.一种电子装置,包含:
电路板;
半导体装置,设置于该电路板上;
保护材料,设置于该半导体装置上方;
多条接合线,分别连接于该半导体装置上的多个第一连接垫以及该电路板上的多个第二连接垫之间;
第一封装体,由一第一材料所形成,用来封装每一接合线的一部分线体,以及封装多个第二接合点,其中,该些第二接合点由该些接合线与该些第二连接垫连接所形成;以及
第二封装体,由一第二材料所形成,该第二材料不同于该第一材料,该第二封装体用来封装多个第一接合点,其中,该些第一接合点由该些接合线与该些第一连接垫连接所形成。
2.如权利要求1所述的电子装置,其中该第一封装体与该第二封装体有所接触。
3.如权利要求1所述的电子装置,其中该保护材料的一侧面未与该半导体装置的一侧面切齐。
4.如权利要求1所述的电子装置,其中该第一封装体覆盖于该半导体装置的一第一表面上,以及该第二封装体覆盖于该半导体装置的一第二表面的一部分。
5.如权利要求1所述的电子装置,其中该第一封装体在该半导体装置与该电路板之间延伸;以及该第二封装体在该半导体装置与该保护材料之间延伸。
6.如权利要求1所述的电子装置,其中该保护材料为保护玻璃。
7.如权利要求1所述的电子装置,其中该电路板为印刷电路板。
8.如权利要求1所述的电子装置,其中该半导体装置为液晶覆硅(liquid crystal onsilicon,LCoS)装置的硅背板(silicon backplane)或为裸管芯(bare die)。
9.如权利要求1所述的电子装置,其中该第一封装体的萧式硬度(shore hardness)大于该第二封装体的萧式硬度。
10.如权利要求1所述的电子装置,其中该第一封装体的热膨胀系数(coefficient ofthermal expansion,CTE)不大于该些接合线的热膨胀系数。
11.如权利要求1所述的电子装置,其中该第一封装体的热膨胀系数介于5ppm/K与24ppm/K之间。
12.如权利要求1所述的电子装置,其中该第一材料的玻璃转移温度(glasstransition temperature)大于85℃。
13.如权利要求1所述的电子装置,其中该第一材料的固化收缩率(curing shrinkage)不大于0.3%。
14.如权利要求7所述的电子装置,其中该印刷电路板为软性印刷电路板。
15.一种封装电子装置的方法,该电子装置具有电路板以及一半导体装置,该半导体装置设置于该电路板上,并且通过多条接合线与该电路板电连接,一保护材料设置于该半导体装置的上方,该方法包含:
将一第一材料涂覆在该电路板上的多个第二接合点以及每一条接合线的一部分线体上,并且将该第一材料固化,形成一第一封装体,其中,该些第二接合点连接于该些接合线;以及
将一第二材料涂覆在该半导体装置上的多个第一接合点上,并且将该第二材料固化,形成一第二封装体,其中,该些第一接合点连接于该些接合线。
16.如权利要求15所述的方法,其中该第一封装体与该第二封装体有所接触。
17.如权利要求15所述的方法,该第一封装体在该半导体装置与该电路板之间延伸;以及该第二封装体在该半导体装置与该保护材料之间延伸。
18.如权利要求15所述的方法,该第一封装体的萧式硬度大于该第二封装体的萧式硬度。
19.如权利要求15所述的方法,其中第一封装体的热膨胀系数不大于该些接合线的热膨胀系数。
20.如权利要求15所述的方法,其中该第一封装体的热膨胀系数介于5ppm/K与24ppm/K之间。
21.如权利要求15所述的方法,其中该第一材料的玻璃转移温度大于85℃。
22.如权利要求15所述的方法,其中该第一材料的固化收缩率不大于0.3%。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5866953A (en) * 1996-05-24 1999-02-02 Micron Technology, Inc. Packaged die on PCB with heat sink encapsulant
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US5866953A (en) * 1996-05-24 1999-02-02 Micron Technology, Inc. Packaged die on PCB with heat sink encapsulant
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