JPS59158570A - 固体撮像素子用パッケージの製造方法 - Google Patents
固体撮像素子用パッケージの製造方法Info
- Publication number
- JPS59158570A JPS59158570A JP58030733A JP3073383A JPS59158570A JP S59158570 A JPS59158570 A JP S59158570A JP 58030733 A JP58030733 A JP 58030733A JP 3073383 A JP3073383 A JP 3073383A JP S59158570 A JPS59158570 A JP S59158570A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- solid
- frame body
- ceramic molding
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/93—Interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Light Receiving Elements (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58030733A JPS59158570A (ja) | 1983-02-28 | 1983-02-28 | 固体撮像素子用パッケージの製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58030733A JPS59158570A (ja) | 1983-02-28 | 1983-02-28 | 固体撮像素子用パッケージの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59158570A true JPS59158570A (ja) | 1984-09-08 |
JPH0518256B2 JPH0518256B2 (enrdf_load_stackoverflow) | 1993-03-11 |
Family
ID=12311867
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58030733A Granted JPS59158570A (ja) | 1983-02-28 | 1983-02-28 | 固体撮像素子用パッケージの製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59158570A (enrdf_load_stackoverflow) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6196562U (enrdf_load_stackoverflow) * | 1984-11-28 | 1986-06-21 | ||
KR100393050B1 (ko) * | 2001-07-18 | 2003-07-28 | 주식회사 애트랩 | 광센서 및 그 패키징 방법 |
JP2012238687A (ja) * | 2011-05-11 | 2012-12-06 | Sony Corp | 半導体パッケージ、半導体装置の製造方法、および固体撮像装置 |
-
1983
- 1983-02-28 JP JP58030733A patent/JPS59158570A/ja active Granted
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6196562U (enrdf_load_stackoverflow) * | 1984-11-28 | 1986-06-21 | ||
KR100393050B1 (ko) * | 2001-07-18 | 2003-07-28 | 주식회사 애트랩 | 광센서 및 그 패키징 방법 |
JP2012238687A (ja) * | 2011-05-11 | 2012-12-06 | Sony Corp | 半導体パッケージ、半導体装置の製造方法、および固体撮像装置 |
US10483308B2 (en) | 2011-05-11 | 2019-11-19 | Sony Corporation | Reducing thickness of module in solid state imaging device |
Also Published As
Publication number | Publication date |
---|---|
JPH0518256B2 (enrdf_load_stackoverflow) | 1993-03-11 |
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