JPS59155164A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS59155164A
JPS59155164A JP58029724A JP2972483A JPS59155164A JP S59155164 A JPS59155164 A JP S59155164A JP 58029724 A JP58029724 A JP 58029724A JP 2972483 A JP2972483 A JP 2972483A JP S59155164 A JPS59155164 A JP S59155164A
Authority
JP
Japan
Prior art keywords
layer
resist
semiconductor
pattern
resist pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58029724A
Other languages
Japanese (ja)
Inventor
Kenji Maeguchi
前口　賢二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58029724A priority Critical patent/JPS59155164A/en
Priority to US06/575,921 priority patent/US4564583A/en
Publication of JPS59155164A publication Critical patent/JPS59155164A/en
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/095—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having more than one photosensitive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H01L21/76218—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Architecture (AREA)
  • Structural Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent an overlap of well regions by previously forming positive and negative type two layer resist layers, forming a pattern to the first resist layer and implanting first ions and forming a pattern to the second resist layer and implanting second ions. CONSTITUTION:Positive and negative type two layer resist layers 25, 24 are formed onto a semiconductor substrate 22 through an insulating film 23. The two layer resist layers are exposed. The resist layer 25 as an upper layer is developed and a first resist pattern 26 is formed. The ions of a first conductive impurity are implanted while using the pattern 26 as a mask. The pattern 26 is exfoliated. The resist layer 24 as a lower layer is developed, and a second resist pattern 28 is formed. The ions of a second conductive impurity are implanted. The overlap of two well regions 30, 31 can be prevented because the two patterns do not overlap.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体装置の製造方法に関し、特に半導体基
板もしくは絶縁性基板上の半導体層の表面に異種の半導
体領域を並設した相補型ＭＯ８半導体装置（０ＭＯ８）
の製造方法に関する。Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a complementary MO8 semiconductor in which different types of semiconductor regions are arranged side by side on the surface of a semiconductor layer on a semiconductor substrate or an insulating substrate. Equipment (0MO8)
Relating to a manufacturing method.

〔発明つ枝椅吻噴呆〕[Invention and branch chair snout]

従来、０ＭＯ８の製造においては、以下に説明する第１
図（、）〜（ｄ）の如く絶縁性基板上の半導体層表面に
２つの異なる導電型の半導体領域（ウェル領域）を互に
並設することが行なわれている。Conventionally, in the production of 0MO8, the first
As shown in Figures (a) to (d), semiconductor regions (well regions) of two different conductivity types are arranged side by side on the surface of a semiconductor layer on an insulating substrate.

まず、絶縁性基板１上に半導体層２を成長させた後、こ
の半導体層２上にバッファ用の熱酸化Ｍ３を形成する。First, a semiconductor layer 2 is grown on an insulating substrate 1, and then a thermally oxidized buffer M3 is formed on this semiconductor layer 2.

つづいて、この熱酸化膜３上にレジスト層４を形成する
（第１図（、）図示）。Subsequently, a resist layer 4 is formed on this thermal oxide film 3 (as shown in FIG. 1(,)).

次いで、写真蝕刻法（Ｐｈｏｔｏ　Ｅｎｇｒａｖｉｎｇ
Ｐｒｏｃｅｓｓ　）によシル−ウェル領域形成予定部に
対応するレジスト層４を選択的に剥離し、レジス）　Ａ
？ターン５を形成する。次に、このパターン５をマスク
として前記半導体層２表面にｐ型不純物をイオン注入し
、ｐ型の不純物層６を形成する（第１図（ｂ）図示）。Next, Photo Engraving
Process) A.
? Form turn 5. Next, using this pattern 5 as a mask, p-type impurity ions are implanted into the surface of the semiconductor layer 2 to form a p-type impurity layer 6 (as shown in FIG. 1(b)).

ひきつづき、前記レジストパターン５を剥離し、前述と
同様にしてｎ−ウェル領域形成予定部に対応する部分が
開孔したレジスト層４ターン７を形成した後、同１？タ
ーン７をマスクとして前記半導体層２表面にｎ型不純物
をイオン注入してｎ型の不純物層８を形成する（第１図
（Ｃ）図示）。更に、前記・母ターン７を剥離後、熱処
理を施して、ｐ−ウェル領域９、ｎ−ウェル領域１０を
形成する（第１図（ｄ）図示）。Subsequently, the resist pattern 5 was peeled off, and a resist layer 4 turn 7 having holes corresponding to the portions where the n-well region was to be formed was formed in the same manner as described above. Using the turn 7 as a mask, n-type impurity ions are implanted into the surface of the semiconductor layer 2 to form an n-type impurity layer 8 (as shown in FIG. 1C). Furthermore, after peeling off the mother turn 7, a heat treatment is performed to form a p-well region 9 and an n-well region 10 (as shown in FIG. 1(d)).

〔背景技術の問題点〕[Problems with background technology]

しかしながら、前述した製造方法によれば、ｐ−ウェル
領域９とｎ−ウェル領域１０とを夫夫別々のＰＥＰ工程
によるレジストパターン５゜７をマスクとして形成する
ため、これらの前記ウェル領域９，１０を互に自己整合
的に形成することが困難である。このようなことから、
ＰＥＰ工程時の合わせズレ′によって第１図（ｄ）に示
す如くウェル領域９，１０が部分的に重なった領域１ノ
が生じ、この領域１ノでは２度目のｎ型不純物のイオン
注入に起因して表面が損傷し素子特性が劣化する。した
がって、前記レジメトツヤターン５，７を形成する際の
夫々のＰＥＰ工程の合わせズレを考慮したパターン設計
をしなければならず、０ＭＯ８素子の微細化が困難であ
る。However, according to the above-described manufacturing method, since the p-well region 9 and the n-well region 10 are formed using the resist pattern 5.7 as a mask by separate PEP processes, these well regions 9, 10 are It is difficult to form these in a mutually self-consistent manner. From such a thing,
Due to misalignment during the PEP process, a region 1 is created where the well regions 9 and 10 partially overlap, as shown in FIG. This damages the surface and deteriorates the device characteristics. Therefore, it is necessary to design a pattern in consideration of the misalignment of the respective PEP processes when forming the regimen gloss turns 5 and 7, making it difficult to miniaturize the 0MO8 element.

また、前述の如（ＰＥＰ工程を２回行なうため、歩留シ
が低下し製品のコスト高を招く。Further, as mentioned above, since the PEP process is performed twice, the yield rate decreases and the cost of the product increases.

〔発明の目的〕[Purpose of the invention]

本発明は上記事情に鑑みてなされたもので、素子特性の
劣化を回避して素子の微細化を図るとともに、ＰＥＰ工
程を減少して製品コストの低減を図った０ＭＯ８等の半
導体装置の製造方法を提供することを目的とするもので
ある。The present invention has been made in view of the above circumstances, and is a method of manufacturing a semiconductor device such as 0MO8, which avoids deterioration of device characteristics, miniaturizes the device, and reduces the number of PEP steps to reduce product cost. The purpose is to provide the following.

〔発明の概要〕[Summary of the invention]

本発明は、半導体基板もしくは絶縁性基板上の半導体層
上に直接あるいは絶縁膜を介して少なくともポジ型及び
ネガ型からなる２層のレジスト層を形成した後、これら
２層のレジスト層の所定領域に露光し、上層のレジスト
層を現像処理して第１のレジスト層やターンを形成した
後該しジストノやターンをマスクとして前記半導体基板
もしくは半４木層に第１の導電性不純物をイオン注入し
、更に前記レジストパターンを剥離し他方のレジスト層
を現像処理して第２のレジストパターンを形成した後、
該レジメトツヤターンをマスクとして前記半導体基板も
しくは半導体層に第２の導電性不純物をイオン注入する
ことによって、０ＭＯ８素子の微細化並びに製品コスト
の低減を達成できるものである。In the present invention, after forming at least two resist layers of a positive type and a negative type on a semiconductor layer on a semiconductor substrate or an insulating substrate directly or via an insulating film, predetermined areas of these two resist layers are formed. After exposing the upper resist layer to light and developing the upper resist layer to form a first resist layer or turns, a first conductive impurity is ion-implanted into the semiconductor substrate or semi-quadrature layer using the resist layers or turns as a mask. Then, after peeling off the resist pattern and developing the other resist layer to form a second resist pattern,
By ion-implanting a second conductive impurity into the semiconductor substrate or semiconductor layer using the regimen gloss turn as a mask, miniaturization of the 0MO8 element and reduction in product cost can be achieved.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明をＳＯＳ基板を用いた０ＭＯ８の製造に適
用した例について第２図（ａ）〜（ｈ）を参照して説明
する。Hereinafter, an example in which the present invention is applied to the manufacture of 0MO8 using an SOS substrate will be described with reference to FIGS. 2(a) to 2(h).

〔１〕　　まず、絶縁性基板としてのサファイア基板２
ノ上にシリコンをエピタキシャル成長させて半導体層２
２を形成した後、この半導体層。[1] First, a sapphire substrate 2 as an insulating substrate
A semiconductor layer 2 is formed by epitaxially growing silicon on top of the semiconductor layer 2.
After forming 2, this semiconductor layer.

２２上にバッファ用の薄い熱酸化膜２３を形成した。つ
づいて、この熱酸化膜２３上に厚さが夫々４０００Ｘの
ネガレジスト（東京応化工業特製商品名：　ＯＭＲ−８
３）　、ポジレジスト（東京応化工業■裏向品名；　０
ＦＰＲ−７８）を塗布してネガレジスト層２４、ポジレ
ジスト層２５を順次形成　　−した。次いで、Ｐ−ウェ
ル領域形成予定部に対応すポジレジスト層２５、ネガレ
・シスト層２４部分に選択的に紫外線を照射して露光し
た（第２図（、）図示）。この結果、露光されたポジレ
ジストＭ２５では崩壊反応が起とシ、露光されたネガレ
ジスト層２４では架橋反応が起こった。A thin thermal oxide film 23 for buffering was formed on 22. Next, a negative resist with a thickness of 4000X (Tokyo Ohka Kogyo special product name: OMR-8) is applied on the thermal oxide film 23.
3), Positive resist (Tokyo Ohka Kogyo ■Reverse product name; 0
FPR-78) was applied to form a negative resist layer 24 and a positive resist layer 25 in this order. Next, the portions of the positive resist layer 25 and the negative cyst layer 24 corresponding to the portion where the P-well region was to be formed were selectively irradiated with ultraviolet rays and exposed (as shown in FIG. 2(a)). As a result, a collapse reaction occurred in the exposed positive resist layer M25, and a crosslinking reaction occurred in the exposed negative resist layer 24.

更に、ポジレジスト用の現像液を用いて露光されたポジ
レジスト層２５を溶解除去し、第１のレジストパターン
としてのｐ−ウェル領域形成予定部に対応する部分が開
孔された？ジレジストノ母ターフ２６を形成した。この
後、このノぐターン２６をマスクとして前記半導体層２
２表面にｐ型不純物例えばポロンをイオン注入し、ｐ型
不純物層２７を形成した（第２図（ｂ）図示）。Furthermore, the exposed positive resist layer 25 was dissolved and removed using a positive resist developer, and a hole was opened in a portion corresponding to a portion where a p-well region was to be formed as a first resist pattern. A diresist mother turf 26 was formed. After that, using this notch turn 26 as a mask, the semiconductor layer 2 is
A p-type impurity layer 27 was formed by ion-implanting a p-type impurity such as poron into the surface of the substrate 2 (as shown in FIG. 2(b)).

〔１！〕　　次に、ポジレジストパターン２６を剥離後
、ネガレジスト用の現像液を用いて露光されないネガレ
ジスト層２６を溶解除去し、ポジレジストパターン２６
とは逆パターンのネガレジストツヤターン（第２のレジ
ストノやターン）２８を形成した。つづいて、このネガ
レジストパターン２８をマスクとして前記半導体層２２
表面にｎ型不純物例えばリンをイオン注入してｎ型不純
物層２９を形成した（第２図（Ｃ）図示）。次いで、ネ
ガレジストツヤターン２８を剥離した後、窒素雰囲気で
１０００℃、１時間熱処理を施して前記不純物２７．２
９を活性化し、ｐ−ウェル領域３０．ｎ−ウェル領域３
ノを夫々形成した（第２図（ｄ）図示）。更に、前記熱
酸化膜２３を除去し、全面に厚い酸化膜（図示せず）を
形成した後、写真蝕刻法によシ前記半導体領域３０゜３
ノの素子領域形成予定部に対応する酸化膜を選択的に除
去し、フィールド領域３２を形成した（第２図（、）図
示）。この後、熱処理を施して露出するウェル領域３０
．３１表面に薄い酸化膜３３を形成し、更に全面に多結
晶シリコン層３４を形成した（第２図（ｆ）図示）。[1! ] Next, after peeling off the positive resist pattern 26, the negative resist layer 26 that is not exposed to light is dissolved and removed using a negative resist developer, and the positive resist pattern 26 is removed.
A negative resist glossy turn (second resist pattern) 28 having a reverse pattern was formed. Next, using this negative resist pattern 28 as a mask, the semiconductor layer 22 is
An n-type impurity layer 29 was formed by ion-implanting an n-type impurity such as phosphorus into the surface (as shown in FIG. 2C). Next, after peeling off the negative resist gloss turn 28, heat treatment was performed at 1000° C. for 1 hour in a nitrogen atmosphere to remove the impurity 27.2.
9 and p-well region 30. n-well region 3
(Illustrated in FIG. 2(d)). Furthermore, after removing the thermal oxide film 23 and forming a thick oxide film (not shown) on the entire surface, the semiconductor region 30° 3 is etched by photolithography.
The oxide film corresponding to the portion where the element region is to be formed was selectively removed to form a field region 32 (as shown in FIG. 2(a)). After this, the well region 30 is subjected to heat treatment and exposed.
．． A thin oxide film 33 was formed on the surface of 31, and a polycrystalline silicon layer 34 was further formed on the entire surface (as shown in FIG. 2(f)).

［：ｉｉｉ：ｌ　　次に、この多結晶シリコン層３４を
パターニングし前記ｐ−ウェル領域３０、ｎ−ウェル領
域３）上に酸化膜３３を介してダート電極３５１．３５
．を形成した後、これらダート電極３５１．３５２をマ
スクとして前記酸化膜３３を選択的にエツチング除去し
ダート絶縁膜３６１゜３６２を形成した。つづいて、写
真蝕刻法によシｎ−ウェル領域３ノ側を覆うレジストパ
ターン（図示せず）を形成した後、同・やターン、ダー
ト電極３５１ｔ３５＊及びフィールド領域３２をマスク
としてｐ−ウェル領域３０表面に例えばリンをイオン注
入した。次いで、前記レジストパターンを剥離後、写真
蝕刻法によシ全面にｐ−ウェル領域３０側を覆うレジス
ト・母ターン（図示せず）を形成した後、同ノ’？ター
ン、ダート電極３５１．３５．及びフィールド領域３２
をマスクとしてｎ−ウェル領域３１表面に例えばポロン
をイオン注入した。更に、前記レジメ）　ノ４ターンを
剥離後、熱処理を施して、ｐ−ウェル領域３０に訂型の
ソース、ドレイン領域３７１＊３８１を形成すると共に
、ｎ−ウニルミＡ域Ｊ７Ｋｐ＋型のソース、ドレイン領
域３７２゜３８２を夫々形成した。この後、全面に層間
絶縁膜３９を形成した（第２図（ｇ）図示）。更に、前
記各ソース、ドレイン領域３７１　．３７２　　。[:iii:l Next, this polycrystalline silicon layer 34 is patterned to form dirt electrodes 351.35 on the p-well region 30 and n-well region 3) via the oxide film 33.
．． After forming these dirt electrodes 351 and 352 as a mask, the oxide film 33 was selectively etched away to form dirt insulating films 361 and 362. Subsequently, after forming a resist pattern (not shown) covering the side of the thin N-well region 3 by photolithography, the p-well region is For example, phosphorus was ion-implanted onto the surface of No. 30. Next, after peeling off the resist pattern, a resist/mother turn (not shown) covering the p-well region 30 side is formed on the entire surface by photolithography, and then the same pattern is removed. Turn, dart electrode 351.35. and field area 32
For example, poron ions were implanted into the surface of the n-well region 31 using as a mask. Furthermore, after peeling off the 4 turns of the above regimen, heat treatment is performed to form revised source and drain regions 371 * 381 in the p-well region 30, and to form source and drain regions of the n-uniluminum A region J7Kp+ type. 372° and 382 were formed, respectively. Thereafter, an interlayer insulating film 39 was formed on the entire surface (as shown in FIG. 2(g)). Further, each of the source and drain regions 371 . 372.

３８１１３８２の一部に対応する層間絶縁膜３９をエツ
チング除去しコンタクトホール４０・・・を形成した後
、これらコンタクトホール４０・・・にＡｌ配線４ノ・
・・を形成して０ＭＯ８を製造した（第２図（ｈ）図示
）。After etching and removing the interlayer insulating film 39 corresponding to a part of 3811382 and forming contact holes 40..., Al wiring 4 holes are formed in these contact holes 40...
... was formed to produce 0MO8 (as shown in FIG. 2(h)).

しかして、本発明によれば、サファイア基板２ノ上の半
導体層２２上に熱酸化膜２３を介して順次積層したネガ
レジスト層２４、ポジレジスト層２５を１回の露光と２
回の現像処理で互に反転したｐ型不純物層２７形成用の
ポジレジストパターン２６とｎ型不純物層２９形成用の
ネガレジストパターン２８とを形成できる。つまシ、ｐ
−ウェル領域３０となるｎ型不純物層２７とｎ−ウェル
領域３Ｊとなるｎ型不純物層２９とを互いに自己整合的
に形成すること力ヨできる。したがって、従来の如く、
ｎ−ウェル領域とｐ−ウェル領域との重なりに起因して
素子特性が劣化することを回避できるとともに、２回の
ＰＥＰ工程に起因する合わせずれを考慮することなく微
細なＣＭＯ８素子を形成できる。According to the present invention, the negative resist layer 24 and the positive resist layer 25, which are sequentially laminated on the semiconductor layer 22 on the sapphire substrate 2 via the thermal oxide film 23, are exposed once and then exposed twice.
A positive resist pattern 26 for forming the p-type impurity layer 27 and a negative resist pattern 28 for forming the n-type impurity layer 29, which are reversed from each other, can be formed in one development process. Tsumashi, p
- The n-type impurity layer 27 that will become the well region 30 and the n-type impurity layer 29 that will become the n-well region 3J can be formed in a mutually self-aligned manner. Therefore, as before,
Deterioration of device characteristics due to overlap between the n-well region and the p-well region can be avoided, and a fine CMO8 device can be formed without considering misalignment caused by two PEP steps.

また、前述の如く、ｐ型不純物領域２２形成用のポジレ
ジス）／ｆターン２６とｎ型不純物領域２９形成用のネ
ガレジストハターン２８が１回の露光と２回の現像処理
で済むため、歩止シを向上させて製品コストの低減を図
ることができる。In addition, as described above, since the positive resist (f-turn 26 for forming the p-type impurity region 22) and the negative resist (f-turn) 28 for forming the n-type impurity region 29 only require one exposure and two development processes, the yield can be reduced. It is possible to improve performance and reduce product costs.

なお、上記実施例ではネガレジスト層と号？ジレジスト
層を順次積層したが、これに限らず、例えばこれらレジ
スト層間にス／’Ｐツタ５ＩＯ２膜等の光を透過する物
質を介在させ、ポジレジスト層のエツチング時にネガレ
ジスト層がエツチングされないようにしてもよい。In addition, in the above embodiment, what is called a negative resist layer? Although the di-resist layers are sequentially laminated, the present invention is not limited to this. For example, a material that transmits light, such as a 5IO2 film, may be interposed between these resist layers to prevent the negative resist layer from being etched when the positive resist layer is etched. It's okay.

上記実施例では、サファイア基板上の半導体層上に熱酸
化膜を介してネガレジスト層、ポジレジスト層を順次形
成したが、熱酸化膜はレジスト層からの汚染を防ぐため
に形成したものであシ、これに限らず、半導体層上に直
接レジスト層を形成しそもよい。In the above example, a negative resist layer and a positive resist layer were sequentially formed on a semiconductor layer on a sapphire substrate via a thermal oxide film, but the thermal oxide film was formed to prevent contamination from the resist layer. However, the present invention is not limited to this, and it is also possible to form a resist layer directly on the semiconductor layer.

上記実施例では、ＳＯ８基板を用いて０ＭＯ８を形成す
る場合について述べたが、これに限らず、例えばｐ型の
Ｓｔ基板にｐ−ウェル領域、ｎ−ウェル領域を形成した
０ＭＯ８を形成してもよい。即ち、第３図（、）に示す
如くｐ型のＳｉ基板５１上に熱酸化膜５２を介してネガ
レジスト層５３、ポジレジスト層５４を順次形成した後
、上記実施例と同様な方法によシ第３図（ｂ）に示す如
く、前記基板５１表面にｐ−ウェル領域５５、ｎ−ウェ
ル領域５６を形成する。In the above embodiment, a case was described in which an 0MO8 is formed using an SO8 substrate, but the invention is not limited to this. For example, an 0MO8 in which a p-well region and an n-well region are formed on a p-type St substrate may also be formed. good. That is, after forming a negative resist layer 53 and a positive resist layer 54 in sequence on a p-type Si substrate 51 via a thermal oxide film 52 as shown in FIG. As shown in FIG. 3(b), a p-well region 55 and an n-well region 56 are formed on the surface of the substrate 51.

上記実施例では、パターンをポジレジスト層、ネガレジ
スト層に露光する方法として紫外線照射を行なったが、
これに限らず、短波長紫外線、Ｘ線、電子線、イオンビ
ーム等を用いることができる。なお、ポジレジスト層、
ネガレジスト層はそれらの露光源あるいは照射源に合わ
せて適宜選択できる。In the above example, ultraviolet irradiation was used as a method of exposing the pattern to the positive resist layer and the negative resist layer.
The present invention is not limited to this, and short wavelength ultraviolet rays, X-rays, electron beams, ion beams, etc. can be used. In addition, the positive resist layer,
The negative resist layer can be appropriately selected depending on the exposure source or irradiation source.

上記実施例では、ｐ−ウェル領域とｎ−ウェル領域とを
互に自己整合的に形成する場合について述べたが、これ
に限らず、互に同一導電型であってしかも不純物濃度が
異なる２つのウェル領域を形成する場合についても同様
に適用できる。In the above embodiment, the case where the p-well region and the n-well region are formed in a self-aligned manner with each other has been described, but the invention is not limited to this. The same applies to the case of forming a well region.

〔発明の効果〕〔Effect of the invention〕

以上詳述した如く本発明によれば、素子の微細化並びに
製品コストの低減を達成できる０ＭＯ８等の半導体装置
の製造方法を提供できるものである。As detailed above, according to the present invention, it is possible to provide a method of manufacturing a semiconductor device such as 0MO8, which can achieve miniaturization of elements and reduction of product cost.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は（ａ）〜（ｄ）は従来の０ＭＯ８の製造工程の
一部を示す断面図、第２図は（、）〜（ｈ）は本発明の
一実施例を示す０ＭＯ８の製造方法を工程順に示す断面
図、第３図（ａ）、（ｂ）は本発明の他の実施例を示す
０ＭＯ８の製造工程の一部を示す断面図である。 ２ノ・・・サファイア基板（絶縁性基板）、２２・・・
半導体層、２３，５２・・・熱酸化膜、２４゜５３・・
・ネガレジスト層、２５，５４・・・ポジレジスト層、
２６・・・ポジレジストパターン（第１のレジストパタ
ーン）、２７・・・ｐ型不純物層、２８・・・ネガレジ
ストハターン（第２のレジストパターン）、２９・・・
ｎ型不純物層、３０．５５・・・ｐ−ウェル領域、３１
．５６・・・ｎ−ウェル領域、３２・・・フィールド領
域、３３・・・薄い酸化膜、３４・・・多結晶シリコン
層、３５１　．３５．・・・ダート電極、３６ｘ　　、
　３６．　・’ｌ’ｌトート膜、３−７１゜３７１・・
・ソース領域、３Ｂ、、３８．・・・ドレイン領域、３
９・・・層間絶縁膜、４０・・・コンタクトホール、４
ノ・・・ＡＩ配線、５１・・・ｐ型の８１基板。Fig. 1 (a) to (d) are cross-sectional views showing a part of the conventional manufacturing process of 0MO8, and Fig. 2 (,) to (h) are sectional views showing an example of the manufacturing method of 0MO8 of the present invention. FIGS. 3(a) and 3(b) are sectional views showing a part of the manufacturing process of 0MO8 showing another embodiment of the present invention. 2... Sapphire substrate (insulating substrate), 22...
Semiconductor layer, 23, 52... thermal oxide film, 24°53...
- Negative resist layer, 25, 54... positive resist layer,
26... Positive resist pattern (first resist pattern), 27... P-type impurity layer, 28... Negative resist pattern (second resist pattern), 29...
n-type impurity layer, 30.55...p-well region, 31
．． 56... N-well region, 32... Field region, 33... Thin oxide film, 34... Polycrystalline silicon layer, 351. 35. ...Dart electrode, 36x,
36.・'l'l tote membrane, 3-71°371...
- Source area, 3B, 38. ...Drain region, 3
9... Interlayer insulating film, 40... Contact hole, 4
No...AI wiring, 51...p-type 81 board.

Claims (3)

【特許請求の範囲】[Claims] （１）　　半導体基板もしくは絶縁性基板上の半導体層
上に直接あるいは絶縁膜を介して少なくともポジ型及び
ネガ型からなる２層のレジスト層を形成する工程と、こ
れら２層のレジスト層の所定領域を露光する工程と、上
層のレジスト層を現像処理して第１のレジス）パターン
を形成した後、該レジストパターンをマスクとして前記
半導体基板もしくは半導体層に第１の導電性不純物をイ
オン注入する工程と、前記レジストパターンを剥離し下
層のレジスト層を現像処理して第２のレジストパターン
を形成した後、該レジストパターンをマスクとして前記
半導体基板もしくは半導体層に第２の導電性不純物をイ
オン注入する工程とを具備することを特徴とする半導体
装置の製造方法。(1) A step of forming at least two resist layers of a positive type and a negative type on a semiconductor layer on a semiconductor substrate or an insulating substrate directly or via an insulating film, and predetermined areas of these two resist layers. and after developing the upper resist layer to form a first resist pattern, ion-implanting a first conductive impurity into the semiconductor substrate or semiconductor layer using the resist pattern as a mask. After peeling off the resist pattern and developing the underlying resist layer to form a second resist pattern, a second conductive impurity is ion-implanted into the semiconductor substrate or semiconductor layer using the resist pattern as a mask. A method for manufacturing a semiconductor device, comprising the steps of: （２）半導体基板もしくは絶縁性基板上の半導体層上に
絶縁膜を介してポジ型レジスト層を設けた後、更に５１
０２膜を介してネガ型レジスト層を設けたことを特徴と
する特許請求”の範囲第１項記載の半導体装置の製造方
法。(2) After providing a positive resist layer on the semiconductor layer on the semiconductor substrate or the insulating substrate via the insulating film, further 51
A method for manufacturing a semiconductor device according to claim 1, characterized in that a negative resist layer is provided through a 02 film. （３）上層のレジスト層を現像処理して第１の半導体領
域形成予定部に対応する部分が開孔された第１のレジス
トパターンを形成する工程と、このレジストパターンを
マスクとして半導体基板もしくは半導体層に第１導電型
の不純物をイオン注入して不純物層を形成する工程と、
前記レジストパターンを除去し下層のレジスト層を現像
処理して第２のレジス）　ｔ＋ターンを形成した後、該
レジストパターンをマスクとして前記半導体基板もしく
は半導体層に第２導電型の不純物をイオン注入し不純物
層を形成する工程とを具備することを特徴とする特許請
求の範囲第１項記載の半導体装置の製造方法。(3) A step of developing the upper resist layer to form a first resist pattern in which a hole is formed in a portion corresponding to a portion where the first semiconductor region is to be formed, and using this resist pattern as a mask to form a semiconductor substrate or a semiconductor. forming an impurity layer by ion-implanting a first conductivity type impurity into the layer;
After removing the resist pattern and developing the underlying resist layer to form a T+ turn, ions of a second conductivity type impurity are implanted into the semiconductor substrate or semiconductor layer using the resist pattern as a mask. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming an impurity layer.
JP58029724A 1983-02-07 1983-02-24 Manufacture of semiconductor device Pending JPS59155164A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP58029724A JPS59155164A (en) 1983-02-24 1983-02-24 Manufacture of semiconductor device
US06/575,921 US4564583A (en) 1983-02-07 1984-02-01 Method for manufacturing a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58029724A JPS59155164A (en) 1983-02-24 1983-02-24 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS59155164A true JPS59155164A (en) 1984-09-04

Family

ID=12284053

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58029724A Pending JPS59155164A (en) 1983-02-07 1983-02-24 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59155164A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04263467A (en) * 1991-02-19 1992-09-18 Fujitsu Ltd Semiconductor device
KR19980030837A (en) * 1996-10-30 1998-07-25 김영환 CMOS transistor and its manufacturing method
WO2014147185A1 (en) * 2013-03-20 2014-09-25 Mpo Energy Method for doping silicon sheets

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04263467A (en) * 1991-02-19 1992-09-18 Fujitsu Ltd Semiconductor device
KR19980030837A (en) * 1996-10-30 1998-07-25 김영환 CMOS transistor and its manufacturing method
WO2014147185A1 (en) * 2013-03-20 2014-09-25 Mpo Energy Method for doping silicon sheets
FR3003687A1 (en) * 2013-03-20 2014-09-26 Mpo Energy METHOD FOR DOPING SILICON PLATES
EP2976782A1 (en) * 2013-03-20 2016-01-27 Ion Beam Services Method for doping silicon sheets
CN105580110A (en) * 2013-03-20 2016-05-11 离子射线服务公司 Method for doping silicon sheets

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