JPS6015155B2 - Manufacturing method of semiconductor device - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a method for manufacturing a semiconductor device having a three-dimensional multilayer structure. In recent years, technology has been developed to vapor-phase epitaxially grow insulators such as single crystal alumina (Yama 203 Sapphire) and single crystal magnesia spinel (M-Al203) on a single crystal semiconductor substrate, and to grow a single crystal semiconductor layer on top of this using impurity growth. has been developed.
. By applying this technology, it is possible to manufacture semiconductor devices with new structures and simplify the manufacturing process. The present invention makes it possible to easily obtain a semiconductor device having a three-dimensional multilayer structure by using a semiconductor wafer in which a single crystal insulating layer and a single crystal semiconductor layer are sequentially epitaxially grown on a single crystal semiconductor substrate. This will be explained in detail below. The present invention provides a single crystal semiconductor substrate with a certain type of M.
An IS transistor, for example, an n-channel transistor is formed, and a semiconductor layer separated by a single crystal insulating layer contains a different type of M that cannot be directly formed on the semiconductor substrate.
The basis is to form IS transistors, for example p-channel transistors. Next, with reference to FIGS. 1 to 8, a case of manufacturing a complementary MIS field effect semiconductor device (C-MIS), which is an embodiment, will be described. See Figure 1 {11 AI2 on p-type silicon semiconductor substrate 1
A single crystal insulating layer 2 such as 03 or MgON203 is grown epitaxially in the vapor phase, an n-type silicon semiconductor layer 3 is epitaxially grown thereon, and a field silicon dioxide insulating film 4 formed by, for example, a thermal oxidation method is further grown. Prepare the formed semiconductor wafer. Refer to Fig. 2 (2) Pattern the insulating film 4 by applying normal photo phosphorography technique to form a closed opening 4A in the element forming area. {3- By applying normal photo phosphorography technique The semiconductor layer 3 is patterned to form a closed opening 3A. At this time, as an etching solution, for example, hydrofluoric acid + nitric acid or an alkaline solution may be used. See FIG. 3 [4] The insulating layer 2 is etched using a mask to complete the Sekiguchi 3A.The etching solution used at this time is at a temperature of 150 to 25°C.
0

[00] sulfuric acid, a mixture of sulfuric acid and phosphoric acid, etc. may be used. See Figure 4 '5} By selecting an appropriate technique such as a thermal oxidation method, a sputtering method, or a chemical vapor deposition method, a thickness of, for example, 300 to 1000
[A] A silicon dioxide insulating film 4' is formed. See FIG. 5 [61] Polycrystalline silicon layer 5 is grown by applying, for example, chemical vapor deposition. Refer to Fig. 6 {7} Photo resist film 6 is applied to the entire area except inside opening 3A.
form. '8} The polycrystalline silicon layer 5 present in the closed opening 3A is patterned to form a silicon gate 50n, and the insulating film 4' is patterned using this as a mask to form a gate insulating film 4Gn. '9- Diffusion of n-type impurities is performed to form source region 7n and drain region 8n. In this case, n-type impurity diffusion is performed by ion implantation, but between the above step and this step {8--, the photoresist film 6 is
For example, if the silicon dioxide film is replaced with a silicon dioxide film of about 2,000 to 5,000 [A], normal thermal diffusion is also possible, and the same applies to the photoresist film 11 shown in FIG. Refer to FIG. 7. The opening □3A is covered with a photoresist film 11, and the photoresist film 6 is removed. (11) Apply normal photolithography technology to pattern the polycrystalline silicon film 5 on the semiconductor layer 3 to form a silicon gate 50P, and use this as a mask to pattern the insulating film 4' to form the gate. An insulating film 4GP is formed. (12) Perform p-type impurity diffusion to form source region 9p and drain region 10p. See Figure 8 (13) Photo. After removing the resist film 11,
The insulating film, electrodes, and wiring may be formed using conventional techniques. When forming electrodes and wiring, the wiring that connects the n-channel transistor part and the p-channel transistor part must pass through a step, but the part that spans the step must be made especially wide, or the n-channel - It is possible to make the insulating film in the transistor part slightly thicker to reduce the step difference. As can be seen from the above explanation, according to the method for manufacturing a semiconductor device of the present invention, an opening □ is selectively formed in a single crystal insulating layer and a semiconductor layer epitaxially grown on a semiconductor substrate, and the inside of the opening □ is selectively formed. A first MIS transistor is formed on the semiconductor substrate exposed to
It forms an S transistor, for example, a C/MI
When manufacturing S, there is no need to create a wafer on the semiconductor substrate, which simplifies the manufacturing process of the device.Moreover, when viewed in plan, the resulting semiconductor device has a first MIS transistor and a second MIS transistor. Since it is formed in contact with the transistor and does not require any margin between them, it is effective for high integration. The impurity concentrations of the semiconductor substrate and semiconductor layer can be freely selected. In the above embodiments, an n-channel device is formed on the semiconductor substrate and a p-channel device is formed on the semiconductor layer, but this may be reversed, and the order in which they are formed may be formed first.

[Brief explanation of the drawing]

FIGS. 1 to 8 are explanatory diagrams of steps in manufacturing an embodiment of the present invention. In the figure, 1 is a substrate, 2 is an insulating layer, 3 is a semiconductor layer, 4 is a
is an insulating film, 40n, 4Gp is a gate insulating film, 5Gn, 5
Gp is a silicon gate, 7n, 9p are source regions, 8
n and 10p are drain regions. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] 1. A step of epitaxially growing a single crystal insulating layer on a single crystal insulating layer formed on a semiconductor substrate, then forming an opening in the single crystal semiconductor layer, and then growing the single crystal using the single crystal semiconductor layer as a mask. selectively removing the insulating layer to expose a part of the surface of the semiconductor substrate, then forming a gate insulating film and a gate electrode on the exposed semiconductor substrate, and then using the gate electrode as a mask to expose a part of the surface of the semiconductor substrate; Introducing impurities into a semiconductor substrate to form an impurity region constituting a first MIS transistor, forming a mask in the opening, and then forming a gate insulating film and a gate electrode on the single crystal semiconductor layer. The method is characterized by including a step of subsequently introducing impurities into the single crystal semiconductor layer using the gate electrode as a mask to form an impurity region constituting a second MIS transistor in any order. A method for manufacturing a semiconductor device.