JPH0334373A - Mos type transistor - Google Patents

Abstract

PURPOSE:To obtain a transistor which can be made large in effective channel width per plane area and is large in current gain by a method wherein a recess is provided to the surface of a semiconductor substrate sandwiched between a source region and a drain region. CONSTITUTION:A recess 105 is formed on the surface of a region surrounded by an element isolating region 102 (field oxide film) formed on the primary face of a single crystal silicon substrate 101, where the recess 105 ranges from a source region 103 through a drain region 104. A gate oxide film 106 is formed on the surface of the recess 105, and a polycrystalline silicon gate electrode 107 is built thereon. As a gate electrode is provided traversing the surface of a recess, an effective channel width can be increased and consequently a transistor of this design can be improved in current gain.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to MOS transistors, particularly those with high integration,
This invention relates to a MOS transistor suitable for high-speed operation.

[Conventional technology]

A conventional MOS transistor is shown in FIG.

A conventional MOS transistor is formed in a region surrounded by an element isolation region 402 formed on one main surface of a silicon substrate 401, and a gate is formed in a flat part sandwiched between a source region 403 and a drain region 404. Oxide film 40
5 and a polycrystalline silicon gate electrode 406 are stacked.

[Problem to be solved by the invention]

Since the above-described conventional MOS transistor is formed on a flat semiconductor substrate surface, the channel width W must be increased in order to obtain a transistor with a large current gain. On the other hand, in order to increase the degree of integration of integrated circuits, the dimension of the channel width W must also decrease,
The conventional structure has the disadvantage that it is difficult to improve the performance of the transistor.

[Means to solve the problem]

The MOS transistor of the present invention has one or more recesses in the surface portion of the semiconductor substrate sandwiched between the source region and the drain region.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1(a) is a layout diagram showing an embodiment of the present invention;
FIG. 1(b) is a longitudinal sectional view of the semiconductor chip taken along the line A--A in FIG. 1(a).

A recess 105 extending from a source region 103 to a drain region 104 is formed on the surface of a region surrounded by an element isolation region 102 (field oxide film) formed on the entire surface of a single crystal silicon substrate 101 . A gate oxide film 106 is formed on the surface of this four part 105, and a polycrystalline silicon gate electrode 107 is formed thereon.

A manufacturing method according to an embodiment of the present invention will be explained with reference to FIG. After forming a thermal oxide film 202 of about 500 A on the surface of a single crystal silicon substrate 201, an element isolation region 203 is formed by a widely used selective oxidation method (FIG. 2(a)). Next, silicon nitride M2 with a thickness of about 0.1 μm
After growing O4 (Fig. 2(b)) and patterning using normal photolithography, silicon nitride 120 is grown using reactive ion etching.
4 is removed to form an opening 505 (FIG. 2(C))
. Next, a thermal oxide film 2 with a thickness of about 160 μm is formed in the opening 205.
06 (Fig. 2 (d)). After completely removing the thermal oxide film 206 using diluted HF solution (Fig. 2 (e)
), the silicon nitride film 204 is removed using phosphoric acid, and the oxide film 202 is further removed (FIG. 2(f)).

A second gate oxide film 207 with a thickness of about 20 OA is formed.
(Fig. (g)), 0.5 μm using the vapor phase growth method.
After depositing a polycrystalline silicon gate 208 of about 100 mL, a MOS type transistor is formed through a normal transistor manufacturing process (FIG. 2(g)).

FIGS. 3(a) to 3(d) are longitudinal cross-sectional views for explaining another manufacturing method of one embodiment.

In this example, thermal oxidation for forming the concave portion of the transistor portion and thermal oxidation for forming the element isolation region 304 are simultaneously performed using a selective oxidation method to form a thermal oxide film with a thickness of about 1 μm. Figure 3 <a>>.

Next, after growing a silicon nitride film 305 with a thickness of about 0.1 μm (FIG. 3(b)), buttering is performed to leave the silicon nitride film 305 on the thermal oxide film used for element isolation 1304. Then, only the silicon nitride film on the surface of the transistor region is removed (Fig. 3 (C)).Next, after removing the thermal oxide films 302 and 303 using diluted HF solution, the silicon nitride film is removed using phosphoric acid. 305 (Figure 3 (
d)).

The steps after the above steps are the same as the manufacturing steps of the previous example. Since this manufacturing method requires only one selective oxidation step, it has the advantage of shortening the construction period.

Since the gate electrode is provided across the surface of the recess, the effective channel width increases and the current gain can be improved.0 For example, when using a recess with a depth of 0.5 μm 2)! When the groove is formed, the effective channel width increases by about 20% compared to the case where the groove is not formed, and as a result, the 2 current gain also increases by about 20%.

〔Effect of the invention〕

As explained above, the present invention can increase the effective channel width per plane area by providing four parts on the surface of the semiconductor substrate sandwiched between the source region and the drain region, thereby realizing a transistor with high current gain. effective.

[Brief explanation of drawings]

FIG. 1(a) is a layout diagram showing an embodiment of the present invention;
FIG. 1(b) is a longitudinal cross-sectional view of the semiconductor chip cut along the line A-A in FIG. 1(a), and FIGS. 2(a) to (h) illustrate the manufacturing method of one embodiment. Longitudinal cross-sectional view for Figure 3
a) to (d) are longitudinal sectional views for explaining another manufacturing method of one embodiment, FIG. 4(a) is a layout diagram showing a conventional MOS transistor, and FIG. 4(b) is a fourth It is a vertical cross-sectional view of the semiconductor chip cut along the line A-A in Figure (a).・
- Drain region, 202, 206. -303...Thermal oxide film, 102.20'3,304,402...Element isolation region, 106,207,405...Gate oxide film, 107,208,406...Polycrystalline silicon gate, 204, 305...Silicon nitride film, 205...
Opening, 105... recess.

Claims (1)

[Claims] A MOS transistor characterized by having one or more recesses in the surface of a semiconductor substrate sandwiched between a source region and a drain region.