JPH0226061A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce contamination of a gate oxide film by performing vapor deposition of a polysilicon film two times, namely, directly after growing the gate oxide film and directly before forming a gate electrode and an emitter electrode. CONSTITUTION:After forming a collector wall layer 9, a thin silicon oxide film 19 to become a gate oxide film is formed, later, a polysilicon film 11 is made to continuously grow. Then, the polysilicon film 11 is made to grow, then being selectively etched to simultaneously form a gate electrode 15 of a MOS transistor, an emitter electrode 16 and a collector electrode 17 coming in contact with an emitter region 13 and a collector contact region 14 of an NPN transistor. In this way, vapor deposition of the polysilicon film 11 for forming the gate electrode 15 of the MOS transistor and the emitter electrode 13 of the NPN transistor is performed divided in two times, namely, directly after growing the gate oxide film 10 and directly before forming the gate electrode 15 and the emitter electrode 13. Thereby, a problem of contamination of gate oxide film is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit in which a bipolar transistor and a MOS (MOS) transistor are formed within the same semiconductor substrate.

Conventional technology BL-CM that integrates bipolar transistors and CMOS (complementary MO3) transistors on the same semiconductor substrate
In O8 technology, a technology has been announced that employs a so-called polysilicon emitter structure in which the emitter electrode is directly drawn out from polysilicon in order to increase the speed of NPN transistors. In Bi-CMOS technology, when the above polysilicon emitter structure is adopted, the formation of the polysilicon emitter electrode and the formation of the polysilicon gate electrode of the CMOS transistor are usually performed separately, that is, using different masks. . If an attempt is made to simultaneously form these emitter electrodes and gate electrodes using the same polysilicon film, the gate oxide film in the emitter region must be selectively opened after the gate oxide film is grown but before the polysilicon growth is performed. Therefore, there was a risk that the gate oxide film would be contaminated.

Problem to be Solved by the Invention In the conventional manufacturing method such as C(7), two layers of polysilicon films and two types of masks are required to form the gate electrode of the CMOS transistor and the emitter electrode of the NPN transistor. , there was a problem that the process became complicated. Furthermore, when attempting to form the gate electrode and the emitter electrode at the same time, there is a problem in that the gate oxide film is highly likely to be contaminated by the selective opening process of the gate oxide film.

The present invention solves the above-mentioned problems, and is a method for manufacturing a semiconductor integrated circuit that allows the gate electrode of a MOS transistor and the emitter electrode of an NPN transistor to be formed simultaneously using a method that is less likely to contaminate the gate oxide film. The purpose is to provide the following.

Means for Solving the Problems In order to solve the above problems, the present invention provides a step of continuously growing a polycrystalline silicon film after growing a gate oxide film, and a step of continuously growing a polycrystalline silicon film after growing a gate oxide film.
N) selectively removing the polycrystalline silicon film on the regions where the emitter, base and collector contacts of the transistor are planned to be formed, and selectively removing the gate oxide film on the regions where the emitter and collector contacts are planned to be formed. and a step of growing a polycrystalline silicon film after forming the emitter, base and collector contact regions;
The method includes a step of simultaneously forming a gate electrode of a MOS transistor and an emitter electrode and a collector electrode of an NPN transistor by selectively etching the polycrystalline silicon film.

Operation With the above configuration, the gate electrode of the MOS transistor and the N
Since the polysilicon film for forming the emitter electrode of the NPN transistor is deposited in two layers, immediately after the growth of the gate oxide film and immediately before the formation of the gate and emitter electrodes, it is possible to form the emitter region of the NPN transistor. The gate electrode of a MOS transistor and the emitter electrode of an NPN transistor can be formed simultaneously without worrying about the possibility of contamination of the gate oxide film due to the selective opening process that is sometimes performed, simplifying the process. be done.

Example An embodiment of the present invention will be described below based on the drawings.

FIG. 1 shows a process flowchart of a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention, and the manufacturing method will be explained using this. First, as shown in FIG. 1 Ca), on a p-type wheel crystal silicon substrate 1 on which n-type buried regions 2 and 21 and n-type buried regions 3 and 31 are selectively formed, a resistivity of 1 to 5 Ω is applied. My n-type silicon epitaxial layer 4 is formed, and an N-well region 5 connected to this is formed on the n-type buried regions 2 and 21 by diffusion of n-type impurities, and an n-type buried region 3 is formed by diffusion of n-type impurities. A p-type isolation region 6 connected to this is formed on the top, and a P-type isolation region 6 is formed on the n-type buried region 31.
A well region 7 is formed. Furthermore, a thick silicon oxide film is grown by selective oxidation to form element isolation regions 8.

Next, as shown in FIG. 1), after forming a collector all layer 9 of an NPN transistor by diffusing n-type impurities, a thin silicon oxide film 10 that will become a gate oxide film is formed, and then 1000 A polysilicon film U of ~2000A is grown. Next, N on the n-type buried region 2
The polysilicon film U on the well region 5 and collector all layer 9, the area where the emitter, base and collector contacts of the NPN transistor are planned to be formed, and the gate oxide film 10 on the area where the emitter and collector contacts are planned to be formed.
After selectively removing p-type impurities, an active base region is formed in the N-well region 5 on the n-type buried region 2 by selectively ion-implanting p-type impurities, and further n-type impurities are selectively implanted. An emitter region opening and a collector contact region 14 are formed in the active base region and collector all layer 9 by ion implantation.

Next, as shown in FIG. 1(C), a polysilicon film of 2000 to 3000 A is grown and selectively etched to form MOS)-transistor gate electrodes and NPN).
An emitter electrode 16 and a collector electrode 17 that contact the emitter region U and collector contact region 14 of the transistor are formed at the same time.

After this, although not shown, a source region and a drain region are formed in the N well region 5 and the P well region 7, respectively.
Contact windows are formed above the active base region and the source and drain regions, and aluminum electrodes are formed in the contact windows to complete the Bi-CMOS integrated circuit.

Effects of the Invention As described above, according to the method for manufacturing a semiconductor integrated circuit of the present invention, in the manufacturing process of a Bi-CMO5 integrated circuit, M
The polysilicon film for forming the gate electrode of the OS transistor and the emitter electrode of the NPN transistor is deposited in two layers: immediately after the growth of the gate oxide film and immediately before the formation of the gate electrode and emitter electrode. It becomes possible to form the gate electrode of the MOS transistor and the emitter electrode of the NPN transistor at the same time without causing film contamination, thereby simplifying the process.

[Brief explanation of the drawing]

FIGS. 1A to 1C are process flow charts showing a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention. 1... P-type wheel crystal silicon substrate, 2, 21°° n-type buried region, 3, 31... p-type buried region, 4...
・N-type silicon epitaxial layer, 5... N-well region M, 6... P-type isolation region, 7... P-well region, 8
... Element isolation region, 9... Collector all of NPN transistor [,10... Silicon oxide film, 11...
...polysilicon film, ν...active base region, edict...
- Emitter region, 14... collector contact region,
15... Gate electrode, 16... Emitter electrode, 17
...Collector electrode.

Claims (1)

[Claims] 1. A step of continuously growing a polycrystalline silicon film after growing a gate oxide film, a step of selectively removing the polycrystalline silicon film on the area where the emitter, base, and collector contacts of the NPN transistor are to be formed; and a step of selectively removing the gate oxide film on the region where the collector contact is to be formed, a step of growing a polycrystalline silicon film after forming the emitter, base and collector contact regions, and selectively etching the polycrystalline silicon film. A method for manufacturing a semiconductor integrated circuit, comprising a step of simultaneously forming a gate electrode of a MOS transistor and an emitter electrode and a collector electrode of an NPN transistor.