JPS5915498B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPS5915498B2 JPS5915498B2 JP50096859A JP9685975A JPS5915498B2 JP S5915498 B2 JPS5915498 B2 JP S5915498B2 JP 50096859 A JP50096859 A JP 50096859A JP 9685975 A JP9685975 A JP 9685975A JP S5915498 B2 JPS5915498 B2 JP S5915498B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- film
- oxide film
- silicon oxide
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 56
- 229910052710 silicon Inorganic materials 0.000 claims description 56
- 239000010703 silicon Substances 0.000 claims description 56
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 35
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 9
- 230000001590 oxidative effect Effects 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 3
- 238000001444 catalytic combustion detection Methods 0.000 description 11
- 239000004020 conductor Substances 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005979 thermal decomposition reaction Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】
１５本発明は半導体装置の製造方法に関し、詳しくは半
導体集積回路における信頼性の向上ならびに高密度化を
はかるものである。DETAILED DESCRIPTION OF THE INVENTION 15 The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to improving reliability and increasing density in a semiconductor integrated circuit.
まず第１図に従来のＣＣＤにおける電極形成法を示す。First, FIG. 1 shows a method of forming electrodes in a conventional CCD.
シリコン半導体基体１１の上面にシリコ２０ ン酸化膜
１２を形成し、更にその上にシリコン膜１３を形成する
ａ、シリコン膜１３とシリコン酸化膜１２を選択的に除
去して島状領域を形成するｂｏしかるのちシリコン半導
体１１及びシリコン膜１３を高温酸化雰囲気に晒してシ
リコン酸化膜ク５１４を形成するＣｏ次に全面にアルミ
、ニウム膜又は第２のシリコン膜１５を選択的に形成す
るｄ。この電極形成法によつて電荷結合素子すなわちＣ
ｈａｒｇｅＣｏｕｐｌｅｄＤｅｖｉｃｅのゲートを構成
できる。このようにして、第１図のｄに示す如く９０φ
４、φ２、φ３、φ４と配線すれば４相、駆動ＣＣＤが
できる。ところがこの第１図の方法ではシリコン膜１３
と導電体膜１５とをフォト・エッチ法で形成するため相
互のマスク合せ余裕Ｌ、が必要なため島状領域形成後の
シリコン膜１３の最小巾■５Ｌ４はＬ４＝Ｌ２＋ ２Ｌ
、
但し、Ｌ２：導電体膜１５の間隙を形成するための最小
巾従つて、ＣＣＤの４相駆動を考えた場合の１ビツト当
りの電極巾ＬはＬ＝２（Ｌ３＋Ｌ４）
但し、Ｌ３：シリコン膜１３の間隙を形成するための最
小巾、現状ではＬ２＝Ｌ３＝３μ，Ｌ１＝２μであるの
でＬ−２０μが最小である。A silicon oxide film 12 is formed on the upper surface of the silicon semiconductor substrate 11, and a silicon film 13 is further formed thereon.A, the silicon film 13 and the silicon oxide film 12 are selectively removed to form an island region. Thereafter, the silicon semiconductor 11 and the silicon film 13 are exposed to a high-temperature oxidizing atmosphere to form a silicon oxide film 514. Next, an aluminum, nium film, or a second silicon film 15 is selectively formed on the entire surface. By this electrode formation method, a charge-coupled device, i.e., C
A gate for a hargeCoupledDevice can be configured. In this way, the 90φ
By wiring 4, φ2, φ3, and φ4, a 4-phase driving CCD can be created. However, in the method shown in FIG.
Since the conductor film 15 and the conductor film 15 are formed by photo-etching, a mutual mask alignment margin L is required, so the minimum width of the silicon film 13 after forming the island region 5L4 is L4=L2+2L.
, However, L2: Minimum width for forming the gap between the conductor films 15 Therefore, when considering four-phase drive of CCD, the electrode width L per 1 bit is L=2 (L3 + L4) However, L3: Silicon The minimum width for forming the gap between the membranes 13 is currently L2=L3=3μ and L1=2μ, so the minimum width is L-20μ.
他方、ＣＣＤの電極巾νと最大転送ロツク周波数ｆφと
はｆφ〜打−２なる関係がある。On the other hand, the relationship between the electrode width ν of the CCD and the maximum transfer lock frequency fφ is fφ˜k−2.
この様に、ＣＣＤの高密度化及び高速動作を考えると電
極巾の微小化が要求されれる。そこで、本発明の目的は
、ＣＣＤの電極巾を短かくし高密度化及び高速動作化、
信頼性の高い電極構造を容易に得ることにある。As described above, considering the high density and high speed operation of CCDs, miniaturization of the electrode width is required. Therefore, an object of the present invention is to shorten the electrode width of a CCD to increase density and high-speed operation.
The objective is to easily obtain a highly reliable electrode structure.
又、本発明の別の目的はＭＯＳトランジスタのゲート電
極、ソース、ドレイン電極及び配線の高密度化、信頼性
の高い電極構造を容易に得ることにある。以下本発明の
実施例を図面とともに詳細に説明する。第２図及び第３
図は本発明の実施例にかかるＣＣＤの電極形成法及びＮ
ＯＳトランジスタの配線の形成法を示すものである。第
２図において、シリコン半導体基体２１の上面に約５０
０λのシリコン酸化膜２２と約１０００Ａのシリコン窒
化膜２３の２層膜を形成するＡＯ更にその上にＳｉＨ４
の熱分解法や蒸着法を用いて約４０００λの低抵抗率の
第１のシリコン膜２４を形成し、約１μのシリコン酸化
膜２５をシリコン膜２４の上に形成する。Another object of the present invention is to easily obtain a high-density, highly reliable electrode structure of the gate electrode, source, drain electrode, and wiring of a MOS transistor. Embodiments of the present invention will be described in detail below with reference to the drawings. Figures 2 and 3
The figure shows a CCD electrode formation method according to an embodiment of the present invention and N
This figure shows a method of forming wiring for an OS transistor. In FIG. 2, approximately 500
AO forms a two-layer film of a silicon oxide film 22 with a thickness of 0λ and a silicon nitride film 23 with a thickness of approximately 1000A.
A first silicon film 24 with a low resistivity of about 4000λ is formed using a thermal decomposition method or a vapor deposition method, and a silicon oxide film 25 of about 1 μm is formed on the silicon film 24.
この場合、シリコン酸化膜２５はＨＦ液に対するエツチ
ング速度を速めるためにリンガラス（ＰｈＯｐｈＯｓｉ
ｌｉｃａｔｅｇｌａｓｓ）膜が好ましいＢＯ次に、シリ
コン膜２４とシリコン酸化膜２５の２層膜を選択的にエ
ツチングして島状領域２６を形成するＣ。こうしたのち
、第１のシリコン膜２４の露出した側面に、高温酸化雰
囲気中に晒して約３０００人の低抵抗率のシリコン酸化
膜２７を形成する。In this case, the silicon oxide film 25 is etched with phosphorus glass (PhOphOsi) to increase the etching rate with respect to the HF solution.
Next, the two-layer film of the silicon film 24 and the silicon oxide film 25 is selectively etched to form an island region 26. Thereafter, a silicon oxide film 27 having a low resistivity of about 3,000 layers is formed on the exposed side surface of the first silicon film 24 by exposing it to a high temperature oxidizing atmosphere.
この場合、シリコン半導体基体２１の表面はシリコン窒
化膜２３で覆われているため酸化されないＤ。ついで全
面に約４０００人の第２のシリコン膜２８を蒸着法によ
つて形成する。この場合、シリコン酸化膜２５の側面に
第２のシリコン膜２８が付着形成されないようにする。
従つて、ＳｉＨ４の熱分解法によるシリコン膜２８の形
成は不適当であるＥＯつぎに、シリコン酸化膜２５のエ
ツチング液（例えばＨＦ液）に浸して、シリコン酸化膜
２５の除去及びその上に形成された一部の第２のシリコ
ン膜２８の除去を同時に行なう。In this case, the surface of the silicon semiconductor substrate 21 is covered with the silicon nitride film 23, so it is not oxidizedD. Next, a second silicon film 28 of approximately 4,000 layers is formed over the entire surface by vapor deposition. In this case, the second silicon film 28 is prevented from being deposited on the side surface of the silicon oxide film 25.
Therefore, forming the silicon film 28 by the thermal decomposition method of SiH4 is inappropriate. At the same time, the removed portion of the second silicon film 28 is removed.
このとき前述のように１μ厚のリンガラス膜をシリコン
酸化膜２５に用いると、ＨＦ液でエツチングすれば約１
分で除去される。なおシリコン窒化膜２３はＨＦ液に対
してエツチング速度は十分に遅いため、シリコン酸化膜
２７が除去されても、窒化膜２３は除去されないＦＯこ
うしたのち、高温酸化雰囲気中に晒して残された第１及
び第２のシリコン膜２４，２８をシリコン酸化膜２９で
覆う。シリコン酸化膜２９に選択的にコンタクト窓あけ
を行ない、ｇ図に示す如くφ１〜φ４の配線を行なえば
４相駆動ＣＣＤが得られる。以上の方法によれば第１の
シリコン膜２４の巾及び間隙を夫々３μに形成できるの
で、Ｌ５＝Ｌ６−３μとなり１ビツト当り１２μで形成
され、従来に比べ巾は約妻、転送速度は約４倍に速くな
る。なお、第２図ａ−ｇの製造工程に於いて、ｂ工程で
第１のシリコン膜２４とシリコン酸化膜２５の間にシリ
コン窒化膜２３′を挟めば、最終工程ではｈに示す如く
、第１のシリコン膜２４の上面はシリコン窒化膜２３′
に、第２のシリコン膜２８の上面はシリコン酸化膜２９
で覆われる。At this time, if a phosphorus glass film with a thickness of 1 μm is used as the silicon oxide film 25 as described above, if etched with HF solution, the thickness will be approximately 1 μm thick.
Removed in minutes. Note that the etching rate of the silicon nitride film 23 is sufficiently slow compared to the HF solution, so even if the silicon oxide film 27 is removed, the nitride film 23 is not removed. The first and second silicon films 24 and 28 are covered with a silicon oxide film 29. A four-phase drive CCD can be obtained by selectively forming contact windows in the silicon oxide film 29 and wiring φ1 to φ4 as shown in FIG. According to the above method, the width and gap of the first silicon film 24 can be formed to 3μ, respectively, so L5=L6-3μ, and 12μ per bit is formed, and compared to the conventional method, the width is about the same and the transfer speed is about 4 times faster. In the manufacturing steps shown in FIGS. 2a to 2g, if the silicon nitride film 23' is sandwiched between the first silicon film 24 and the silicon oxide film 25 in step b, the final step will be as shown in h. The upper surface of the silicon film 24 of No. 1 is a silicon nitride film 23'.
The upper surface of the second silicon film 28 is covered with a silicon oxide film 29.
covered with
この場合には、第１及び第２のシリコン膜２４，２８へ
のコンタクト窓あけ工程でシリコン酸化膜２９とシリコ
ン窒化膜２３′の選択的エツチングが可能なためフオト
・エツチング工程でのマスク合せ余裕を大きくすること
ができる。第３図は本発明を用いた他の実施例であるＭ
ＯＳトランジスタの製造方法である。In this case, the silicon oxide film 29 and the silicon nitride film 23' can be selectively etched in the process of forming contact windows in the first and second silicon films 24 and 28, so there is no mask alignment margin in the photo-etching process. can be made larger. FIG. 3 shows another embodiment of the present invention.
This is a method for manufacturing an OS transistor.
第３図において、シリコン半導体基体３１の上面に選択
的に約１０００人のシリコン窒化膜３２を形成するＡＯ
このシリコン窒化膜３２を酸化に対する保護膜として用
いて露出したシリコン半導体基体３１を選択的に酸化し
約１μのシリコン酸化膜３３を形成し、シリコン窒化膜
３２を熱リン酸液で除去するＢ。つぎに露出したシリコ
ン半導体基体３１に約５００へのシリコン酸化膜３４を
形成し、更にその上に約１０００人のシリコン窒化膜３
５を形成するＣＯ更にその上に約４０００人の低抗率の
第１のシリコン膜３６をＳｉＨ４の熱分解法又は蒸着法
によつて形成し、その上に約１μのシリコン酸化膜３７
を形成するＤ。In FIG. 3, AO selectively forms about 1000 silicon nitride films 32 on the upper surface of a silicon semiconductor substrate 31.
Using this silicon nitride film 32 as a protective film against oxidation, the exposed silicon semiconductor substrate 31 is selectively oxidized to form a silicon oxide film 33 with a thickness of about 1 μm, and the silicon nitride film 32 is removed with hot phosphoric acid solution B. Next, a silicon oxide film 34 of approximately 500 mL is formed on the exposed silicon semiconductor substrate 31, and a silicon nitride film 34 of approximately 1000 mL is further formed thereon.
Furthermore, a first silicon film 36 with a low resistivity of about 4,000 layers is formed thereon by a thermal decomposition method or vapor deposition method of SiH4, and a silicon oxide film 37 with a thickness of about 1 μm is formed thereon.
D to form.
しかるのち、シリコン酸化膜３７及び第１のシリコン膜
３６の２層膜を選択的にエツチングして島状領域３８を
形成するＥＯ第１のシリコン膜３６の露出した側面を高
温酸化雰囲気に晒して約５０００λのシリコン酸化膜３
９を形成するＦＯこうした後、シリコン酸化膜３７と第
１のシリコン膜３６の２層膜をエツチング保護膜として
シリコン窒化膜３５、シリコン酸化膜３４の２層膜を自
己整合的にエツチング除去するＧＯそして不純物原子を
含んた約４０００人の低抵抗率の第２のシリコン膜４０
を蒸着法で形成するＨ。Thereafter, the two-layer film of the silicon oxide film 37 and the first silicon film 36 is selectively etched to form the island region 38, and the exposed side surface of the EO first silicon film 36 is exposed to a high temperature oxidizing atmosphere. Silicon oxide film 3 of about 5000λ
After this, the two-layer film of the silicon nitride film 35 and the silicon oxide film 34 is etched away in a self-aligned manner using the two-layer film of the silicon oxide film 37 and the first silicon film 36 as an etching protection film. Then, a second silicon film 40 of approximately 4,000 layers containing impurity atoms and having a low resistivity is formed.
H formed by vapor deposition.
ＨＦ液でシリコン酸化膜３７とその上の第２のシリコン
膜４０を除去すると、第１と第２のシリコン膜３６と４
０がシリコン酸化膜３８の厚さで隔てられて形成される
。この状態で高温に保持すれば第２のシリコン膜４０と
シリコン半導体基体３１と接し２部分に不純物原子が拡
散されソース、ドレインとなる拡散領域４１，４２が形
成されるＦ。しかるのち、高温酸化雰囲気中に晒せば第
１と第２のシリコン膜３６，４０はシリコン酸化膜４３
で覆われるＪＯその後、第１と第２のシリコン膜３６，
４０に選択的にコンタクト領域を形成し配線を施せばＭ
ＯＳ型集積回路が形成される。即ち第３図は拡散領域４
１，４２およびその上の第２のシリコン膜４０をソース
、ドレイン、シリコン酸化膜３４とシリコン窒化膜３５
をゲート絶縁膜、このゲート絶縁膜上の第１のシリコン
膜３６をゲート導電体、シリコン酸化膜３３の上面に形
成された第１と第２のシリコン膜３６，４０を配線とし
たＭＯＳ集積回路である。なお、第３図ｄで第１のシリ
コン膜３６とシリコン酸化膜３７の間にシリコン窒化膜
を挟めぱ第２図のｈで説明した如くコンタクト窓あけの
選択エツチングが可能で、更に高密度化が可能である。When the silicon oxide film 37 and the second silicon film 40 thereon are removed with HF solution, the first and second silicon films 36 and 4 are removed.
0 are formed separated by the thickness of the silicon oxide film 38. If the high temperature is maintained in this state, impurity atoms are diffused into the two portions where the second silicon film 40 and the silicon semiconductor substrate 31 are in contact, forming diffusion regions 41 and 42 that will become the source and drain F. Thereafter, by exposing the first and second silicon films 36 and 40 to a high temperature oxidizing atmosphere, the first and second silicon films 36 and 40 become silicon oxide films 43.
The JO is then covered with the first and second silicon films 36,
If a contact region is selectively formed in 40 and wiring is applied, M
An OS type integrated circuit is formed. That is, FIG. 3 shows the diffusion region 4.
1, 42 and the second silicon film 40 thereon as a source, a drain, a silicon oxide film 34 and a silicon nitride film 35.
is a gate insulating film, the first silicon film 36 on this gate insulating film is a gate conductor, and the first and second silicon films 36 and 40 formed on the upper surface of the silicon oxide film 33 are wirings. It is. If a silicon nitride film is sandwiched between the first silicon film 36 and silicon oxide film 37 in FIG. 3d, selective etching of contact windows can be performed as explained in FIG. is possible.
第３図の方法にて作成されたＭＯＳトランジスタは、ゲ
ート、ソース、ドレイン電極となるシリコン膜の巾のみ
でほぼ寸法が決定され、かつソース、ドレイン電極は自
己整合的に形成可能でマスク合せ寸法が全く必要でなく
、また、ソース、ドレイン領域自体もソース、ドレイン
電極とほぼ同一の大きさとなり、従来のＭＯＳトランジ
スタに比べ大巾に面積を小さくすることができ、当然電
気的な性能も向上する。そして、ゲート、ソース、ドレ
イン電極も平坦な構造となり、高密度化、多層配線構造
に好適である。以上のように本発明を用いればＣＣＤの
ゲート電極巾が従来の約２倍短かくできるため高密度化
と高速動作が可能になつた。The dimensions of the MOS transistor fabricated using the method shown in Figure 3 are determined almost solely by the widths of the silicon films that serve as the gate, source, and drain electrodes, and the source and drain electrodes can be formed in a self-aligned manner, allowing for mask alignment dimensions. In addition, the source and drain regions themselves are approximately the same size as the source and drain electrodes, making it possible to significantly reduce the area compared to conventional MOS transistors, and of course improve electrical performance. do. The gate, source, and drain electrodes also have a flat structure, which is suitable for high-density and multilayer wiring structures. As described above, by using the present invention, the width of the gate electrode of a CCD can be made approximately twice as short as that of the conventional one, thereby making it possible to achieve higher density and higher speed operation.
又、本発明はＭＯＳ型集積回路に於いても高密度化が可
能で、かつ第３図ｊで分るように第２層目の配線を施こ
すに際し、表面が平坦に形成されるため第２層配線の高
密度化と断線防止が可能となつた。さらに、本発明では
、電極として平坦な信頼性の高いシリコン膜を形成して
おり、かつ、電極間に酸化により絶縁膜を容易に形成で
きるため、微小な電極間の絶縁を一層確実なものとする
ことができる。Furthermore, the present invention enables high density even in MOS type integrated circuits, and as shown in FIG. It has become possible to increase the density of two-layer wiring and prevent disconnections. Furthermore, in the present invention, a flat and highly reliable silicon film is formed as an electrode, and an insulating film can be easily formed between the electrodes by oxidation, making the insulation between minute electrodes even more reliable. can do.
このように、本発明は半導体集積回路の高密度化、信頼
性の向上、製造の容易さに大きく寄与するものである。As described above, the present invention greatly contributes to higher density, improved reliability, and ease of manufacturing of semiconductor integrated circuits.
第１図ａ−ｄは従来のＣＣＤにおける電極形成工程図、
第２図ａ−ｈは本発明の一実施例にかかるＣＣＤの電極
形成工程図、第３図ａ−ｊは本発明の他の実施例にかか
るＭＯＳ型集積回路の製造工程断面図である。
２１，３１・・・・・・シリコン半導体基体、２２，２
５，２７，２９，３３，３４，３９，４３・・・・・・
シリコン酸化膜、２６，３８・・・・・・島状領域、２
４，２８，３６，４０・・・・・・シリコン膜、２３，
２３′，３２，３５・・−・・・シリコン窒化膜、４１
，４２・・・・・・拡散領域。Figures 1a-d are electrode forming process diagrams in a conventional CCD;
2A to 2H are process diagrams for forming electrodes of a CCD according to an embodiment of the present invention, and FIGS. 3A to 3J are sectional views of a manufacturing process for a MOS type integrated circuit according to another embodiment of the present invention. 21, 31... Silicon semiconductor substrate, 22, 2
5, 27, 29, 33, 34, 39, 43...
Silicon oxide film, 26, 38... island-like region, 2
4, 28, 36, 40... silicon film, 23,
23', 32, 35...Silicon nitride film, 41
, 42... Diffusion area.
Claims (1)
ゲート絶縁膜として第１のシリコン酸化膜、シリコン窒
化膜を形成する工程と、更にその上面に第１のシリコン
膜の３層膜を形成する工程と、更にその上面に第２のシ
リコン酸化膜を形成する工程と、上記第２のシリコン酸
化膜と第１のシリコン膜とを選択的に除去してゲート電
極及び配線を形成する工程と、上記第１のシリコン膜の
露出した側面を熱酸化する工程と、第２のシリコン膜を
全面に形成した後、上記第２のシリコン酸化膜をエッチ
ング除去すると同時にその上に形成された上記第２のシ
リコン膜を除去してＭＯＳトランジスタのソース、ドレ
イン電極と配線を形成する工程と、上記ソース、ドレイ
ン電極から上記シリコン半導体基体へ不純物を拡散して
ソース、ドレイン領域を形成する工程と、残された上記
第１、第２のシリコン膜間に絶縁膜を形成する工程とを
備えたことを特徴とする半導体装置の製造方法。 ２ 上記特許請求の範囲第１項において、上記第１のシ
リコン膜の露出した側面を酸化した後、上記シリコン窒
化膜及び第１のシリコン酸化膜を選択的に除去する工程
を備えたことを特徴とする半導体装置の製造方法。[Claims] 1. A step of forming a first silicon oxide film and a silicon nitride film as a gate insulating film of a MOS transistor on the upper surface of a silicon semiconductor substrate, and further forming a three-layer film of the first silicon film on the upper surface. a step of forming a second silicon oxide film on the upper surface thereof; and a step of selectively removing the second silicon oxide film and the first silicon film to form a gate electrode and wiring. and a step of thermally oxidizing the exposed side surface of the first silicon film, and after forming a second silicon film on the entire surface, etching away the second silicon oxide film and simultaneously removing the second silicon film formed thereon. a step of removing a second silicon film to form source and drain electrodes and wiring of a MOS transistor; a step of diffusing impurities from the source and drain electrodes into the silicon semiconductor substrate to form source and drain regions; A method for manufacturing a semiconductor device, comprising the step of forming an insulating film between the remaining first and second silicon films. 2. The method according to claim 1, further comprising the step of selectively removing the silicon nitride film and the first silicon oxide film after oxidizing the exposed side surface of the first silicon film. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50096859A JPS5915498B2 (en) | 1975-08-09 | 1975-08-09 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50096859A JPS5915498B2 (en) | 1975-08-09 | 1975-08-09 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5220771A JPS5220771A (en) | 1977-02-16 |
| JPS5915498B2 true JPS5915498B2 (en) | 1984-04-10 |
Family
ID=14176185
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50096859A Expired JPS5915498B2 (en) | 1975-08-09 | 1975-08-09 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5915498B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR940009601B1 (en) * | 1991-09-14 | 1994-10-15 | 금성일렉트론 주식회사 | Manufacturing method of charge coupled device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4868177A (en) * | 1972-01-27 | 1973-09-17 | ||
| JPS4914792A (en) * | 1972-04-14 | 1974-02-08 | ||
| JPS4966082A (en) * | 1972-09-11 | 1974-06-26 | ||
| JPS49114375A (en) * | 1973-02-28 | 1974-10-31 | ||
| JPS49114374A (en) * | 1973-02-28 | 1974-10-31 | ||
| JPS5146078A (en) * | 1974-10-18 | 1976-04-20 | Hitachi Ltd | EMUAIESUGATAHANDOTAISHUSEKIKAIROSOCHINO SEIHO |
-
1975
- 1975-08-09 JP JP50096859A patent/JPS5915498B2/en not_active Expired
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4868177A (en) * | 1972-01-27 | 1973-09-17 | ||
| JPS4914792A (en) * | 1972-04-14 | 1974-02-08 | ||
| JPS4966082A (en) * | 1972-09-11 | 1974-06-26 | ||
| JPS49114375A (en) * | 1973-02-28 | 1974-10-31 | ||
| JPS49114374A (en) * | 1973-02-28 | 1974-10-31 | ||
| JPS5146078A (en) * | 1974-10-18 | 1976-04-20 | Hitachi Ltd | EMUAIESUGATAHANDOTAISHUSEKIKAIROSOCHINO SEIHO |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5220771A (en) | 1977-02-16 |
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