JPS59152746U - パワ−トランジスタの素子構造 - Google Patents

パワ−トランジスタの素子構造

Info

Publication number
JPS59152746U
JPS59152746U JP1983046353U JP4635383U JPS59152746U JP S59152746 U JPS59152746 U JP S59152746U JP 1983046353 U JP1983046353 U JP 1983046353U JP 4635383 U JP4635383 U JP 4635383U JP S59152746 U JPS59152746 U JP S59152746U
Authority
JP
Japan
Prior art keywords
power transistor
element structure
chip
transistor element
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1983046353U
Other languages
English (en)
Japanese (ja)
Other versions
JPH02912Y2 (https=
Inventor
上符　敏昭
関　修
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Corp
Original Assignee
Meidensha Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Corp filed Critical Meidensha Corp
Priority to JP1983046353U priority Critical patent/JPS59152746U/ja
Publication of JPS59152746U publication Critical patent/JPS59152746U/ja
Application granted granted Critical
Publication of JPH02912Y2 publication Critical patent/JPH02912Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Bipolar Transistors (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
JP1983046353U 1983-03-30 1983-03-30 パワ−トランジスタの素子構造 Granted JPS59152746U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983046353U JPS59152746U (ja) 1983-03-30 1983-03-30 パワ−トランジスタの素子構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983046353U JPS59152746U (ja) 1983-03-30 1983-03-30 パワ−トランジスタの素子構造

Publications (2)

Publication Number Publication Date
JPS59152746U true JPS59152746U (ja) 1984-10-13
JPH02912Y2 JPH02912Y2 (https=) 1990-01-10

Family

ID=30176908

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983046353U Granted JPS59152746U (ja) 1983-03-30 1983-03-30 パワ−トランジスタの素子構造

Country Status (1)

Country Link
JP (1) JPS59152746U (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5756911B2 (ja) * 2010-06-03 2015-07-29 パナソニックＩｐマネジメント株式会社 半導体装置およびこれを用いた半導体リレー

Also Published As

Publication number Publication date
JPH02912Y2 (https=) 1990-01-10

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