JPS59152746U - Power transistor element structure - Google Patents

Power transistor element structure

Info

Publication number
JPS59152746U
JPS59152746U JP1983046353U JP4635383U JPS59152746U JP S59152746 U JPS59152746 U JP S59152746U JP 1983046353 U JP1983046353 U JP 1983046353U JP 4635383 U JP4635383 U JP 4635383U JP S59152746 U JPS59152746 U JP S59152746U
Authority
JP
Japan
Prior art keywords
power transistor
element structure
chip
transistor element
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1983046353U
Other languages
Japanese (ja)
Other versions
JPH02912Y2 (en
Inventor
上符　敏昭
関　修
Original Assignee
株式会社明電舎
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社明電舎 filed Critical 株式会社明電舎
Priority to JP1983046353U priority Critical patent/JPS59152746U/en
Publication of JPS59152746U publication Critical patent/JPS59152746U/en
Application granted granted Critical
Publication of JPH02912Y2 publication Critical patent/JPH02912Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Bipolar Transistors (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のパワートランジスタの素子構成図、第２
図は従来構成におけるベースドライブへの影響を説明す
るためのスイッチ回路図、第３図は本考案の一実施例を
示す素子構成図、第４図は本考案の応用例を示す回路図
である。 １・・・シリコンチップ、２・・・トランジスタケース
、３　＝、　　３　ｎ、　　３　ｏ、　　３　ｏ””ホ
ンディング線、Ｂ、Ｃ。 Ｅ・・・外部引出し端子、Ｂｏ・・・ベースドライブ専
用端子、４・・・ベースドライブ回路、７．８・・・接
続導体。Figure 1 is an element configuration diagram of a conventional power transistor, Figure 2
The figure is a switch circuit diagram for explaining the influence on the base drive in a conventional configuration, Figure 3 is an element configuration diagram showing an embodiment of the present invention, and Figure 4 is a circuit diagram showing an example of application of the present invention. . 1...Silicon chip, 2...Transistor case, 3=, 3n, 3o, 3o""Honding wire, B, C. E... External lead-out terminal, Bo... Base drive dedicated terminal, 4... Base drive circuit, 7.8... Connection conductor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] パワートランジスタが形成され該トランジスタの各引出
し端子が形成されたチップと、このチップを収納し上記
各端子に対応づけてボンディング線で接続される外部引
出し臨子及び上記チップ上のエミッタ引出し端子とボン
ディング線で接続されるベースドライブ専用の基準電位
端子にされる外部引出し端子を有するトランジスタケー
スとを備えたことを特徴とするパワートランジスタの素
子構造。A chip on which a power transistor is formed and each lead-out terminal of the transistor is formed, an external lead-out connector that accommodates this chip and is connected to each of the above-mentioned terminals by a bonding wire, and bonding with the emitter lead-out terminal on the chip. 1. An element structure of a power transistor characterized by comprising: a transistor case having an external lead-out terminal connected by a wire and used as a reference potential terminal dedicated to a base drive;
JP1983046353U 1983-03-30 1983-03-30 Power transistor element structure Granted JPS59152746U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983046353U JPS59152746U (en) 1983-03-30 1983-03-30 Power transistor element structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983046353U JPS59152746U (en) 1983-03-30 1983-03-30 Power transistor element structure

Publications (2)

Publication Number Publication Date
JPS59152746U true JPS59152746U (en) 1984-10-13
JPH02912Y2 JPH02912Y2 (en) 1990-01-10

Family

ID=30176908

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983046353U Granted JPS59152746U (en) 1983-03-30 1983-03-30 Power transistor element structure

Country Status (1)

Country Link
JP (1) JPS59152746U (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5756911B2 (en) * 2010-06-03 2015-07-29 パナソニックＩｐマネジメント株式会社 Semiconductor device and semiconductor relay using the same

Also Published As

Publication number Publication date
JPH02912Y2 (en) 1990-01-10

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