JPS6016556U - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS6016556U JPS6016556U JP1983195087U JP19508783U JPS6016556U JP S6016556 U JPS6016556 U JP S6016556U JP 1983195087 U JP1983195087 U JP 1983195087U JP 19508783 U JP19508783 U JP 19508783U JP S6016556 U JPS6016556 U JP S6016556U
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- transistor element
- outside
- semiconductor equipment
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来の配線法によるトランジスタ装置の上から
見た図であり、第2図は本考案の一実施例を示すトラン
ジスタ装置の上から見た図である。
1.19.20・・・・・・コレクタリード電極、2゜
21・・・・・・ベー゛スリード電極、3.22.24
゜15・・・・・・エミッタリード電極、5.27.2
8−・・・・・トランジスタ素子、6. 7. 33.
34. 41゜42・・・・・・ボンディング線、4
・・・・・・容器、29〜32・・・・・・電極。FIG. 1 is a top view of a transistor device using a conventional wiring method, and FIG. 2 is a top view of a transistor device showing an embodiment of the present invention. 1.19.20... Collector lead electrode, 2゜21... Base lead electrode, 3.22.24
゜15...Emitter lead electrode, 5.27.2
8-...Transistor element, 6. 7. 33.
34. 41゜42...Bonding wire, 4
... Container, 29-32 ... Electrode.
Claims (1)
および第2のトランジスタ素子と、該第1のトランジス
タ素子を載置して該第1のトランジスタ素子の出力電極
を外部に導出する第1の電極と、前記第2のトランジス
タ素子を載置して該第2のトランジスタ素子の出力電極
を外部に導出する第2の電極と、前記第1のトランジス
タ素子の入力電極を外部に導出する第3の電極と、前記
第2のトランジスタ素子の入力電極を外部に導出する第
4の電極と、前記第1および第2のトランジスタ素子の
共通電極を外部に導出する第5の電極とを単一の容器に
備え、前記第1、第2、第3、第4および第5の電極は
前記単一容器内部でほぼ同一平面を形成していることを
特徴とする半導体 、装置。A first electrode comprising an input electrode, an output electrode, and a common electrode, respectively.
and a second transistor element, a first electrode on which the first transistor element is placed and an output electrode of the first transistor element is led to the outside, and a second transistor element on which the second transistor element is placed. a second electrode that leads the output electrode of the second transistor element to the outside; a third electrode that leads the input electrode of the first transistor element to the outside; and an input electrode of the second transistor element. A fourth electrode led out to the outside and a fifth electrode led out to the outside a common electrode of the first and second transistor elements are provided in a single container, and the first, second, third, A semiconductor device, wherein the fourth and fifth electrodes form substantially the same plane within the single container.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1983195087U JPS6016556U (en) | 1983-12-19 | 1983-12-19 | semiconductor equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1983195087U JPS6016556U (en) | 1983-12-19 | 1983-12-19 | semiconductor equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6016556U true JPS6016556U (en) | 1985-02-04 |
Family
ID=30419118
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1983195087U Pending JPS6016556U (en) | 1983-12-19 | 1983-12-19 | semiconductor equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6016556U (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63310686A (en) * | 1987-06-12 | 1988-12-19 | シャープ株式会社 | Washing machine |
JPH01103596U (en) * | 1987-12-23 | 1989-07-13 |
-
1983
- 1983-12-19 JP JP1983195087U patent/JPS6016556U/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63310686A (en) * | 1987-06-12 | 1988-12-19 | シャープ株式会社 | Washing machine |
JPH0477636B2 (en) * | 1987-06-12 | 1992-12-08 | Sharp Kk | |
JPH01103596U (en) * | 1987-12-23 | 1989-07-13 |
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