JPS59147505A - Amplifier circuit - Google Patents

Amplifier circuit

Info

Publication number
JPS59147505A
JPS59147505A JP58020951A JP2095183A JPS59147505A JP S59147505 A JPS59147505 A JP S59147505A JP 58020951 A JP58020951 A JP 58020951A JP 2095183 A JP2095183 A JP 2095183A JP S59147505 A JPS59147505 A JP S59147505A
Authority
JP
Japan
Prior art keywords
circuit
power supply
switching
output
bootstrap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58020951A
Other languages
Japanese (ja)
Inventor
Kenzou Shiyou
鐘 健三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP58020951A priority Critical patent/JPS59147505A/en
Publication of JPS59147505A publication Critical patent/JPS59147505A/en
Pending legal-status Critical Current

Links

Landscapes

  • Amplifiers (AREA)

Abstract

PURPOSE:To prevent abnormal sound from being produced by providing a switching control circuit and the 1st and the 2nd switching circuits to a drive circuit of an amplifier for an output circuit of which a bootstrap circuit is used so as to prevent the leakage of power supply ripple at application of a power switch. CONSTITUTION:The bootstrap circuit comprising output transistors (TR) 6, 8 and a bootstrap capacitor 18 is provided to an output stage of an amplifier circuit and the TRs 6, 8 are switched alternately by the drive circuit 10. The 1st switching circuit 28 is connected between the circuit 10 and a power supply terminal 2 and the 2nd switching circuit 32 is connected between the base of the TR8 and the power supply terminal 2 via a constant current source 30. Further, a switching control circuit 34 is connected between the power supply terminal 2 and a reference potential terminal 4 and the time constant of the circuit 34 is decided by the capacitor 38. Moreover the circuits 28, 32 are controlled by the circuit 34 so as to prevent the leakage of ripple and the generation of abnormal sound at application of the power supply switch 40.

Description

【発明の詳細な説明】 この発明は増幅回路に係り、特に、ブートストランプ回
路を内部に持つ増幅回路において過渡者の発生を防止し
たものに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an amplifier circuit, and more particularly to an amplifier circuit having an internal bootstrap circuit in which the generation of transients is prevented.

第1図は出力回路をブートストラップ回路で構成した増
幅回路の構成を示している。電源端子2には図示してい
ない電源スィッチを介して駆動型(1) 圧Vccが印加され、この電源端子2と基準電位側端子
4との間には、出力l−ランジスクロ、8が直列に接続
されている。各出力1−ランジスタロ、8のベースには
駆動回路10が接続され、この駆動回路10の出力信号
に基づき各出カドランジスタロ、8は交互にスイッチン
グ動作をするように成っている。前記電源端子2には抵
抗12を介して駆動回路10が接続され駆動電圧Vcc
が印加されるとともにブートストラップ端子14が形成
されている。このブートストラップ端子14と出力端子
16との間には、ブー1ヘストラップ用のコンデンサ1
Bが挿入されている。また、出力11b1子16と基準
電位側端子4との間には、コンデンサ20を介して負荷
22が接続されている。また、この増幅回路の出力点に
は抵抗24が接続され、この抵抗24を介して図示して
いない前段増幅器へ帰還信号が与えられる。また、駆動
回路10には信号入力端子2Gが形成され、この信号入
力端子26には前段増幅器からの信号が与えられる。
FIG. 1 shows the configuration of an amplifier circuit in which the output circuit is composed of a bootstrap circuit. A driving type (1) voltage Vcc is applied to the power supply terminal 2 via a power switch (not shown), and an output l-range screen 8 is connected in series between the power supply terminal 2 and the reference potential side terminal 4. It is connected. A drive circuit 10 is connected to the base of each output transistor 8, and each output transistor 8 alternately performs a switching operation based on the output signal of the drive circuit 10. A drive circuit 10 is connected to the power supply terminal 2 via a resistor 12, and a drive voltage Vcc is connected to the drive circuit 10 through a resistor 12.
is applied and a bootstrap terminal 14 is formed. Between this bootstrap terminal 14 and the output terminal 16, a capacitor 1 for bootstrap is connected.
B is inserted. Further, a load 22 is connected between the output 11b1 terminal 16 and the reference potential side terminal 4 via a capacitor 20. Further, a resistor 24 is connected to the output point of this amplifier circuit, and a feedback signal is given to a pre-stage amplifier (not shown) via this resistor 24. Further, a signal input terminal 2G is formed in the drive circuit 10, and a signal from the previous stage amplifier is applied to this signal input terminal 26.

このように出力回路がブートスI・ラップ回路で(2) 構成されている場合、駆動回路10は電源スィッチの投
入に基づく過渡台の発生を防止するために、電源スィッ
チの投入から一定の時間遅れの後、動作し得るように構
成される。しかしながら、電源スィッチの投入から駆動
回路10が動作するまでの間、出力端子16のインピー
ダンスは高い状態に維持されるため、負荷22には異常
信号電流が流れ易い状態となっており、これがポツプ音
等、異常音の発生原因に成る。特に、電源ラインからの
影響は抵抗12、コンデンサ18.20を介して負荷2
2に伝達され、電源スィッチの投入時のショックや電源
電圧の変動やリップル等が異常信号の発生原因に成る。
In this way, when the output circuit is configured with a bootstrap I/wrap circuit (2), the drive circuit 10 is configured with a certain time delay after turning on the power switch in order to prevent the occurrence of a transient stage due to turning on the power switch. After that, it is configured to be operational. However, since the impedance of the output terminal 16 is maintained in a high state from the time when the power switch is turned on until the drive circuit 10 starts operating, an abnormal signal current easily flows through the load 22, which causes pop noises. etc., may cause abnormal noise. In particular, the influence from the power supply line is applied to the load 2 through the resistor 12 and capacitor 18.
2, and shocks when the power switch is turned on, fluctuations and ripples in the power supply voltage, etc., become causes of abnormal signals.

この発明は、このようなブートスI・ラップ回路で出力
回路を構成する場合、電源スィッチの投入時における異
常音の発生を防止した増幅回路の提供を目的としている
An object of the present invention is to provide an amplifier circuit that prevents abnormal noise from occurring when a power switch is turned on when an output circuit is configured with such a bootstrap I/wrap circuit.

この発明は、出力回路がブートスI・ランプ回路で構成
される増幅回路において、前記出力回路を駆動する駆動
回路と電源との間に挿入された第1(3) のスイッチング回路と、前記出力回路と電源との間に挿
入された第2のスイッチング回路と、電源供給開始から
一定時間において第1のスイッチング回路を導通状態に
制御するとともに第2のスイッチング回路を不導通状態
に制御するスイッチング制御回路とを具備したことを特
徴とする。
The present invention provides an amplifier circuit in which the output circuit is composed of a boots I/ramp circuit, and a first (third) switching circuit inserted between a drive circuit that drives the output circuit and a power supply; and a switching control circuit that controls the first switching circuit to be in a conductive state and the second switching circuit to be in a non-conductive state for a certain period of time from the start of power supply. It is characterized by having the following.

以下、この発明の実施例を図面を参照して詳細に説明す
る。
Embodiments of the present invention will be described in detail below with reference to the drawings.

第2図はこの発明の増幅回路の実施例を示し、第1図の
回路と同一部分には同一・符号をイ」シである。図にお
いて、駆動回路10に電源を供給するための電源ライン
には第1のスイッチング回路28が挿入され、出力トラ
ンジスタ8のヘースと電源ラインとの間には定電流源3
0を介して第2のスイッチング回路32が挿入されてい
る。そして、電源ラインと基準電位側端子4との間にa
Ct、前記第1及び第2のスイッチング回路28.32
を制御するためのスイッチング制御回路34が設置され
ている。このスイッチング制御回路34の制御端子36
には、時定数を設置するためのコンデン(4) す38が接続されている。第1及び第2のスイッチング
回路28.32はスイッチング用l−ランジスタ等のス
イッチング素子で構成され、スイッチング制御回路34
の制御出力に基づき〜導通、不導通状態が制御されるも
のである。
FIG. 2 shows an embodiment of the amplifier circuit of the present invention, and the same parts as the circuit of FIG. 1 are designated by the same symbols. In the figure, a first switching circuit 28 is inserted into the power supply line for supplying power to the drive circuit 10, and a constant current source 3 is inserted between the output transistor 8 and the power supply line.
A second switching circuit 32 is inserted through 0. And, between the power supply line and the reference potential side terminal 4,
Ct, said first and second switching circuit 28.32
A switching control circuit 34 is installed for controlling. Control terminal 36 of this switching control circuit 34
A capacitor (4) 38 is connected to the capacitor (4) for setting a time constant. The first and second switching circuits 28 and 32 are composed of switching elements such as switching L-transistors, and the switching control circuit 34
The conduction and non-conduction states are controlled based on the control output.

また、電源端子2には電源スィッチ40を介してバッテ
リ等で構成される電源42が接続されている。
Further, a power source 42 composed of a battery or the like is connected to the power source terminal 2 via a power switch 40.

以上の構成に基づき、その動作を説明する。電源スィッ
チ40が導通状態に置かれると、電源42ば電源ライン
を介してスイッチング制御回路34に与えられる。この
電源42の供給に伴いコンデンサ38には一定の充電電
流が流れ、一定時間経過後、コンデンサ38は一定の電
位に充電される。
The operation will be explained based on the above configuration. When the power switch 40 is placed in a conductive state, a power supply 42 is applied to the switching control circuit 34 via the power supply line. As the power supply 42 is supplied, a constant charging current flows through the capacitor 38, and after a certain period of time, the capacitor 38 is charged to a constant potential.

即ち、電源スィッチ40の導通開始からコンデンサ38
が一定電位に充電されるまでの一定時間において、第1
のスイッチング回路28は不導通状態に制御され、この
間第2のスイッチング回路32は導通状態に制御される
。この場合、出力]・ランジスタ8のヘースには定電流
源30から一定の(5) バイアスが与えられ、出力1−ランジスタ8は導通状態
に制御される。この結果、出力端子16と基準電位側端
子4との間は出力トランジスタ8で短絡され、出力端子
16の電位は基準電位+1lllレベルとほぼ同様のレ
ヘルに維持されることになる。従って1.電源スイツチ
投入時の過渡台の発生を防止するためにスイッチング回
路28を不導通状態に保って駆動回路10の動作を停止
させているにもかかわらず、出力体1子16の直流レヘ
ルば基準電位側レヘルに維持されることから、出力端子
16は非常に低いインピーダンス状態と成り、従来化じ
ていた電源スィッチ40の導通に伴う過渡台や電源リッ
プル等が抵抗12、及びコンデンサ18.20を介して
負荷22に発生ずる不都合を効果的に防止することがで
きる。即ち、従来の異常音の信号電流経路は出力トラン
ジスタ8を介して基準電位側に形成され、負荷22に流
れる異常信号電流が阻止されることに成る。
That is, from the start of conduction of the power switch 40, the capacitor 38
During a certain period of time until the is charged to a certain potential, the first
The second switching circuit 28 is controlled to be non-conductive, and during this period, the second switching circuit 32 is controlled to be conductive. In this case, a constant (5) bias is applied to the base of the output transistor 8 from the constant current source 30, and the output transistor 8 is controlled to be conductive. As a result, the output terminal 16 and the reference potential side terminal 4 are short-circuited by the output transistor 8, and the potential of the output terminal 16 is maintained at approximately the same level as the reference potential +1llll level. Therefore 1. Even though the switching circuit 28 is kept in a non-conducting state to stop the operation of the drive circuit 10 in order to prevent the occurrence of a transient stage when the power switch is turned on, the DC level of the output element 16 remains at the reference potential. Since the output terminal 16 is maintained at a low level, the output terminal 16 is in a very low impedance state, and the transient stage and power ripple caused by the conduction of the conventional power switch 40 are transmitted through the resistor 12 and capacitors 18 and 20. Therefore, inconveniences caused to the load 22 can be effectively prevented. That is, the conventional abnormal sound signal current path is formed on the reference potential side via the output transistor 8, and the abnormal signal current flowing to the load 22 is blocked.

このような構成によれば、低周波電力増幅器の出力回路
においても、ヘソドフォン等の比較的軽(6) い負荷が接続される場合でも、電源ラインからの異常音
の発生を防止できる。
According to such a configuration, even in the output circuit of the low frequency power amplifier, even when a relatively light load such as a hesodophone is connected, abnormal noise can be prevented from being generated from the power supply line.

以上説明したようにこの発明によれば、ブートストラン
プ 源スィッチの投入時における過渡台の発生や電源リップ
ルの漏れ込みを防止できる。
As described above, according to the present invention, it is possible to prevent the occurrence of a transient stage and the leakage of power supply ripples when the bootstrap source switch is turned on.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の増幅回路を示す回路図、第2図はこの発
明の増幅回路の実施例を示す回路図である。 6、8・・・出力I・ランジスタ、IO・・・駆動回路
、28・・・第1のスイッチング回路、32・・・第2
のスイッチング回路、34・・・スイッチング制御回路
。 (7)
FIG. 1 is a circuit diagram showing a conventional amplifier circuit, and FIG. 2 is a circuit diagram showing an embodiment of the amplifier circuit of the present invention. 6, 8... Output I transistor, IO... Drive circuit, 28... First switching circuit, 32... Second
switching circuit, 34... switching control circuit. (7)

Claims (1)

【特許請求の範囲】[Claims] 出力回路をブートストラップ回路で構成した増幅回路に
おいて、前記出力回路を駆動する駆動回路と電源との間
に挿入された第1のスイッチング回路と、前記出力回路
と電源との間に挿入された第2のスイッチング回路と、
電源供給開始から一定時間において第1のスイッチング
回路を導通状態に制御するとともに第2のスイッチング
回路を不導通状態に制御するスイッチング制御回路とを
具備したことを特徴とする増幅回路。
In an amplifier circuit in which an output circuit is configured with a bootstrap circuit, a first switching circuit inserted between a drive circuit that drives the output circuit and a power supply, and a first switching circuit inserted between the output circuit and the power supply. 2 switching circuit;
An amplifier circuit comprising: a switching control circuit that controls a first switching circuit to be in a conductive state and controls a second switching circuit to be in a non-conductive state for a certain period of time from the start of power supply.
JP58020951A 1983-02-10 1983-02-10 Amplifier circuit Pending JPS59147505A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58020951A JPS59147505A (en) 1983-02-10 1983-02-10 Amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58020951A JPS59147505A (en) 1983-02-10 1983-02-10 Amplifier circuit

Publications (1)

Publication Number Publication Date
JPS59147505A true JPS59147505A (en) 1984-08-23

Family

ID=12041495

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58020951A Pending JPS59147505A (en) 1983-02-10 1983-02-10 Amplifier circuit

Country Status (1)

Country Link
JP (1) JPS59147505A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61144904A (en) * 1984-12-19 1986-07-02 Nec Corp Amplifier circuit provided with shock noise preventing circuit at switch-on

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58157204A (en) * 1982-03-15 1983-09-19 Hitachi Ltd Audio amplifier

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58157204A (en) * 1982-03-15 1983-09-19 Hitachi Ltd Audio amplifier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61144904A (en) * 1984-12-19 1986-07-02 Nec Corp Amplifier circuit provided with shock noise preventing circuit at switch-on
JPH0516686B2 (en) * 1984-12-19 1993-03-05 Nippon Denki Kk

Similar Documents

Publication Publication Date Title
JP2541585B2 (en) Reset signal generation circuit
JP4158285B2 (en) Electric load drive
EP0570655A1 (en) Audio amplifier on-off control circuit
JPH041992A (en) Semiconductor memory device
JP3538480B2 (en) Power supply switching circuit
JP3314473B2 (en) Power MOSFET control device
JPS59147505A (en) Amplifier circuit
JPS59154805A (en) Amplifier circuit
JP4204119B2 (en) Switching device for switching inductive loads
JP2001177387A (en) Load driver
JP4043835B2 (en) Pop sound prevention circuit
JPS6339162B2 (en)
JPH0221686B2 (en)
JP5303927B2 (en) Switching power supply circuit
JPS6122345Y2 (en)
JPH0351334B2 (en)
JP3429969B2 (en) Bias circuit
JP3271269B2 (en) Output drive circuit
JPS6226265B2 (en)
JPH09163720A (en) Semiconductor device
JP3421594B2 (en) DC-DC converter
JP3764597B2 (en) Switch device
JPH05114853A (en) Low-noise output driving circuit
JPS6021625A (en) Output circuit
JPS60123111A (en) Amplifiying circuit