JP3429969B2 - Bias circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bias circuit for obtaining a predetermined voltage output suitable for use in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit configured between a power supply VCC and a reference potential (hereinafter referred to as GND), as means for obtaining a voltage output between the power supply VCC and the GND potential,
Normally, the bias circuit shown in FIGS. 10 and 11 is used.

In FIG. 10, a resistor R1 and a resistor R2 are connected in series between a power supply VCC and GND, and an output terminal OUT is taken out from the connection point. In this case, the resistance R1
It is possible to obtain a voltage-divided output of the power supply VCC voltage that is determined by the resistance ratio setting between the resistor R2 and the resistor R2.

In FIG. 11, the gate and drain of a PMOS transistor P9 whose source is connected to a power supply VCC and an NMOS transistor N6 whose source is connected to GND are commonly connected, and the common connection point is the output terminal OUT.
I am trying. In this case, the output terminal OUT voltage is PM
It is possible to obtain a divided voltage output according to the transistor size W / L ratio setting of the OS transistor P9 and the NMOS transistor N6. Here, W represents the channel width of the MOS transistor, and L represents the channel length.

[0005]

In both of the conventional examples shown in FIGS. 10 and 11, a DC path is formed between the power supplies VCC and GND, and a DC bias current always flows from the power supply VCC toward GND. When such a bias circuit is used in, for example, a CMOS-configured microcomputer module,
There are the following problems. That is, when the microcomputer system operates at high speed, the overall average current consumption Iop due to the through current in the CMOS gate and the charge / discharge current component of the gate capacitance of the next stage also becomes relatively large. It is sufficient to set the current, but in the case of low speed operation, the average current consumption Iop decreases in proportion to the operating frequency, so the ratio of the DC bias current to the average current consumption of the entire microcomputer system increases. . This is because the DC bias current does not depend on the operating frequency and is determined by the power supply VCC voltage and the impedances of the resistors R1, R2, etc. On the other hand, the average current consumption by the CMOS gate configuration is basically expressed by C × V × f. It depends. Where C is the load capacitance such as the gate capacitance of the next stage, V
Is the applied power supply voltage, and f is the operating frequency.

If it is desired to suppress the overall average current consumption during low-speed operation to about several μA, the resistors R1, R2, etc. in FIG. 10 need to have an impedance of the order of MΩ in order to suppress the bias current. This is a resistance value that is difficult to form on a semiconductor chip, which is disadvantageous in terms of chip area and cost.

An object of the present invention is to provide a bias circuit which can reduce the bias current during the low speed operation and can be easily integrated on a semiconductor chip.

[0008]

The above object is to provide a capacitor having one end connected to a power source (or GND) side, a discharge switch connected in parallel to the capacitor, and a voltage generator connected in series to the capacitor. And a charging switch connected to the GND (or power supply) side, the connection point between the charging switch and the voltage generating means is used as an output, and the discharging switch and the charging switch are supplied by a signal such as a system clock. This is achieved by performing the exclusive operation and allowing the charging current of the capacitor to flow to the voltage generating means when the charging switch is turned on. It should be noted that the same operation can be obtained even if the connection positions of the capacity and the charging switch in the above configuration are exchanged. In that case, the connection point between the capacitance and the voltage generating means becomes the output.

Further, the above-mentioned object is to provide a power source (or GN) at one end.
A capacitor connected to the D) side, a discharge switch having one end connected to the capacitor and connected to the power source (or GND) side through a voltage generating means, one end to the capacitor and the other end to the GND (or A charging switch connected to the power supply side is provided, the connection point between the voltage generating means and the discharging switch is used as an output, and the discharging switch and the charging switch are exclusively operated by a signal such as a system clock in the same manner as above. It is also achieved by allowing the discharge current of the capacity to flow to the voltage generating means when the discharge switch is turned on.

The output in the above configuration is a MOS.
It is assumed that a high impedance load such as a gate of a transistor is connected in terms of direct current.

By alternately turning on the charging switch and the discharging switch, the capacitance is alternately charged / discharged. The charging current or discharging current of the capacitor flows at the moment when the charging switch or the discharging switch is turned on, that is, when the control signal such as the system clock is inverted, and becomes 0 when the charging or discharging is completed.

The above charging current (or discharging current) flows through the voltage generating means connected in series with the charging switch (or discharging switch) and becomes a bias current for the voltage generating means. Here, if the voltage generating means is composed of, for example, a MOS transistor whose gate and drain are short-circuited, and the bias current is made to flow between its drain and source, the voltage across the voltage generating means when the bias current flows becomes It corresponds to the gate-source voltage VGS of the MOS transistor. The bias current is relatively small,
Alternatively, if the conductance of the MOS transistor is large, the VGS becomes a voltage substantially equal to the threshold voltage Vth of the MOS transistor. Therefore, the load capacitance such as the gate of the MOS transistor connected to the output is charged to the output voltage Vth.

When the charging (or discharging) of the capacity is completed and the bias current of the voltage generating means is exhausted, the charged electric charge of the load capacity connected to the output tends to be discharged through the voltage generating means. However, since the output voltage is originally charged near the threshold voltage Vth of the MOS transistor,
The discharge current is due to leakage current in the so-called subthreshold region of the MOS transistor in the voltage generating means. Therefore, its discharge time constant is much larger than the control signal cycle of the system clock, etc., so the output voltage component that drops by the discharge before the supply of the bias current in the next cycle is very small, and the output voltage level remains almost constant. Can be maintained. For example, assuming that the leak current is 100 pA and the output load capacitance is about 1 pF, the output voltage drop due to this leak current is 100 pA.
It has a slope of A ÷ 1 pF = 0.1 mV / μs. Therefore, even when controlled by a low-speed system clock of about 10 kHz, for example, the output voltage drop until the bias current is supplied in the next cycle is about 0.1 mV / μs × 100 μs = 10 mV.

As described above, since the bias current of the voltage generating means is not supplied constantly but is supplied by using the charge or discharge current of the capacitor, the bias current flows only when the control signal is switched. As the operating frequency is lower, the average current consumption due to the bias current can be reduced. Further, since the capacitance can be formed by utilizing the gate capacitance or the like of a normal MOS transistor, it is extremely easy to integrate the above circuit configuration on the semiconductor chip.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, a capacitor CB having one end connected to the power supply VCC, a charging PMOS transistor P2 connected between the other end of the capacitor CB and the output terminal OUT, and a discharging PMOS transistor connected in parallel with the capacitor CB. P1
A voltage generating means A connected between the output terminal OUT and GND, an inverter G2 having its output connected to the gate of the charging PMOS transistor P2, and an input of the inverter G2 and a gate of the discharging PMOS transistor P1. An inverter G1 having an output connected to the input terminal IN is provided, and the output terminal OUT is connected to the gate of the NMOS transistor ND as a load. Further, the voltage generating means A is composed of an NMOS transistor NL1 in which the drain and the gate are short-circuited and the output terminal OUT is connected to the source to the GND. The inverters G1 and G2 are PMO for discharge.
S transistor P1 and charging PMOS transistor P2
Are provided for exclusive operation of and, and do not form an essential constituent element of the present invention, and other circuit configurations may be used as long as the above exclusive operation is possible. The same applies to other embodiments described below.

The operation of this embodiment will be described below.

First, when a high level input voltage is applied to the input terminal IN, the output of the inverter G1 is low.
, The output of the inverter G2 becomes high level, so the discharging PMOS transistor P1 is turned on and the discharging PMOS transistor P1 is turned on.
The transistor P2 is in the OFF state. At this time, the capacitance CB is in the discharging state because the voltage difference between both ends becomes 0 due to the power supply VCC voltage due to the turning on of the discharging PMOS transistor P1. Also for charging PMO
Since the S transistor P2 is in the OFF state, the power source VC
No bias current flows from C to the voltage generating means A.

Next, when the input voltage at the input terminal IN becomes low level, the output of the inverter G1 becomes high and the output of the inverter G2 becomes low level. Therefore, contrary to the above, the discharge PMOS transistor P1 is turned off and the charging PMOS transistor P1 is turned off.
The transistor P2 is turned on. When the charging PMOS transistor P2 is turned on, the charging PMO of the capacitor CB is charged.
The terminal potential on the S transistor P2 side decreases from the power supply VCC potential to the output terminal OUT side potential. This decrease in the terminal potential of the capacitor CB causes a potential difference between both terminals of the capacitor CB, and the capacitor CB is in a charged state. The charging current flowing at this time is from the power source VCC to the capacity CB and charging PMO.
Although it flows to the voltage generating means A side through the S transistor P2, the output terminal OUT potential is the threshold voltage V of the NMOS transistor NL1 in the voltage generating means A.
If it is less than th, the NMOS transistor NL1 is in the cutoff state, so that the stray capacitance component connected to the output terminal OUT, that is, the gate of the NMOS transistor NL1 and the gate of the NMOS transistor ND are charged by the above charging current, and output. The voltage at the terminal OUT rises.
When the voltage of the output terminal OUT reaches the threshold voltage Vth of the NMOS transistor NL1, the NMOS transistor NL1 becomes active and the charging current is GND.
Bypassing to the side, the voltage increase of the output terminal OUT is suppressed. At this point, the voltage of the output terminal OUT is almost stable, so that the terminal voltage of the capacitor CB is also stable, the charging operation is completed, and the charging current is attenuated. Although the charging current disappears in due course, the output terminal OUT voltage biased once near the threshold voltage Vth of the NMOS transistor NL1 as described above, even if the charging current, that is, the bias current to the voltage generating means A, disappears,
Since there is no discharge path other than the discharge due to the leak current in the subthreshold region of the NMOS transistor NL1, its discharge time constant is extremely large, and therefore the potential fluctuation until the next charge cycle can be suppressed small. Specific examples of numerical values are as described above.

Next, when the input voltage of the input terminal IN becomes high level, the discharging PMOS transistor P1 is turned on and the charging transistor P2 is turned off in the same manner as in the initial state, and the voltage across the capacitor CB becomes the power supply VCC voltage and discharge occurs. The action is taken. The discharge of this capacity CB is
It is performed in a closed loop of B and the discharging PMOS transistor P1, and there is no current supply from the power supply VCC. Although the bias current supply path to the voltage generating means A side is cut off by turning off the charging transistor P2, the potential of the output terminal OUT is maintained near the threshold voltage Vth of the NMOS transistor NL1 as described above.

Furthermore, the input voltage at the input terminal IN is low again.
At the level, the discharge PMOS transistor P1 becomes O
The FF and the charging transistor P2 are turned on, and the charging current of the capacitor CB again flows to the voltage generating means A side. As a result, the charge accumulated in the output terminal OUT portion, which has been lost by the discharge due to the leak current, is replenished, and the state at the time of the previous charge of the capacitor CB is restored.

By applying a periodic pulse such as a system clock to the input terminal IN, the above operation is repeated, and as a result, the potential of the output terminal OUT is in the vicinity of the threshold voltage Vth of the NMOS transistor NL1 in the voltage generating means A. The electric potential will be maintained. Also, the capacity C
Since the charging current of B serves as the bias current source of the voltage generating means A, the bias current flows only when the input pulse of the input terminal IN transits. Therefore, the lower the input pulse frequency, the more the average current consumption thereof. Get smaller.

In FIG. 1, if the source of the NMOS transistor ND whose gate is connected to the output terminal OUT is connected to GND, the gate-source voltage VGS of the NMOS transistor ND is close to the threshold voltage Vth of the NMOS transistor NL1 in the voltage generating means A. Will be biased to. Therefore, when a load circuit is connected to the drain of the NMOS transistor ND, the current flowing through the load circuit, that is, the drain current of the NMOS transistor ND can be suppressed, and a minute bias current is required from the viewpoint of low power consumption. A bias circuit suitable as a bias source for the load circuit can be obtained.

As described above, according to the present embodiment, it is possible to obtain a bias circuit in which a DC bias current does not flow and the current consumption during low speed operation can be suppressed low. Further, by using the bias voltage output, a current bias circuit in which the output current is suppressed can be easily obtained.

The discharging PMOS transistor P1 and the charging PMOS transistor P2 in this embodiment may be replaced with another structure, for example, an NMOS transistor, as long as they have a function as a switch. As for the configuration of the voltage generating means A, it is sufficient if it has a characteristic that it has a high impedance when the potential of the output terminal OUT is equal to or lower than the threshold voltage thereof, and may be constituted by, for example, a diode or a PMOS transistor. In the case of a diode, the anode is the output terminal OUT
Side and the cathode are connected to the GND side, and the output voltage is the forward voltage drop (FVD). In the case of a PMOS transistor, the source is connected to the output terminal OUT side and the gate / drain is connected to the GND side. As in the case of the NMOS transistor NL1, the output voltage becomes a voltage near the threshold voltage Vth of the PMOS transistor.

A second embodiment of the present invention is shown in FIG. This embodiment is the same as the first embodiment shown in FIG. 1 except for the configuration of the voltage generating means A.
The configuration is the same as that of the embodiment.

In FIG. 2, the voltage generating means A is a gate
N NMOS transistors NL1 whose drains are short-circuited
To NLn are connected in series, and the direction from the output terminal OUT to GND is the energizing direction, like the NMOS transistor NL1 in the embodiment of FIG.

The operation of this embodiment is similar to that of the first embodiment, but the charging current of the capacitor CB is n NMO.
Since it flows into the S transistors NL1 to NLn, the voltage appearing at the output terminal OUT is n times the threshold voltage Vth of one NMOS transistor.

As described above, according to this embodiment, in addition to the effect of the first embodiment, it is possible to obtain the bias circuit capable of multiplying the output voltage by n times.

A third embodiment of the present invention is shown in FIG.

In FIG. 3, a capacitor CB having one end connected to GND, a charging NMOS transistor N2 connected between the other end of the capacitor CB and the output terminal OUT, and a capacitor C
A discharge NMOS transistor N1 connected in parallel with B,
A voltage generating means A connected between the output terminal OUT and the power supply VCC, an inverter G2 having its output connected to the gate of the charging NMOS transistor N2, and an inverter G2.
Of the input and the discharge NMOS transistor N1 is provided with the output thereof, and the input terminal IN thereof is connected with the inverter G1 thereof, and the output terminal OUT is connected with the gate of the PMOS transistor PD as a load. The voltage generating means A is composed of a PMOS transistor PL1 in which the drain and the gate are short-circuited to connect to the output terminal OUT and the source to the power supply VCC.

The operation of this embodiment will be described below.

Similar to the first embodiment, the discharging NMOS transistor N1 and the charging NMOS transistor N2 operate exclusively by a control signal such as a system clock input to the input terminal IN. First, the discharging NMOS transistor N1 side is ON, and the charging NMOS transistor N is
When the second side is OFF, the voltage across the capacitor CB is at the GND potential, and the capacitor CB is in the discharged state. NM for charging
Power supply VCC because the OS transistor N2 is off
The current path from is blocked.

Subsequently, when the discharging NMOS transistor N1 side is turned off and the charging NMOS transistor N2 side is turned on, a charging current for the capacitor CB flows from the power supply VCC through the PMOS transistor PL1 in the voltage generating means A. As a result, the output terminal OUT potential changes from the power supply VCC potential to PM.
The potential rises to the potential lowered by the threshold voltage Vth of the OS transistor PL1, and the stray capacitance connected to the output terminal OUT portion is charged to that voltage. Since the gate-source voltage VGS of the PMOS transistor PL1 at the time when the charging operation is completed and the charging current disappears is almost at the threshold voltage Vth, the potential of the output terminal OUT thereafter rises.
Although it depends on the leakage current in the sub-threshold region of No. 1, the charging time constant due to the leakage current is extremely large as described above, and therefore the fluctuation of the potential of the output terminal OUT becomes very slight.

Then, the first state, that is, NMO for discharge
When the S-transistor N1 side is turned on and the charging NMOS transistor N2 side is turned off, the charged charge of the capacitor CB is NM.
It is discharged by the OS transistor N1. Output terminal O
The electric charge charged in the UT part is the PMOS transistor PL
There is no charge / discharge path other than that due to the leak current of No. 1, and therefore the potential of the output terminal OUT maintains the almost previous state.

When the discharging NMOS transistor N1 side is turned off and the charging NMOS transistor N2 side is turned on again, the excess electric charge charged in the output terminal OUT portion due to the leak current of the PMOS transistor PL1 is discharged to the capacitance CB side and the PMOS. Transistor PL1
A charging current of the capacitor CB flows through the output terminal OUT, and the output terminal OUT potential returns to the previous charging state.

If a periodic pulse such as a system clock is applied to the input terminal IN and the above operation is repeated, the output terminal O
The UT has a power supply VCC to a PMOS transistor PL.
It is possible to obtain a voltage output reduced by the threshold voltage Vth of 1.

According to the present embodiment, it is possible to obtain the bias circuit which has the effect of reducing the average current consumption regarding the bias current as in the first embodiment and has the voltage output with the power supply VCC side as the reference. If the source of the PMOS transistor PD whose gate is connected to the output terminal OUT is connected to the power supply VCC, its gate-source voltage VGS is P
Since it is biased in the vicinity of the threshold voltage Vth of the MOS transistor PL1, the drain current of the PMOS transistor PD is suppressed. Therefore, if the drain of the PMOS transistor PD is used as the output terminal, a current bias circuit with suppressed output current can be easily obtained. be able to.

A fourth embodiment of the present invention is shown in FIG.

In the configuration of the embodiment shown in FIG. 4, the PMOS transistor P3 as a voltage generating means is inserted in series with the discharging PMOS transistor P1 in the configuration of the embodiment shown in FIG.
The discharge of the capacitor CB is performed by discharging PMOS transistors P1 and P
This is done in a closed loop of the MOS transistor P3 and the capacitor CB. As a result, when the capacitance CB is discharged, the potential difference between the ends of the capacitance CB changes to the PMOS transistor P3.
Since the threshold voltage Vth is kept open for about that amount of electric charge, the amount of electric charge is saved, and the amount of electric charge charged from the power supply VCC during the charging operation can be reduced.

According to the present embodiment, in addition to the effect of the first embodiment, it is possible to obtain the bias circuit which can further reduce the average current consumption due to the bias current. In FIG. 4, the PMOS transistor P3 is used as the voltage generating means.
Although the configuration of one stage is shown, a plurality of stages connected in series may be inserted. Another device such as a diode may be used as long as a potential difference is generated across the capacitance CB and the potential difference across the capacitance CB can be kept open when the capacitance CB is discharged. Further, it goes without saying that the structure of this embodiment can be used in combination with other embodiments.

A fifth embodiment of the present invention is shown in FIG.

In FIG. 5, one end is connected to GND and the other end is connected to the power supply VCC through the charging PMOS transistor P4.
To the discharge PMOS transistor P5 connected between the output terminal OUT and the connection point between the capacitor CB and the charging PMOS transistor P4, and the output terminal O.
A voltage generating means A connected between UT and GND; an inverter G2 having its output connected to the gate of a charging PMOS transistor P4; and its output to the input of the inverter G2 and the gate of a discharging PMOS transistor P5.
An inverter G1 having its inputs connected to an input terminal IN, and an output terminal OUT having a load N
The gate of the MOS transistor ND is connected. Further, the voltage generating means A is composed of an NMOS transistor NL1 in which the drain and the gate are short-circuited and the output terminal OUT is connected to the source to the GND.

The operation of this embodiment will be described below.

Also in this embodiment, like the other embodiments described above,
The charging PMOS transistor P4 and the discharging PMOS transistor P5 operate exclusively by a control signal such as a system clock input to the input terminal IN. First, the charging PMOS transistor P4 side is ON, and the discharging PMOS
When the transistor P5 side is OFF, a charging current flows from the power supply VCC to the capacitor CB via the PMOS transistor P4, and the capacitor CB is charged to the power supply VCC voltage. Further, since the discharging PMOS transistor P5 is off, no bias current flows to the voltage generating means A side.

Next, when the charging PMOS transistor P4 side is turned off and the discharging PMOS transistor P5 side is turned on, a discharging current flows from the capacitor CB to the NMOS transistor NL1 in the voltage generating means A through the discharging PMOS transistor P5, and the output terminal OUT potential. Is biased near the threshold voltage Vth of the NMOS transistor NL1. After discharging the capacitor CB, output terminal O
The charge of the UT section is discharged by the NMOS transistor NL1.
The leakage current in the sub-threshold region of the output terminal OU is generated even if the discharge current of the capacitor CB disappears.
The T potential is maintained near the threshold voltage Vth of the NMOS transistor NL1.

Continuing, the charging PMOS transistor P4
Side is ON, discharge PMOS transistor P5 side is OFF
Then, the capacitor CB is charged to the power supply VCC voltage again.
Further, since the discharging PMOS transistor P5 is off, no bias current flows to the voltage generating means A side,
As described above, the output terminal OUT potential is maintained.

Further, the charging PMOS transistor P is again used.
4 side is OFF, discharge PMOS transistor P5 side is O
Then, the discharge current of the capacitor CB again flows into the NMOS transistor NL1 to compensate the discharge charge due to the leak current, and as a result, the output terminal OUT potential is N
The biased state of the MOS transistor NL1 is maintained in the vicinity of the threshold voltage Vth.

As described above, the charging PMOS transistor P
4 and the discharge PMOS transistor P5 are exclusively operated, the bias voltage output similar to that of the first embodiment can be obtained.

According to this embodiment, it is possible to obtain a bias circuit having the same effect as that of the first embodiment.

A sixth embodiment of the present invention is shown in FIG.

In FIG. 6, one end is connected to the power supply VCC and the other end is connected to GND via the charging NMOS transistor N3.
A discharge PMOS transistor P6 connected between an output terminal OUT and a connection point between the capacitor CB and the charging NMOS transistor N3, and an output terminal O.
Voltage generating means A connected between the UT and the power supply VCC;
An inverter G2 having its output connected to the gate of the charging NMOS transistor N3, and an inverter G1 having its input connected to the input of the inverter G2 and the gate of the discharging PMOS transistor P6 and its input connected to the input terminal IN are provided. The gate of the PMOS transistor PD is connected to the output terminal OUT as a load. The voltage generating means A is composed of a PMOS transistor PL1 in which the drain and the gate are short-circuited to connect to the output terminal OUT and the source to the power supply VCC.

The operation of this embodiment will be described below.

In this embodiment, as in the other embodiments, the charging NMOS transistor N3 and the discharging PMOS transistor P6 operate exclusively to alternately charge and discharge the capacitor CB. First, the charging NMOS transistor N3 side is turned on
Then, the connection terminal of the capacitor CB on the side of the charging NMOS transistor N3 is pulled down to the GND potential, and the potential difference between both ends of the capacitor CB becomes the potential difference between the power supplies VCC and GND to enter the charging state. At this time, the discharging PMOS transistor P6 is O
Since it is FF, the bias current of the voltage generating means A does not flow.

Next, when the discharging PMOS transistor P6 side is turned on, the capacitance CB is discharged by the closed loop of the voltage generating means A, the discharging PMOS transistor P6 and the capacitance CB. PMOS transistor P in the voltage generating means A
When the discharge current of the capacitor CB flows through L1, its gate-source voltage VGS becomes about the threshold voltage Vth of the PMOS transistor PL1, and therefore the output terminal OUT potential from the power supply VCC to the above threshold voltage Vth.
The potential drops by a minute. Even if the discharge of the capacitor CB is completed and the discharge current disappears, there is no leak path other than the PMOS transistor PL1 with respect to the output terminal OUT portion, so that the potential is maintained as in the other embodiments.

Then, when the charging NMOS transistor N3 side is turned on, the state returns to the initial charging state. However, the output terminal OUT potential maintains the above potential. After that, discharge PM
By alternately repeating the ON operation of the OS transistor P6 side and the charging NMOS transistor N3 side, the above potential is maintained as the output terminal OUT potential. According to this embodiment, it is possible to obtain a bias circuit having the same effect as that of the third embodiment.

A seventh embodiment of the present invention is shown in FIG.

In FIG. 7, one end is connected to the power supply VCC via the charging PMOS transistor P7, and the other end is connected to GND via the voltage generating means A, and a capacitor C and a capacitor C.
A discharge PMOS transistor P8 connected in parallel to B,
An inverter G2 having its output connected to the gate of the charging PMOS transistor P7, and an inverter G1 having its input connected to the input of the inverter G2 and the gate of the discharging PMOS transistor P8 and its input connected to the input terminal IN are provided. The gate of the NMOS transistor ND is connected to the output terminal OUT as a load.
Further, the voltage generating means A is composed of an NMOS transistor NL1 in which the drain and the gate are short-circuited and the output terminal OUT is connected to the source to the GND.

FIG. 7 has a configuration in which the connection positional relationship between the capacitor CB and the charging PMOS transistor P2 in the configuration of the first embodiment shown in FIG. 1 is replaced, and its operation is the same as in the case of FIG. Is. That is, the charging PMOS transistor P7 and the discharging PMOS transistor P8 operate exclusively, and when the charging PMOS transistor P7 side is turned on, the charging current of the capacitor CB flows from the power supply VCC, whereby the output terminal OUT potential becomes the NMOS transistor NL1.
Is biased to about the threshold voltage Vth. When the discharging PMOS transistor P8 side is turned on, the capacitance CB
Both ends are short-circuited and the capacitance CB is discharged. Since this discharge current flows in the closed loop of the discharging PMOS transistor P8 and the capacitor CB, it does not affect the output terminal OUT potential. At this time, since the charging PMOS transistor P7 is off, the bias current is not supplied to the NMOS transistor NL1 in the voltage generating means A, but the NMOS transistor NL1.
Since there is no discharge path other than the leakage current of
The UT potential is maintained.

According to this embodiment, it is possible to obtain a bias circuit having the same effect as that of the first embodiment.

The eighth embodiment of the present invention is shown in FIG.

In FIG. 8, one end is connected to GND via the charging NMOS transistor N5 and the other end is connected to the power supply VCC via the voltage generating means A, and a capacitor C
A discharge NMOS transistor N4 connected in parallel with B,
An inverter G2 having its output connected to the gate of the charging NMOS transistor N5, and an inverter G1 having its output connected to the input of the inverter G2 and the gate of the discharging NMOS transistor N4 and its input connected to the input terminal IN are provided. The gate of the PMOS transistor PD is connected to the output terminal OUT as a load.
The voltage generating means A is composed of a PMOS transistor PL1 in which the drain and the gate are short-circuited and the output terminal OUT is connected, and the source is connected to the power supply VCC.

FIG. 8 shows a configuration in which the connection positional relationship between the capacitor CB and the charging NMOS transistor N2 in the configuration of the third embodiment shown in FIG. 3 is exchanged, and its operation is as shown in FIG.
It is similar to the case of. That is, the charging NMOS transistor N5 and the discharging NMOS transistor N4 perform an exclusive operation, and when the charging NMOS transistor N5 side is turned on, one end of the capacitor CB is biased to the GND potential and the power supply VCC causes the PMOS transistor PL in the voltage generating means A.
The charging current of the capacitor CB flows through 1. As a result, the potential of the output terminal OUT is biased to a potential lowered from the power supply VCC by the threshold voltage Vth of the PMOS transistor PL1. When the discharging NMOS transistor N4 side is turned on, both ends of the capacitor CB are short-circuited and the capacitor CB is discharged. This discharge current is the discharge NMOS transistor N
4 and the capacitor CB flow in a closed loop, so there is no effect on the output terminal OUT potential. At this time, since the charging NMOS transistor N5 is off, the PM in the voltage generating means A is PM.
Although the bias current is not supplied to the OS transistor PL1, the potential of the output terminal OUT is maintained because there is no charge / discharge path other than the leak current of the PMOS transistor PL1.

According to this embodiment, it is possible to obtain a bias circuit having the same effect as that of the third embodiment.

A ninth embodiment of the present invention is shown in FIG.

In FIG. 9, the drain is connected to the power supply VCC.
Depletion type NMOS transistor DM whose source is connected to output terminal OUTD, and output terminal OUTD
And a load circuit B connected between GND and GND,
The gate of the depletion type NMOS transistor DM has an output terminal O of the bias circuit in the embodiment shown in FIG.
It is connected to the UT.

In this case, the threshold voltage of the depletion type NMOS transistor DM is Vthd, and the output terminal O
If the UT voltage, that is, the gate voltage of the depletion type NMOS transistor DM is used as the threshold voltage Vth of the NMOS transistor NL1 in the voltage generating means A, the output terminal OUTD potential is almost | Vthd | + regardless of the power supply VCC voltage.
It will be clamped to Vth. The clamp is of course the power supply VCC voltage ≧ | Vthd | + Vth
It is effective in the range of. The applied voltage to the load circuit B is suppressed to the clamp voltage | Vthd | + Vth, which is an extremely effective means in terms of low power consumption.

Normally, the gate of the depletion type NMOS transistor DM is biased to GND and used.
In that case, the clamp voltage becomes | Vthd |. In order to adjust this clamp voltage or to set a plurality of voltages, it is necessary to have several threshold voltages of the depletion type NMOS transistor DM, but the threshold voltage of the depletion type NMOS transistor DM is determined by the manufacturing process conditions. However, it is not preferable to have several threshold voltage settings in terms of manufacturing cost.

According to this embodiment, since the clamp voltage by the depletion type NMOS transistor DM can be shifted by the output voltage of the voltage generating means A as described above, the voltage generating means A as shown in FIG. With this configuration, it is possible to obtain a bias circuit that enables setting of a desired clamp voltage. Further, it goes without saying that the gate bias circuit of the depletion type NMOS transistor DM has the same effect as that of the first embodiment.

[0070]

According to the present invention, the capacitance CB flowing only at the transition of the control signal without using the DC bias current.
Since the charging or discharging current is used as the bias current source, the conduction duty can be reduced as the operation speed becomes slower, and a bias circuit that is extremely effective in reducing the average current consumption due to the bias current can be obtained.

Further, according to the present invention, since the average current consumption due to the bias current can be reduced as described above, it can be equivalently regarded as a high-impedance reference current source, and the output of the MOS transistor whose gate is connected to the output terminal OUT. It is possible to obtain a bias circuit suitable for suppressing the current.

Further, according to the present invention, the depletion type MO
It is possible to obtain a bias circuit that can adjust the clamp voltage output setting without changing the threshold voltage setting of the depletion type MOS transistor while achieving reduction of average current consumption related to the gate bias of the S transistor.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a fourth exemplary embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a sixth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a seventh embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of an eighth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a configuration of a ninth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a conventional configuration.

FIG. 11 is a circuit diagram showing a conventional configuration.

[Explanation of symbols]

CB ... Capacitance, P1 to P9, PL1 ... PMOS transistor, N1 to N6, NL1 to NLn ... NMOS transistor, A ... Voltage generating means, VCC ... Power supply, OUT, OUT
D ... Output terminal, IN ... Input terminal, G1, G2 ... Inverter.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Junichi Kono 3-1, 1-1 Sachimachi, Hitachi City, Ibaraki Hitachi Ltd. Hitachi factory (56) Reference JP-A-2-146189 (JP, A) Kaihei 4-255109 (JP, A) JP-A 1-186163 (JP, A) JP-A 63-232455 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03K 19 / 00 H03K 19/094 H03K 19/096

Claims (8)

(57) [Claims] 1. A serial connection between a first power supply terminal and an output terminal.
The first switching element and the capacitor connected to each other, the second switching element connected in parallel to the capacitor, and the output terminal and the second power supply terminal are connected to each other, and
The voltage between the input terminal and the second power supply terminal is less than or equal to a predetermined voltage.
When the impedance of the
A bias circuit having a voltage generating means having a characteristic higher than that of the impedance, and a voltage output is obtained from the output terminal by exclusively operating the first switching element and the second switching element. 2. The voltage generating means has a MOS transistor having a gate and a drain short-circuited, and a current flowing direction thereof is a forward direction of a charging current of the capacitance flowing when the first switching element is turned on. The bias circuit according to claim 1, wherein the bias circuit is connected between the first switching element and the second power supply terminal. 3. The voltage generating means includes a plurality of MOS transistors whose gates and drains are short-circuited, and the energizing direction of each MOS transistor is such that the charging current of the capacitance flowing when the first switching element is turned on. 2. The bias circuit according to claim 1, wherein the bias circuit is configured to be connected in series between the first switching element and the second power supply terminal so that the direction is a forward direction. 4. A series connection is provided between the first power supply terminal and the output terminal.
A continuous capacitance and a first switching element, a first voltage generating means connected in parallel with the capacitance via the second switching element, and a first voltage generation means connected between the output terminal and the second power supply terminal. 2 voltage generating means is provided, and the first switching element and
The second switching element is operated exclusively and the output is
A bias circuit characterized by obtaining a voltage output from a force terminal . 5. A capacitor having one end connected to a first power supply terminal through a first switching element and the other end connected to a second power supply terminal, and connected between one end of the capacitor and an output terminal. And a second switching element connected between the output terminal and the second power supply terminal ,
The voltage between the output terminal and the second power supply terminal is less than a predetermined voltage.
If the impedance at the bottom is equal to or higher than the specified voltage,
A bias circuit comprising: a voltage generating unit having a characteristic higher than impedance , wherein the first switching element and the second switching element are exclusively operated to obtain a voltage output from the output terminal . 6. A direct line between the first power supply terminal and the first potential point.
A column-connected capacitor and a first switching element, and a capacitor connected in parallel with the capacitor, and the first switching element
A second switching element whose exclusive operation is controlled, a voltage generating means connected between the first potential point and a second power supply terminal, and a depletion type M having a gate connected to the first potential point .
The depletion type M has an OS transistor and is a power source for driving a load circuit.
A bias circuit connected to the drain side of an OS transistor and the load circuit connected to the source side of the depletion type MOS transistor. 7. The second voltage generating means according to claim 4, wherein the impedance when the voltage between the output terminal and the second power supply terminal is equal to or lower than a predetermined voltage is higher than the impedance when the voltage is equal to or higher than the predetermined voltage. Bias circuit with high characteristics. 8. The method of claim 6, wherein the voltage generating means,
A bias circuit having a characteristic that impedance when a voltage between the first potential point and the second power supply terminal is a predetermined voltage or lower is higher than impedance when the voltage is a predetermined voltage or higher.