JPS59144176A - Method of producing rectifier - Google Patents

Method of producing rectifier

Info

Publication number
JPS59144176A
JPS59144176A JP58154242A JP15424283A JPS59144176A JP S59144176 A JPS59144176 A JP S59144176A JP 58154242 A JP58154242 A JP 58154242A JP 15424283 A JP15424283 A JP 15424283A JP S59144176 A JPS59144176 A JP S59144176A
Authority
JP
Japan
Prior art keywords
semiconductor structure
rectifying element
heat sink
silver
diffusion welding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58154242A
Other languages
Japanese (ja)
Inventor
エリク・ロベルトウイツチ・ガリンスキ−
ウラジミ−ル・ビクトロウイツチ・ズンベロフ
エドウアルド・ゲルマノウイツチ・カルポフ
オレグ・ミハイロウイツチ・コロルコフ
ビクトル・レオニドウイツチ・クズミン
ゲンナジ−・ニコラエウイツチ・スルゼンコフ
グンナ−ル・カルロウイツチ・トムソ−
エフイム・ダビドウイツチ・フトルヤンスキ−
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NAUCHINOOISUREDOWAACHIERUSUKII I PUROEKUTONOOCHIEFUNOROGIICHIESUKII INST SYSTEM PURANIROWANIA I UPURAFURENIA BEE
NI I PUROEKUTONOOCHIEFUNOROGII
Original Assignee
NAUCHINOOISUREDOWAACHIERUSUKII I PUROEKUTONOOCHIEFUNOROGIICHIESUKII INST SYSTEM PURANIROWANIA I UPURAFURENIA BEE
NI I PUROEKUTONOOCHIEFUNOROGII
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NAUCHINOOISUREDOWAACHIERUSUKII I PUROEKUTONOOCHIEFUNOROGIICHIESUKII INST SYSTEM PURANIROWANIA I UPURAFURENIA BEE, NI I PUROEKUTONOOCHIEFUNOROGII filed Critical NAUCHINOOISUREDOWAACHIERUSUKII I PUROEKUTONOOCHIEFUNOROGIICHIESUKII INST SYSTEM PURANIROWANIA I UPURAFURENIA BEE
Publication of JPS59144176A publication Critical patent/JPS59144176A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492Bases or plates or solder therefor
    • H01L23/4924Bases or plates or solder therefor characterised by the materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026Bonding areas specifically adapted for layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
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    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)
  • Rectifiers (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Thyristors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は整流素子の製造方法に関するもので、%にプレ
スによって作られたタブやビンを有する電力用半導体装
置における金属被覆とコンタクト接続を与えるのに使用
されるものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing rectifying elements, which are used to provide metallization and contact connections in power semiconductor devices having tabs or bottles made by pressing. be.

整流素子の製造方法についての従来技術としては半導体
構造の2つの対向する面にニッケル等の金属を化学的に
堆積することによって金属被覆(めっき)し、その上に
シリコンに近い熱衝張係数を有したモリブデン、タング
ステンおよびこれらの・δ金などの材料でできたヒート
シンクを半導体構造の一方の面にはんだ付等の液相状態
で接合したものが知られている(ソビエト連邦発明者証
664.244号を参照のこと)。
The conventional technology for manufacturing rectifying elements is to chemically deposit metal such as nickel on two opposing surfaces of a semiconductor structure (plating), and then coat the metal with a thermal expansion coefficient close to that of silicon. It is known that a heat sink made of materials such as molybdenum, tungsten, and these materials and δ gold is bonded to one surface of a semiconductor structure in a liquid phase state by soldering or the like (Soviet Union Inventor's Certificate No. 664. (See No. 244).

しかし外から、この方法によって製造された整流素子の
金属堆積層は、高接触抵抗、孔の増大、金属層の厚さが
51tmを超えたときのはがれやすさを有しており、整
流素子のパルスフォワード電圧(pulse forw
ard voltage )  と熱抵抗の増大を招い
ている。
However, from the outside, the metal deposited layer of the rectifying element manufactured by this method has high contact resistance, increased pores, and easy peeling when the metal layer thickness exceeds 51 tm. Pulse forward voltage
ard voltage) and thermal resistance.

また、化学的堆積技術は半導体構造を金属被覆するのに
使用可能な限られた数の材料に制限される。
Also, chemical deposition techniques are limited to a limited number of materials that can be used to metallize semiconductor structures.

しかも、化学的堆積過程によって形成された金属層は厚
さが一様でない。
Moreover, metal layers formed by chemical deposition processes are not uniform in thickness.

この方法(千生導体構造上に金属堆積操作を行った後に
半導体構造への堆積金属層の付着を良好にするため、整
流素子を予熱しなければならない煩雑さがある。
This method has the complication of preheating the rectifying element after performing the metal deposition operation on the conductor structure to ensure good adhesion of the deposited metal layer to the semiconductor structure.

その上、この方法は半導体構造の2つの対向面のそれぞ
れに異った金属を同時に被覆させることができない。
Moreover, this method does not allow simultaneous coating of different metals on each of two opposing sides of the semiconductor structure.

電力用半導体装置の整流素子の製造方法についての従来
技術として、半導体構造の2つの対向面の金属被覆を真
空スパッタリングによって行い、その後半導体構造の一
方の金属被覆面にヒートシンクをはんだ付等の液相状態
で接合したものも知られている(米国特許第3,987
,217号を参照のこと)。
As a conventional technique for manufacturing a rectifying element for a power semiconductor device, two opposing surfaces of a semiconductor structure are coated with metal by vacuum sputtering, and then a heat sink is attached to one of the metal coated surfaces of the semiconductor structure using a liquid phase process such as soldering. It is also known that they are joined in a state (U.S. Pat. No. 3,987)
, No. 217).

この方法は高純度金属を適当に使用し、工程を真空中で
実行することによって接触抵抗を減少させ、スパッタし
た金属層は孔が少なく、スパッタ層が5μmを超える厚
さとなってもはがれにくく、スパッタリングに使用され
る金属の数は増大し、“スパッタ層の熱処理操作を不要
とする。
This method uses appropriate high-purity metals and performs the process in vacuum to reduce contact resistance, and the sputtered metal layer has fewer pores and is difficult to peel off even when the sputtered layer has a thickness of more than 5 μm. The number of metals used for sputtering is increasing, eliminating the need for heat treatment operations on sputtered layers.

しかしながら、この方法は半導体構造の2つの対向面に
異つブこ金属を同時に堆積させることはできない。
However, this method does not allow simultaneous deposition of different metals on two opposing surfaces of a semiconductor structure.

また、金属層の厚さが10μmを超えると多孔性となり
剥離し易くなって、パルスフォワード電圧と整流素子の
熱抵抗の増大を招いている。
Furthermore, when the thickness of the metal layer exceeds 10 μm, it becomes porous and easily peels off, leading to an increase in pulse forward voltage and thermal resistance of the rectifying element.

半導体構造の表面積の増加はスパック層の厚みの一様性
に影響を与える。
The increase in the surface area of the semiconductor structure affects the uniformity of the spuck layer thickness.

ヒートシンクを半導体構造に液相状態で結合させること
は、結合表面の濡れ性を完全な状態にすることが現実と
して困離であることから所望の均質な接触が得られず、
その結果、整流素子のパルスフォワード電圧および熱抵
抗を増加させることになる。
When bonding a heat sink to a semiconductor structure in a liquid state, it is difficult to achieve the desired homogeneous contact because it is difficult in reality to achieve complete wettability of the bonding surface.
As a result, the pulse forward voltage and thermal resistance of the rectifying element will increase.

その上、半導体構造を金属被覆することおよびそこへヒ
ートシンクを結合することは2つの連続した作業で行わ
れるので生産工程の労働量を増大させ不合格整流素子数
を増加させる。
Additionally, metallizing the semiconductor structure and bonding the heat sink thereto are performed in two consecutive operations, increasing the labor load of the production process and increasing the number of rejected rectifier elements.

整流素子の製造方法についての従来技術として、半導体
構造の2つの対向面の金属被覆をその上への化学的金属
堆積または真空金属スパッタリングによって行い、その
後半導体構造の金属被覆面の一方にヒートシンクが拡散
溶接されたものが知らレテいる。べ−・べ−・スンベロ
フ(V、V。
The conventional method for manufacturing rectifying elements is to metallize two opposing sides of a semiconductor structure by chemical metal deposition or vacuum metal sputtering thereon, and then diffuse a heat sink onto one of the metallized sides of the semiconductor structure. There are some welded ones. Be-be-Sumberov (V, V.

Zumberov )、べ−−xル、クズミン(V、L
Zumberov), Be-xle, Kuzmin (V,L
.

Kuzumin )、ニー・デー・フトリャンスキー(
B。
Kuzumin), N.D. Khutryansky (
B.

D 、 Khutoryansky )、ゲーエヌース
#ジェンコフ(G 、 N 、 5urzhenkov
 )、およびデー・工8、クヤルク(A 、 N 、 
Kyark  )が発表した「改良技術」(r[peo
6pa3oBateAhHa* TexonKa  )
(1978年巻7(102)、P、3)シリーズ中の「
電子工業」(9xeKrpoTexHHqecKas+
 npoMuusxe)I−HOe丁b ”  )編の
「電力用半導体素子の整流素子の拡散溶接J(”J11
1ΦΦy31(OH)la$1 CBapKa Bbl
rlpiM)I丁e−JbHOrO9AeMeHTa 
 1HJIOBOro  ll0JI/npOBOJI
HMKOBOrO0,□6opa ”  )を参照のこ
と。
D, Khutoryansky), Gehenkov (G, N, 5urzhenkov)
), and D.K. 8, Kuyark (A, N,
"Improved technology" (r[peo
6pa3oBateAhHa* TexonKa)
(1978 Vol. 7 (102), P, 3) "
Electronic industry” (9xeKrpoTexHHqecKas+
"Diffusion welding of rectifying elements of power semiconductor devices J ("J11
1ΦΦy31(OH)la$1 CBapKa Bbl
rlpiM)Idinge-JbHOrO9AeMeHTa
1HJIOBOro ll0JI/npOBOJI
HMKOBOOrO0, □6opa”).

拡散溶接は同相における接合を与えるので、結果として
生じる接触は高度の均質性を特徴とし、整流素子のパル
スフォワード電圧と熱抵抗の低下を可能とする。
Because diffusion welding provides a bond in phase, the resulting contact is characterized by a high degree of homogeneity, allowing for a reduction in pulse-forward voltage and thermal resistance of the rectifying element.

しかしながら、半導体構造の対向面は化学堆積や真空ス
パッタリングによって金属被覆されているので、整流素
子は堆積金属の剥離し易さ、多孔性、厚さの不均一性に
よって説明されるパルスフォワード電圧と熱抵抗の増加
をやはり示す。
However, since the opposing surfaces of the semiconductor structure are metallized by chemical deposition or vacuum sputtering, the rectifying elements are affected by the pulse-forward voltage and thermal It also shows an increase in resistance.

多孔性のため、半導体構造上に化学的堆積や真空スパッ
タリングによって形成された金属層はヒートシンクとの
拡散溶工程中半導体構造の反対面へ拡散溶接される面密
度材料の金属層よりも変形に対する抵抗性が小さい。こ
のため今度は整流素子の残留曲げを増加させることにな
る。
Because of their porosity, metal layers formed by chemical deposition or vacuum sputtering on semiconductor structures are more resistant to deformation than metal layers of areal density materials that are diffusion welded to the opposite side of the semiconductor structure during the diffusion welding process with a heat sink. gender is small. This in turn increases residual bending of the rectifying element.

その上、この方接では、半導体構造を金属被覆すること
とそこにヒートシンクを接合することに連続する2つの
作業で行われ、生産工程の労働量を増大させ、不良整流
素子数を増加させる。
Moreover, this method involves two consecutive operations: metallizing the semiconductor structure and bonding the heat sink thereto, increasing the labor involved in the production process and increasing the number of defective rectifying elements.

本発明の主要な目的は、半導体構造の金属被覆とそれの
ヒートシンクへの取付をいかなる厚さの層でも金属層が
剥離しないように行う方法を提供すること、半導体構造
の2つの対向面へ類似および非類似の金屑な同時に金属
被膜することを可能にすること、金属層の高度に一様な
厚さを得ること、残留曲げを減少させること、整流素子
の製造プロセスにおける労働量を減少させること、エネ
ルギー消費を節減すること、不良整流素子数を減少させ
ることにある。
The main object of the invention is to provide a method for metallizing a semiconductor structure and attaching it to a heat sink in such a way that the metal layer does not peel off at any thickness, analogous to the two opposing surfaces of the semiconductor structure. making it possible to simultaneously metallize and dissimilar gold scraps, obtaining a highly uniform thickness of the metal layer, reducing residual bending, reducing the amount of labor in the manufacturing process of rectifier elements. The main objectives are to save energy consumption, and to reduce the number of defective rectifying elements.

半導体構造の2つの対向面の金属被膜を含む整流素子の
製造方法におけるこの主要プよ目的を考慮して、本発明
によれば、金属被覆は半導体構造へ金属箔を拡散溶接す
るようにして得られ、この溶接は半導体構造の2つの面
上で同時に行われる。
Considering this main objective in the method of manufacturing a rectifying element comprising a metal coating on two opposite sides of a semiconductor structure, according to the invention the metal coating is obtained by diffusion welding a metal foil onto the semiconductor structure. The welding is performed simultaneously on two sides of the semiconductor structure.

この方法で製造される整流素子に被覆される金属層の厚
さの非一様性および化学的不均一性は溶接される箔材料
の同様な性質のみによって定まる。
The non-uniformity of the thickness and chemical non-uniformity of the metal layer coated on rectifying elements produced in this way is determined only by the similar properties of the foil material to be welded.

箔は半導体構造の表面に析出される金属よりも良好な熱
伝導率とより低い電気抵抗を有した高密度の金属層に相
当し、本発明で提案された方法によって作られた整流素
子は同様に低い熱伝導率とパルスフォワード電圧を有し
ている。
The foil corresponds to a dense metal layer with better thermal conductivity and lower electrical resistance than the metal deposited on the surface of the semiconductor structure, and the rectifier elements made by the method proposed in the present invention similarly It has low thermal conductivity and pulse forward voltage.

金属層の一様な厚さによって整流素子にプレスされた接
触子を設けるためのより良い状態が保証され、このこと
は全体として半導体装置の熱抵抗とパルスフォワード電
圧とをさらに減少させる。
The uniform thickness of the metal layer ensures better conditions for providing pressed contacts on the rectifying element, which further reduces the thermal resistance and the pulse forward voltage of the semiconductor device as a whole.

この方法はいかなる厚さにおいても半導体構造から金属
層が剥離することがなく、孔や酸化含有物のない高密度
金属で半導体構造を被う金属被覆を提供することも可能
にする。
This method does not cause delamination of the metal layer from the semiconductor structure at any thickness and also makes it possible to provide a metallization over the semiconductor structure with a dense metal without pores or oxidized inclusions.

半導体構造の少くとも1つの面へヒートシンクを拡散溶
接を行うのと同時に半導体構造への金属箔の拡散溶接を
行うことが望ましい。
It is desirable to diffusion weld the metal foil to the semiconductor structure at the same time as diffusion weld the heat sink to at least one side of the semiconductor structure.

ヒートシンクの溶接作業と同時に半導体構造の対向面を
金属被覆する作業を行うことは、生産工程の労働量およ
び不良整流素子数を減少させ、エネルギー消費量を削減
させる。
Performing the metallization of the opposite side of the semiconductor structure at the same time as the heat sink welding operation reduces the amount of labor in the production process, the number of defective rectifying elements, and reduces energy consumption.

半導体構造に金属箔を拡散溶接するのと同時に、半導体
構造の少なくとも1つの金属被覆面に銀又は銀合金でで
きた電極の剛性接続を行い、その後このように作られた
整流素子を250ないし230°Cまで01ないし15
℃/秒の割合で冷却することが望ましい。
Simultaneously with the diffusion welding of the metal foil to the semiconductor structure, a rigid connection of an electrode made of silver or a silver alloy is made to at least one metallized side of the semiconductor structure, after which the rectifying element made in this way is °C up to 01 to 15
It is desirable to cool at a rate of 0.degree. C./sec.

ヒートシンクの外表面に金属箔を金属被覆するのと同時
に拡散溶接法によってヒートシンクの外表面に銀または
銀金金製の電極を剛性接続を行い、このように作られた
整流素子を250ないし230°Cまで0.1ないし1
5°C/秒の割合で冷却することが望ましい。
At the same time as metal foil is coated on the outer surface of the heat sink, electrodes made of silver or silver-gold are rigidly connected to the outer surface of the heat sink by diffusion welding, and the rectifying element thus made is heated at 250 to 230 degrees. 0.1 to 1 up to C
It is desirable to cool at a rate of 5°C/sec.

半導体構造の金属被覆表面またはヒートシンクの金属被
覆表面に銀または銀合金でできた電極を剛性接続するた
めに拡散溶接を用いることは、電極の表面原子と公称接
触面積全体にわたって金属被覆された半導体構造の表面
原子間の金属結合の形成の原因となる。このことは、熱
移動が熱伝導だけでな(対流や輻射によって行われる清
浄状態でプレスされた接触子とは異って、水沫による接
触子中の最も効率のよい原子−分子熱伝導機構の作用に
よって熱抵抗の減少が保証される。
The use of diffusion welding to rigidly connect electrodes made of silver or silver alloys to the metallized surfaces of semiconductor structures or to the metallized surfaces of heat sinks is used to connect metallized semiconductor structures over the entire nominal contact area with surface atoms of the electrodes. causes the formation of metallic bonds between surface atoms. This means that heat transfer is not only by conduction (unlike in clean pressed contacts, where heat transfer occurs by convection or radiation, the most efficient atomic-molecular heat transfer mechanism in contacts is water droplets). This action ensures a reduction in thermal resistance.

このように、この方法は、公称面積全体にわたって緻密
な物理的接触を容易に得ることができ、熱抵抗、電極の
実質的な塑性変形、電流路へのその押出しく sque
ezing out )を最小にし、付随する熱サイク
ルを同時に除去できるので、金属被覆された半導体構造
またはヒートシンクに銀または銀合金でできた電極を拡
散溶接することは、性能を犠牲にした従来の方法に従っ
て作られた整流素子の品質を改善することができる。後
者の性質は熱サイクル中に生じる軸方向ストレスが、自
由状態に位置決めされた電極の場合と同様な電極ばかり
でなく、拡散溶接によって電極が強固に固定された表面
によっても吸収されろという事実によって達成される。
Thus, this method can easily obtain close physical contact over the entire nominal area, reducing thermal resistance, substantial plastic deformation of the electrode, and its extrusion into the current path.
Diffusion welding of electrodes made of silver or silver alloys to metallized semiconductor structures or heat sinks can be done in accordance with traditional methods at the expense of performance, since it minimizes the thermal cycling and eliminates the associated thermal cycling at the same time. The quality of the manufactured rectifier can be improved. The latter property is due to the fact that the axial stresses generated during thermal cycling are absorbed not only by the electrode, as in the case of a free-positioned electrode, but also by the surface to which the electrode is firmly fixed by diffusion welding. achieved.

金属箔としてアルミニウムが用いられたとすると、拡散
溶接の間、銀にアルミニウムが拡散した固溶体が溶接領
域に形成される。状態図にしたがって温度390°Cで
溶接後冷却を行うと金属間化合物Ag3Al  を発生
しつつ過飽和固溶体の分解の包晶反応を生ずる。このよ
うな金属間化合物の中間層が形成されることは、熱抵抗
を増加させ、適用アルミ層と銀または銀合金できた電極
との剛性直接接続の強度と塑性を実質的に損う結果とな
り、そして、次には電流サイクル中に起る温度負荷の循
環動作において特に接続部の破壊を引き起す可能性があ
るため非常に望ましくない。
If aluminum is used as the metal foil, during diffusion welding a solid solution of aluminum diffused into silver is formed in the weld area. When cooling is performed after welding at a temperature of 390°C according to the phase diagram, a peritectic reaction of decomposition of a supersaturated solid solution occurs while generating an intermetallic compound Ag3Al. The formation of such intermetallic interlayers increases the thermal resistance and results in a substantial loss of the strength and plasticity of the rigid direct connection between the applied aluminum layer and the silver or silver alloy electrode. , which in turn is highly undesirable since it can lead to breakdown of the connections, especially in the cycling of temperature loads that occur during current cycling.

所定の割合の溶接後冷却により望ましくない層の形成は
防止される。これは冷却が溶接温度から始まって250
ないし230°Cの温度まで下る温度範囲内で0.1 
ないし15℃/秒の割合で行われるとき達成される。こ
れは硬化、すなわち鎖中の過飽和アルミニウム固溶体の
不平衡状態の定着を与えるものである。250ないし2
30℃よりも低い温度では、拡散プロセスは非常に遅く
なり金属間化合物の中間層の形成は不可能になる。冷却
が上記温度範囲を0.1℃/秒より小さい割合で行われ
ると、6金属間化合物Ag3Alが溶接領域に形成され
る。
A certain rate of post-weld cooling prevents the formation of undesirable layers. This means that cooling starts from the welding temperature at 250°C.
0.1 within the temperature range down to temperatures between 230°C and 230°C.
This is achieved when carried out at a rate of between 15°C and 15°C/sec. This provides hardening, ie, establishment of an unbalanced state of supersaturated aluminum solid solution in the chain. 250 to 2
At temperatures below 30° C., the diffusion process becomes so slow that the formation of an intermetallic interlayer becomes impossible. When cooling is carried out in the above temperature range at a rate of less than 0.1° C./sec, a 6-intermetallic compound Ag3Al is formed in the weld area.

15℃/秒より大きい冷却率とすると、熱ショックのた
めおよびストレス緩和のための時間が不足するため半導
体構造のクラック発生の危険がある。
If the cooling rate is greater than 15° C./sec, there is a risk of cracking of the semiconductor structure due to insufficient time for thermal shock and stress relaxation.

半導体構造およびヒートシンク間に挿入される金属箔の
厚さと半導体構造の対向面上の金属箔厚さとの比を02
5から0.5の範囲にとることが望ましい。
The ratio of the thickness of the metal foil inserted between the semiconductor structure and the heat sink to the thickness of the metal foil on the opposite side of the semiconductor structure is 02.
It is desirable to set it in the range of 5 to 0.5.

整流素子を設計する際には、装置の電気的および物理的
特性についての一連の要求事項にもとづいて半導体構造
やヒートシンクの材料や幾何学的寸法が選択されるので
、整流素子の唯一の制御できる設計変数は、半導体47
4造のめつき厚とそこへのヒートシンクの結合のために
使用される金FA箔の厚さ間との比である。
When designing a rectifier, the materials and geometrical dimensions of the semiconductor structure and heat sink are selected based on a set of requirements for the electrical and physical properties of the device, making it the only controllable component of the rectifier. The design variables are semiconductor 47
The ratio between the plating thickness of the 4-layer plate and the thickness of the gold FA foil used for bonding the heat sink thereto.

整流素子の構造が、削性を高(しそのため残留曲げひず
みを小さくしたヒートシンクと結合される場合には、半
導体構造とヒートシンク間に挿入される金属箔の厚さと
半導体構造の対向面上の金属箔厚さとの比を5に近く選
択することが望ましい。このような比は、素子の高平担
度を維持し、半導体構造のヒートシンクに隣接面に対向
する面のめつきに薄い金属箔を使用することを可能にす
る。薄い箔の使用は整流素子製造中の次の作業において
写真蝕刻法が用いられるならば箔の高精度で高品質の写
真蝕刻が得られるのでより望ましい。
When the structure of the rectifying element is combined with a heat sink that has high machinability (and therefore reduces residual bending strain), the thickness of the metal foil inserted between the semiconductor structure and the heat sink and the metal on the opposing surface of the semiconductor structure It is desirable to choose a ratio of foil thickness close to 5. Such a ratio maintains a high degree of flatness of the device and makes it possible to use a thin metal foil for plating the surface opposite the surface adjacent to the heat sink of the semiconductor structure. The use of thin foils is more desirable as it allows for highly accurate and high quality photoetching of the foil if photolithography is used in subsequent operations during rectifier manufacturing.

整流素子が残留曲げひずみを除去するために低剛性であ
るときは、半導体構造とヒートシンク間に挿入される金
属箔の厚さと半導体構造の対向面上の金属箔の厚さとの
比をo、25に近づげることが望ましい。しかし、これ
らの色間の比を0.25未満にすると、半導体構造の残
留曲げ屈曲の符号はヒートシンクの曲げ屈曲に対して負
となり、整流素子をハウジングに塔載する過程で加わる
圧力は半導体構造の不良を招く。
When the rectifying element has low rigidity to remove residual bending strain, the ratio of the thickness of the metal foil inserted between the semiconductor structure and the heat sink to the thickness of the metal foil on the opposite side of the semiconductor structure is o, 25. It is desirable to get it close to . However, if the ratio between these colors is less than 0.25, the sign of the residual bending of the semiconductor structure will be negative with respect to the bending of the heat sink, and the pressure applied during the process of mounting the rectifier on the housing will be resulting in defects.

本発明の特徴は図面により示される詳細な記載によりさ
らに説明される。
Features of the invention are further explained by the detailed description illustrated in the drawings.

提案される方法は次のように行われる。The proposed method works as follows.

対向面上に配置された金属箔円盤2,3を有する半導体
構造1を含むスタックは加熱され、圧縮され、真空中で
所定時間保持される。これらの作業は第1図中で水平線
ゝa”および1b″により示される平面に沿った溶接接
合を同時に与える。
A stack comprising a semiconductor structure 1 with metal foil disks 2, 3 arranged on opposite sides is heated, compressed and held in vacuum for a predetermined time. These operations simultaneously provide a welded joint along the plane indicated by horizontal lines a" and 1b" in FIG.

第2図に示される整流素子を製造す゛るときには、対向
面上に配置された金属箔円盤2.3を有する半導体構造
1とヒートシンク4を含スタックが組立てられる。円盤
3と円盤2間の比は0.25か恒5の範囲に選択すべき
である。組立てられたスタックは加熱され、圧縮され、
真空中に所定時間保持されて、これらの作業は第2図中
で水平線ゝa“。
When manufacturing the rectifying element shown in FIG. 2, a stack is assembled comprising a semiconductor structure 1 with metal foil disks 2.3 arranged on opposite sides and a heat sink 4. The ratio between disk 3 and disk 2 should be selected in the range of 0.25 or constant 5. The assembled stack is heated, compressed,
These operations are carried out by being kept in a vacuum for a predetermined period of time, as indicated by the horizontal line "a" in FIG.

1b“および1C”で示される平面に沿った溶接接合を
同時に与える。
Welded joints along the planes designated 1b" and 1C" are simultaneously provided.

第3図に示される整流素子を製造するときには、対向面
上に配置された金属箔円盤を有する半導体構造1とヒー
トシンク4,5を含むスタックは組立てられる。円盤3
と2間の比は015から10の範囲に選択すべきである
。組立てられたスタックは、加熱され、圧縮され、真空
中で所定時間保持されて、これらの作業は第3図中で水
平線ゝa“ %b“。
When manufacturing the rectifying element shown in FIG. 3, a stack comprising a semiconductor structure 1 with metal foil disks arranged on opposite sides and a heat sink 4, 5 is assembled. Disc 3
and 2 should be selected in the range 015 to 10. The assembled stack is heated, compressed, and held in vacuum for a predetermined period of time, these operations being indicated by the horizontal line "a"%b" in FIG.

′C“により示される平面に沿った溶接接合を同時に与
え゛る。
At the same time, a welded joint along the plane indicated by 'C' is provided.

第4図に示される整流素子を製造するときには、対向面
上に配置された金属箔円盤を有する半導体構造1とヒー
トシンク4、金属箔円盤6、銀又はその合金で作られた
電極7,8を含むスタックが組立てられる。組立てられ
たスタックは、加熱され、圧縮され、真空中で所定時間
保持されて、これらの作業は第4図中で水平線ゝa“、
ゝb”、1C”。
When manufacturing the rectifying element shown in FIG. 4, a semiconductor structure 1 with metal foil discs arranged on opposite sides, a heat sink 4, a metal foil disc 6, electrodes 7, 8 made of silver or its alloys are used. A stack containing is assembled. The assembled stack is heated, compressed, and held in vacuum for a predetermined period of time, and these operations are indicated by horizontal lines "a" and "a" in FIG.
ゝb", 1C".

′d“ %e“、薯”、1g” により示される平面に
沿った溶接接合を同時に与える。
At the same time, a welded joint is provided along the planes indicated by %e, %e, and 1g.

その後ただちに整流素子は0.1ないし15°C/秒の
割合で250ないし230°Cの温度まで冷却される。
Immediately thereafter, the rectifying element is cooled at a rate of 0.1 to 15°C/sec to a temperature of 250 to 230°C.

提案された方法の特別の応用例を以下に示す。A special application of the proposed method is given below.

(例1) 電流630A、くり返し電圧2ないし3KVの定格を有
するダイナミックサイリスタの整流素子が作られた。シ
リコン半導体構造、タングステンヒートシンク、アルミ
ニウム箔円盤の直径はそれぞれ50 mylであった。
(Example 1) A dynamic thyristor rectifier element having a rating of 630 A current and 2 to 3 KV repetition voltage was made. The diameters of the silicon semiconductor structure, tungsten heat sink, and aluminum foil disk were each 50 ml.

7リコン構造の厚さは0.6 vrxであり、ヒートシ
ンクの厚さは3闘であった。ヒートシンクと半導体構造
との間に挿入されたアルミニウム箔の厚さは0.12+
+iであり、シリコン構造の対向面を金属被覆するため
の箔の厚さは0.0131gであり、これらの箔厚さ間
の比は9に等しかった。
The thickness of the 7 recon structure was 0.6 vrx and the thickness of the heat sink was 3 vrx. The thickness of the aluminum foil inserted between the heat sink and the semiconductor structure is 0.12+
+i and the thickness of the foil for metallizing the opposite side of the silicon structure was 0.0131 g, and the ratio between these foil thicknesses was equal to 9.

組立てられたスタックの拡散溶接は6’6.5 MP 
aの真空チャンバ中で、15 MP a  の単位圧縮
圧力、550℃の温度で300秒間行われた。
Diffusion welding of the assembled stack is 6'6.5 MP
It was carried out for 300 seconds at a unit compressive pressure of 15 MPa and a temperature of 550° C. in a vacuum chamber of a.

部品が互いに拡散溶接された後、残留曲げ屈曲は0.0
08關であった。
After the parts are diffusion welded together, the residual bending flexion is 0.0
It was on the 08th.

(例2) 電流2.00OA 、 <、り返し電圧400■の定格
を有する溶接装置用のダイオード整流素子が作られた。
(Example 2) A diode rectifier element for a welding device having a current rating of 2.00 OA and a repetition voltage of 400 μm was manufactured.

シリコン構造、モリブデン製ヒートシンク、アルミニウ
ム箔円盤の直径はそれぞれ40蛮産であった。
The silicon structure, molybdenum heat sink, and aluminum foil disk each had a diameter of 40 mm.

シリコン構造の厚さは0.251m、モリブデンヒート
シンクの厚さは0.5 mmであった。ヒートシンクと
半導体構造どの間に挿入されたアルミニウム箔の厚さは
0.05 フnmであり、半導体構造の対向面を金属被
覆するための箔の厚さは0.28mmであり、これらの
箔厚さ間の比は0.18に等しかった。
The thickness of the silicon structure was 0.251 m and the thickness of the molybdenum heat sink was 0.5 mm. The thickness of the aluminum foil inserted between the heat sink and the semiconductor structure is 0.05 nm, and the thickness of the foil for metallizing the opposite side of the semiconductor structure is 0.28 mm. The gap ratio was equal to 0.18.

組立てられたスタックの拡散溶接は、66.5MPaの
真空チャンバ中で、15MPa  の単位圧縮圧力、5
50℃の温度で300秒間行われた。
Diffusion welding of the assembled stack was carried out in a 66.5 MPa vacuum chamber at a unit compression pressure of 15 MPa, 5
It was carried out for 300 seconds at a temperature of 50°C.

部品が互いに拡散溶接された後、残留曲げ屈曲は0.0
1mmであった。
After the parts are diffusion welded together, the residual bending flexion is 0.0
It was 1 mm.

(例3) 電流80ないし100A、(り返し電圧0.7ないし1
.5KVの定格を有する逆極接続ダイオード用の整流素
子が作られた。シリコン構造およびタングステンヒート
シンクの直径は18間であった。ヒートシンクと半導体
構造との間に挿入されたアルミニウム箔円盤および半導
体構造の対向面を金属被覆するための円盤は同一直径で
それぞれ0.05 mmと012記の厚さ、を有してお
り、すなわちこれらの厚さ間の比は4.2に等しかった
。シリコン構造の厚さは03mmでありタングステンヒ
ートシンクの厚さは1.5關であった。
(Example 3) Current 80 to 100A, (repetition voltage 0.7 to 1
.. A rectifier element was made for a reverse polarity connected diode with a rating of 5KV. The diameter of the silicon structure and tungsten heat sink was between 18 mm. The aluminum foil disk inserted between the heat sink and the semiconductor structure and the disk for metallizing the opposite side of the semiconductor structure have the same diameter and a thickness of 0.05 mm and 0.12 mm respectively, i.e. The ratio between these thicknesses was equal to 4.2. The thickness of the silicon structure was 0.3 mm and the thickness of the tungsten heat sink was 1.5 mm.

組立てられたスタックの拡散溶接は66.5MPaの真
空チャンバ中で15MPa  の単位圧縮圧力、550
℃の温度で300秒間行われた。
Diffusion welding of the assembled stack was carried out at a unit compression pressure of 15 MPa in a vacuum chamber of 66.5 MPa, 550
It was carried out for 300 seconds at a temperature of °C.

前述の部品が互いに拡散溶接された後、残留曲げ屈曲は
0.01朋であった。
After the aforementioned parts were diffusion welded together, the residual bending flex was 0.01.

(例4) すべての溶接されるべきすべての部品の直径が32朋で
あり、1000 Aの定格を有する周波数逆極接続ダイ
オードの整流素子が製造された。厚さ0.15 mmの
銀円盤、厚さ01朋のアルミニウム円盤、シリコン構造
、厚さ0.1朋のアルミニウム円盤、厚さ0.15 t
tmの銀円盤を有するスタックが組立てられた。拡散溶
接は例1に記載された条件で行われ、溶接温度550℃
から250℃への冷却は0.15°C/秒の割合で行わ
れた。
Example 4 A frequency reverse connected diode rectifier with a rating of 1000 A was manufactured, with the diameter of all parts to be welded being 32 mm. Silver disk 0.15 mm thick, aluminum disk 01 mm thick, silicon structure, aluminum disk 0.1 mm thick, 0.15 t thick
A stack with tm silver discs was assembled. Diffusion welding was carried out under the conditions described in Example 1, with a welding temperature of 550°C.
Cooling from to 250°C was performed at a rate of 0.15°C/sec.

溶接後の溶接部の金属組織検査およびX線分光分析検査
によって、溶接部は金属間化合物AgaA1層がないこ
とが明確に示された。さらにダイオードの試験は高い電
気的、温度および動作特性を示した。
Metallographic and X-ray spectroscopic examination of the weld after welding clearly showed that the weld was free of intermetallic AgaAl layer. Additionally, diode testing showed high electrical, temperature and operating characteristics.

(例5) 溶接されるすべての部品の直径が32順であり、320
Aの定格を有する工業用サイリスクの整流素子が製造さ
れた。整流素子のすべての溶接部を与えて0.05 t
nnの厚さの銀円盤状の電極は同時に剛性固定された。
(Example 5) The diameters of all parts to be welded are in order of 32, and 320
An industrial Sirisk rectifier having a rating of A was manufactured. 0.05 t given all welds of the rectifier
At the same time, a silver disk-shaped electrode with a thickness of nn was rigidly fixed.

銀円盤0.02mrtr厚のアルミニウム円盤、シリコ
ン構造、0.1mm厚のアルミニウム円盤、タングステ
ンの、ヒートシンク、 Q、05 mm厚のアルミニウ
ム円盤、および銀円盤を有するスタックが組立てられた
。拡散溶接は例1に示された条件で行われ550℃から
230℃までの範囲の冷却は14°C/秒の割合で行わ
れた。
A stack was assembled with a silver disk, a 0.02 mrtr thick aluminum disk, a silicon structure, a 0.1 mm thick aluminum disk, a tungsten, heat sink, a Q,05 mm thick aluminum disk, and a silver disk. Diffusion welding was carried out under the conditions given in Example 1, with cooling from 550°C to 230°C at a rate of 14°C/sec.

5つの整流素子の金属組織検査によって、溶接部は金属
間化合物の中間層がなく、半導体構造はクラックがない
ことが示された。
Metallographic examination of the five rectifying elements showed that the welds were free of intermetallic interlayers and the semiconductor structure was crack-free.

装置内の整流素″子の試験によって、電、気菌、熱的要
素に関して提案された方法が高性能かつ有利であること
が示された。
Testing of the rectifying elements in the device showed that the proposed method is efficient and advantageous with regard to electrical, pneumatic and thermal elements.

(例6) 直径18鉢の周波数ダイオードの整流素子が製造された
。銀電極は整流素子中の残りの接触部を拡散溶接によっ
て設げるのと同時に剛性固定される。
(Example 6) A frequency diode rectifier element with a diameter of 18 pots was manufactured. The silver electrode is rigidly fixed at the same time as the remaining contacts in the rectifying element are provided by diffusion welding.

002罷厚のアルミニウム円盤、シリコン構造、01m
m厚のアルミニウム円盤、  1.57+m厚のタング
ステン円盤、0.05 mm厚のアルミニウム円盤、 
0.05 mm厚の銀円盤を有するスタックが組立てら
れた。スタックの拡散溶接は550°の温度で300秒
問および66.5 MPaの真空中で15 MP a 
 の単位圧縮で行われた。溶接後の230°Cまでの冷
却は、45℃/秒の割合で行われた。金属組織検査によ
って、溶接部にはアルミニウムと銀の金属間化合物が存
在しないことがわかり、また、装置内の溶接された整流
素子の試験は高い電気的、温度および動作特性を示した
002 thick aluminum disk, silicon structure, 01m
m thick aluminum disk, 1.57+m thick tungsten disk, 0.05 mm thick aluminum disk,
A stack with 0.05 mm thick silver discs was assembled. Diffusion welding of the stack was performed at a temperature of 550° for 300 seconds and in a vacuum of 66.5 MPa at 15 MPa.
This was done with unit compression. Cooling to 230°C after welding was performed at a rate of 45°C/sec. Metallographic examination showed the absence of aluminum and silver intermetallic compounds in the weld, and testing of the welded rectifying elements within the device showed high electrical, temperature and operating characteristics.

本発明による整流素子の製造方法の利点は従来技術に比
べて、 低熱抵抗と低パルスフォワード電圧を有する整流素子を
製造することができ、 全体として整流素子の動作負荷耐力を増加させることが
でき、 高純度金属の消費を減少させることができ、銀又は銀合
金で作られた電極の厚さを減少させることにより銀を節
約することができ、整流素子のすべての接触部を形成す
るのと同時に銀又は銀合金で作られた電極の剛性直接接
続な設けることができ、 整流素子を製造する工程の労働集中と電力消費を減少さ
せることができ、 整流素子の不良数を減少させることができ、使用する設
備の数やコストおよびそれらを収納する必要面積を減少
することができる、という点にある。
The advantages of the manufacturing method of a rectifying element according to the present invention, compared to the prior art, are that a rectifying element with low thermal resistance and low pulse forward voltage can be manufactured, and the operating load carrying capacity of the rectifying element as a whole can be increased; The consumption of high-purity metals can be reduced, and silver can be saved by reducing the thickness of the electrodes made of silver or silver alloys, and at the same time forming all the contacts of the rectifying elements. The rigid direct connection of electrodes made of silver or silver alloy can be provided, which can reduce the labor concentration and power consumption of the process of manufacturing rectifying elements, and can reduce the number of defective rectifying elements. The advantage is that the number and cost of equipment used and the area required to house them can be reduced.

本発明の特別な実施例を示して説明したが、当業者にお
いてこれらの各種の変形が明らかであるので、本発明は
上記に考察された整流素子の提案された方法の記載や、
これらの詳細な点に限定さ
Although specific embodiments of the invention have been shown and described, various variations thereof will be apparent to those skilled in the art, and the invention therefore includes a description of the proposed method of rectifying elements as discussed above;
limited to these details

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明にかかる整流素子の製造法の一実施例に
より製造された整流素子を示す断面図、第2図は本発明
の他の実施例により製造された整流素子を示す断面図、
第3図は本発明のさらに他の実施例により製造された整
流素子を示す断面図、第4図は本発明のさらに他の実施
例により製造−された整流素子を示す断面図である。 1・・・半導体構造、2,3・・・金属箔、4・・・ヒ
ートシンク、6・・・金属箔、7.8・・・銀又は銀合
金製電極。 出願人代理人  猪  股    清 Flに、2 F広3 チ・カルポフ ソビエト連邦タリン・ウーリッ ツア・ベリキエ・ホキ22カーベ 104 0発 明 者 オレグ・ミハイロウイッチ・コロルコフ ソビエト連邦タリン・ウーリッ ツア・フエドユニンスコホ56カ ーベー98 0発 明 者 ビクトル・レオニドウィッチ・クズミン ソビエト連邦タリン・イスムヤ 工・チー114カーベー20 0発 明 者 ゲンナジー・ニコラエウイツチ・スルゼ
ンコフ ソビエト連邦タリン・フィルト リ・チー8カーベー14 移発 明 者 グンナール・カルロウイツチ・トムソー ソビエト連邦タリン・タムサレ ・チー121カーベー27 0発 明 者 エフイム・ダビドウイツチ・フトルヤン
スキー ソビエト連邦タリン・ウーリツ ツア・クレイツバルダ4アー・ 力一べ−24
FIG. 1 is a sectional view showing a rectifying element manufactured by an embodiment of the rectifying element manufacturing method according to the present invention, and FIG. 2 is a sectional view showing a rectifying element manufactured by another embodiment of the present invention.
FIG. 3 is a sectional view showing a rectifying element manufactured according to still another embodiment of the present invention, and FIG. 4 is a sectional view showing a rectifying element manufactured according to still another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor structure, 2, 3... Metal foil, 4... Heat sink, 6... Metal foil, 7.8... Silver or silver alloy electrode. Applicant's agent Kiyoshi Inomata Fl, 2 F Hiro 3 Chi Karpov Soviet Union Tallinn Uritsa Velikie Hoki 22 Kave 104 0 Inventor Oleg Mikhailovich Korolkov Soviet Union Tallinn Uritsa Feduns Koho 56 Kabe 98 0 Inventor Viktor Leonidovich Kuzmin Soviet Union Tallinn Ismyya Kochi 114 Kabe 20 0 Inventor Gennady Nikolaevich Sluzhenkov Soviet Union Tallinn Filtli Chi 8 Kabe 14 Transfer inventor Gunnar Karlowicz Thomsor Soviet Union Tallinn Tamsare Kyi 121 Kabe 27 0 Inventor Efim Davidovich Khutruyanskiy Soviet Union Tallinn Ulitsa Kreizbarda 4A Rikichibe-24

Claims (1)

【特許請求の範囲】 1、半導体構造(1)の2つの対向面を金属被覆するこ
とを含む整流素子の製造方法において、前記金属被覆は
半導体構造(1)に金属箔(2゜3)を拡散溶接するこ
とによって与えられ、前記溶接は半導体構造の両面上で
同時に行われることを特徴とする整流素子の製造方法。 2、半導体構造(1)の少くとも1つの面にヒートシン
ク(4)を拡散溶接することを含み、前記金属箔(2、
3)の半導体構造への拡散溶接は前記ヒートシンク(4
)の拡散溶接と同時に行われることを特徴とする特許請
求の範囲第1項記載の整流素子の製造方法。 3、半導体構造(1)およびヒートシンク(4)のりに
挿入される金属箔(3)の厚さと、半導体構造(1)の
対向面上に配置される金属箔の厚さとの比が0.15か
ら10までの範囲であることを特徴とする特許請求の範
囲第2項記載の整流素子の製造方法。 4、半導体構造(1)の少くとも1つの金属被覆面に銀
又は銀合金で成る電極を固着し、 この固着は半導体構造(1)に金属箔(2)を拡散溶接
するのと同時に拡散溶接によって与えられ、 さらにこのように作られた整流素子は01ないし15°
C/秒の割合で250ないし230℃まで冷却されるこ
とを特徴とする特許請求の範囲第1項記載の整流素子の
製造方法。 5、ヒートシンク(4)の外表面に銀又は銀合金で成る
電極を固着し、 この電極の固着は金属箔(6)でヒートシンク(4)の
外表面を金属被覆するのと同時に拡散溶接によって与え
られ、 さらに、このように作られた整流素子は0.1ないし1
5°C/秒の割合で250ないし230℃まで冷却され
ることを特徴とする特許請求の範囲第2項記載の整流素
子の製造方法。
[Claims] 1. A method for manufacturing a rectifying element including metal coating two opposing surfaces of a semiconductor structure (1), wherein the metal coating includes metal foil (2°3) on the semiconductor structure (1). A method for manufacturing a rectifier element, characterized in that it is provided by diffusion welding, said welding being carried out simultaneously on both sides of the semiconductor structure. 2. diffusion welding a heat sink (4) to at least one side of the semiconductor structure (1), said metal foil (2,
Diffusion welding to the semiconductor structure in step 3) is performed using the heat sink (4).
2. The method for manufacturing a rectifying element according to claim 1, wherein said method is carried out simultaneously with diffusion welding. 3. The ratio of the thickness of the metal foil (3) inserted into the semiconductor structure (1) and the heat sink (4) and the thickness of the metal foil placed on the opposite side of the semiconductor structure (1) is 0.15. 3. The method of manufacturing a rectifying element according to claim 2, wherein the rectifying element is in a range from 10 to 10. 4. An electrode made of silver or a silver alloy is fixed to at least one metallized surface of the semiconductor structure (1), and this fixation is done by diffusion welding at the same time as diffusion welding the metal foil (2) to the semiconductor structure (1). Furthermore, the rectifying element made in this way is given by 01 to 15°
2. The method of manufacturing a rectifying element according to claim 1, wherein the rectifying element is cooled to 250 to 230° C. at a rate of C/sec. 5. An electrode made of silver or silver alloy is fixed to the outer surface of the heat sink (4), and this electrode is fixed by diffusion welding at the same time as coating the outer surface of the heat sink (4) with metal foil (6). Furthermore, the rectifying element made in this way has a power of 0.1 to 1
3. The method of manufacturing a rectifying element according to claim 2, wherein the rectifying element is cooled to 250 to 230° C. at a rate of 5° C./sec.
JP58154242A 1983-02-03 1983-08-25 Method of producing rectifier Pending JPS59144176A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SU833540851A SU1114253A1 (en) 1983-02-03 1983-02-03 Sealed storage battery
SU3540851 1983-02-03

Publications (1)

Publication Number Publication Date
JPS59144176A true JPS59144176A (en) 1984-08-18

Family

ID=21045701

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58154242A Pending JPS59144176A (en) 1983-02-03 1983-08-25 Method of producing rectifier

Country Status (6)

Country Link
JP (1) JPS59144176A (en)
DE (1) DE3325355A1 (en)
FR (1) FR2540673B1 (en)
IT (1) IT1195541B (en)
SE (1) SE8303838L (en)
SU (1) SU1114253A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3446780A1 (en) * 1984-12-21 1986-07-03 Brown, Boveri & Cie Ag, 6800 Mannheim METHOD AND JOINING MATERIAL FOR METALLICALLY CONNECTING COMPONENTS
DE58908749D1 (en) * 1988-03-03 1995-01-26 Siemens Ag Method for fixing electronic components on substrates and arrangement for carrying them out.
EP0330896A3 (en) * 1988-03-03 1991-01-09 Siemens Aktiengesellschaft Method for attaching semiconductor components to substrates, and arrangement for carrying it out

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5380169A (en) * 1976-12-24 1978-07-15 Nippon Intaanashiyonaru Seiriy Diffused alloy semiconductor
JPS55128836A (en) * 1979-03-29 1980-10-06 Toshiba Corp Method of mounting semiconductor pellet
JPS5691990A (en) * 1979-12-26 1981-07-25 Hitachi Ltd Diffusion joining device

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US326598A (en) * 1885-09-22 Hot-air furnace
NL275554A (en) * 1961-04-19 1900-01-01
FR1419202A (en) * 1963-12-31 1965-11-26 Ibm Ohmic contacts for semiconductor elements
FR2046593A5 (en) * 1970-04-30 1971-03-05 Silec Semi Conducteurs
US3717797A (en) * 1971-03-19 1973-02-20 Westinghouse Electric Corp One piece aluminum electrical contact member for semiconductor devices
GB1389542A (en) * 1971-06-17 1975-04-03 Mullard Ltd Methods of securing a semiconductor body to a support
FR2412168A1 (en) * 1977-12-15 1979-07-13 Silicium Semiconducteur Ssc OVERVOLTAGE DIODES
US4315591A (en) * 1979-03-08 1982-02-16 General Electric Company Method for thermo-compression diffusion bonding a structured copper strain buffer to each side of a substrateless semiconductor device wafer
GB2067117B (en) * 1980-01-02 1983-07-06 Secr Defence Bonding semi-conductor bodies to aluminium thick-film circuits
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Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5380169A (en) * 1976-12-24 1978-07-15 Nippon Intaanashiyonaru Seiriy Diffused alloy semiconductor
JPS55128836A (en) * 1979-03-29 1980-10-06 Toshiba Corp Method of mounting semiconductor pellet
JPS5691990A (en) * 1979-12-26 1981-07-25 Hitachi Ltd Diffusion joining device

Also Published As

Publication number Publication date
DE3325355A1 (en) 1984-08-09
FR2540673B1 (en) 1988-07-29
FR2540673A1 (en) 1984-08-10
IT1195541B (en) 1988-10-19
SU1114253A1 (en) 1987-03-23
IT8341604A0 (en) 1983-09-12
SE8303838D0 (en) 1983-07-05
SE8303838L (en) 1984-08-04
IT8341604A1 (en) 1985-03-12

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