JP2503775B2 - Substrate for semiconductor device - Google Patents

Substrate for semiconductor device

Info

Publication number
JP2503775B2
JP2503775B2 JP24709788A JP24709788A JP2503775B2 JP 2503775 B2 JP2503775 B2 JP 2503775B2 JP 24709788 A JP24709788 A JP 24709788A JP 24709788 A JP24709788 A JP 24709788A JP 2503775 B2 JP2503775 B2 JP 2503775B2
Authority
JP
Japan
Prior art keywords
plate material
semiconductor device
insulating plate
heat sink
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP24709788A
Other languages
Japanese (ja)
Other versions
JPH0294649A (en
Inventor
秀昭 吉田
暁 森
祥郎 黒光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP24709788A priority Critical patent/JP2503775B2/en
Publication of JPH0294649A publication Critical patent/JPH0294649A/en
Application granted granted Critical
Publication of JP2503775B2 publication Critical patent/JP2503775B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置の高集積化および大電力化に
十分対応することができる半導体装置用基板に関するも
のである。
Description: TECHNICAL FIELD The present invention relates to a semiconductor device substrate which can sufficiently cope with higher integration and higher power consumption of a semiconductor device.

〔従来の技術〕[Conventional technology]

従来、一般に、半導体装置用基板としては、例えば第
2図に概略説明図で示されるように、酸化アルミニウム
(Al2O3)焼結体からなる絶縁板材C′の上下両面に、C
u薄板材B′を液相接合し、この液相接合は、例えば前
記Cu薄板材の接合面に酸化銅(Cu2O)を形成しておき、
前記Al2O3製絶縁板材と重ね合わせた状態で、1965〜108
5℃に加熱して接合面に前記Cu2OとCuとの間で液相を発
生させて結合する方法であり、また前記Cu薄板材のう
ち、Al2O3製絶縁板材C′の上面側が回路形成用導体と
なり、同下面側がはんだ付け用となるものであり、この
状態で、通常Pb-Sn合金からなるはんだ材(融点:450℃
以下をはんだという)D′を用いて、Cuからなるヒート
シンク板材A′に接合してなる構造をもつことが知られ
ている。
2. Description of the Related Art Conventionally, as a substrate for a semiconductor device, for example, as shown in a schematic explanatory view in FIG. 2, an insulating plate material C ′ made of an aluminum oxide (Al 2 O 3 ) sintered body has C and C
u The thin plate material B'is liquid-phase bonded. For this liquid phase bonding, for example, copper oxide (Cu 2 O) is formed on the bonding surface of the Cu thin plate material,
In the state of being laminated with the Al 2 O 3 insulating plate material, 1965 to 108
This is a method of heating at 5 ° C. to generate a liquid phase between the Cu 2 O and Cu on the joint surface and bonding, and the upper surface of the Al 2 O 3 insulating plate material C ′ of the Cu thin plate materials. The side is the conductor for circuit formation, and the bottom side is for soldering. In this state, the solder material usually made of Pb-Sn alloy (melting point: 450 ° C
It is known to have a structure in which a heat sink plate material A'made of Cu is bonded using D '(hereinafter referred to as solder).

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

しかし、近年の半導体装置の高集積化および大電力化
によって半導体装置に発生する熱量が増大するようにな
り、これに伴って半導体装置が受ける発熱・冷却の繰り
返しからなる温度サイクルもその振幅が大きく、苛酷に
なる傾向にあるが、上記した構造の従来半導体装置用基
板では、このような苛酷な温度サイクルにさらされる
と、例えば純度:96%のAl2O3焼結体の熱膨張係数が6×
10-6/℃、Cuのそれが17.2×10-6/℃であるように、Al
2O3製絶縁板材C′とCu薄板材B′との間に存在する大
きな熱膨張差によって、延性のないAl2O3製絶縁板材に
は割れが発生し易くなるばかりでなく、はんだ材D′に
は、融点が450℃以下と低いことと合まって、熱疲労が
発生し易く、このはんだ材層に剥離現象が生じるように
なり、この状態になると半導体装置内に発生した熱のヒ
ートシンク板材A′からの放熱を満足に行なうことがで
きなくなるという問題が発生し、かかる点で半導体装置
の高集積化および大電力化に十分対応することができな
いのが現状である。
However, the amount of heat generated in a semiconductor device has increased due to the recent higher integration and higher power consumption of the semiconductor device, and along with this, the amplitude of the temperature cycle of repeated heat generation and cooling received by the semiconductor device is also large. However, in the conventional semiconductor device substrate having the above structure, when exposed to such a severe temperature cycle, for example, the thermal expansion coefficient of an Al 2 O 3 sintered body having a purity of 96% is 96%. 6x
10 -6 / ℃, Cu so that it is 17.2 × 10 -6 / ℃, Al
Due to the large thermal expansion difference existing between the 2 O 3 insulating plate material C ′ and the Cu thin plate material B ′, not only the ductility of the Al 2 O 3 insulating plate material, which is not ductile, easily occurs, but also the solder material D'has a melting point as low as 450 ° C. or lower, which easily causes thermal fatigue, and causes a peeling phenomenon in this solder material layer. In this state, heat generated in the semiconductor device The problem that heat radiation from the heat sink plate material A'cannot be performed satisfactorily occurs, and at this point, it is not possible to sufficiently cope with high integration and high power consumption of the semiconductor device.

〔課題を解決するための手段〕[Means for solving the problem]

そこで、本発明者等は、上述のような観点から、半導
体装置の高集積化および大電力化に対応することができ
る半導体装置用基板を開発すべく研究を行なった結果、
第1図に概略説明図で示されるように、絶縁板材Cを窒
化アルミニウム(AlN)焼結体で構成し、これの両面に
回路形成用導体薄板材Bとヒートシンク板材Aとを接合
した構造とすると共に、前記導体薄板材Bとヒートシン
ク板材Aとを、それぞれW,Mo,W合金、およびMo合金のう
ちのいずれかで構成し、かつこれらの前記絶縁板材Cへ
の接合を重量%で(以下同じ)、例えばAg-29%Cu-4%T
i合金や、Cu-3%Ti合金、あるいはCu-3%Zr合金などか
らなる高融点ろう材(この発明では、750℃以上の融点
を有するろう材をいう)Dを用いて行なうと、前記絶縁
板材と導体薄板材Bおよびヒートシンク板材Aとは、苛
酷な温度サイクルによっても熱疲労することのない前記
高融点ろう材Dによって強固に接合し、かつ前記AlN製
絶縁板材Cは、Al2O3焼結体の熱伝導率が17W/K・mであ
るのに対してAlN焼結体のそれは160W/K・mであるよう
にすぐれた熱の良導体であり、この熱伝導率は回路形成
用導体薄板材Bおよびヒートシンク板材Aを構成するMo
の熱伝導率:142W/K・m、Wの熱伝導率:167W/K・mとき
わめて近似するものであり、さらに熱膨張係数に関して
も、AlN焼結体:3.6×10-6/℃、Mo:5.3×10-6/℃、W:
4.7×10-6/℃、例えばW-10%Cu合金:5.5×10-6/℃で
あるようにきわめて近似するものであり、したがって上
記構造の半導体装置用基板においては、AlN製絶縁板材
Cと導体薄板材Bおよびヒートシンク板材Aとの間に、
ろう材の熱疲労が原因の剥離や、絶縁板材Cに大きな熱
膨張差が原因の割れの発生がなく、すぐれた熱の拡散性
と放熱性を発揮するようになるという知見を得たのであ
る。
Therefore, the inventors of the present invention have conducted research to develop a semiconductor device substrate capable of accommodating high integration and high power consumption of the semiconductor device from the above viewpoints.
As shown in the schematic explanatory view of FIG. 1, a structure in which an insulating plate material C is made of an aluminum nitride (AlN) sintered body, and a circuit-forming conductor thin plate material B and a heat sink plate material A are bonded to both surfaces of the insulating plate material C, In addition, the conductor thin plate material B and the heat sink plate material A are each formed of any one of W, Mo, W alloy, and Mo alloy, and the bonding to the insulating plate material C by weight% ( The same shall apply hereinafter), eg Ag-29% Cu-4% T
When using a high melting point brazing filler metal (in the present invention, a brazing filler metal having a melting point of 750 ° C. or higher) D made of an i alloy, Cu-3% Ti alloy, Cu-3% Zr alloy, or the like, The insulating plate material, the conductor thin plate material B, and the heat sink plate material A are firmly joined by the high melting point brazing material D that does not cause thermal fatigue even under severe temperature cycles, and the AlN insulating plate material C is made of Al 2 O. 3 The thermal conductivity of the sintered body is 17 W / K ・ m, while that of the AlN sintered body is 160 W / K ・ m, which is a good conductor of heat. Mo that constitutes the conductor thin plate material B and the heat sink plate material A
Thermal conductivity of 142 W / K ・ m, thermal conductivity of W: 167 W / K ・ m, which are extremely close to each other, and regarding the coefficient of thermal expansion, AlN sintered body: 3.6 × 10 -6 / ℃, Mo: 5.3 × 10 -6 / ℃, W:
It is very close to 4.7 × 10 -6 / ° C., for example, W-10% Cu alloy: 5.5 × 10 -6 / ° C. Therefore, in the semiconductor device substrate having the above structure, the insulating plate material C made of AlN is used. Between the conductor thin plate material B and the heat sink plate material A,
It has been found that the exfoliation of the brazing material caused by thermal fatigue and the cracking of the insulating plate material C caused by a large difference in thermal expansion do not occur, and excellent heat diffusivity and heat dissipation can be exhibited. .

この発明は、上記知見にもとづいてなされたものであ
って、AlN焼結体からなる絶縁板材の一方面に、W,Mo,W
合金、およびMo合金のうちのいずれかからなる回路形成
用導体薄板材を、前記絶縁板材の他方面に、同じくW,M
o,W合金、およびMo合金のうちのいずれかからなるヒー
トシンク板材をそれぞれ高融点ろう材を用いて接合して
なる半導体装置用基板に特徴を有するものである。
This invention was made on the basis of the above findings, in which W, Mo, W is formed on one surface of an insulating plate material made of an AlN sintered body.
Alloy, and a conductor forming thin plate material for circuit formation made of any one of the Mo alloy, the same W, M on the other surface of the insulating plate material.
The semiconductor device substrate is characterized in that a heat sink plate material made of any one of o, W alloy, and Mo alloy is joined by using a high melting point brazing material.

〔実施例〕〔Example〕

つぎに、この発明の半導体装置用基板を実施例により
具体的に説明する。
Next, the semiconductor device substrate of the present invention will be specifically described with reference to examples.

第1図に示されるように、絶縁板材Cとして、幅:50m
m×厚さ:0.63mm×長さ:75mmの寸法もった純度:99%のAl
N焼結体を用意し、また第1表に示される材質からな
り、かつ幅:45mm×厚さ:0.3mm×長さ:70mmの寸法をもっ
た回路形成用導体薄板材B、並びに幅:50mm×厚さ:3mm
×長さ:75mmの寸法をもったヒートシンク板材Aをそれ
ぞれ用意し、これらをそれぞれ第1表に示される高融点
ろう材Dを間にはさんで重ね合わせた状態で、真空中、
温度:880℃に10分間保持の条件でろう付けすることによ
り本発明基板1〜8を それぞれ製造した。
As shown in FIG. 1, the insulating plate material C has a width of 50 m.
m × thickness: 0.63mm × length: 75mm dimensions Purity: 99% Al
N sintered body is prepared, and it is made of the material shown in Table 1 and has a width of 45 mm x thickness: 0.3 mm x length: 70 mm, and a conductor forming thin plate material B for circuit formation, and a width: 50mm x thickness: 3mm
× Length: Prepare heat sink plate materials A each having a dimension of 75 mm, and in a state where they are superposed with the high melting point brazing filler metals D shown in Table 1, respectively, in a vacuum,
The substrates 1 to 8 of the present invention were brazed at a temperature of 880 ° C. for 10 minutes. Each was manufactured.

また、比較の目的で、第2図に示されるように絶縁板
材C′として幅:50mm×厚さ:0.63mm×長さ:75mmの寸法
をもった純度:96%のAl2O3焼結体を、また回路形成用お
よびはんだ付け用として、幅:45mm×厚さ:0.3mm×長さ:
70mmの寸法をもった無酸素銅薄板材B′(2枚)をそれ
ぞれ用意し、これら両者を重ね合わせた状態で、酸素:1
容量%含有のAr雰囲気中、温度:1075℃に50分間保持の
条件で加熱し、前記酸化性雰囲気によって形成したCu2O
とCuとの共晶による液相を接合面に発生させて接合し、
ついでこの接合体を厚さ:300μmのPb-60%Sn合金から
なるはんだ材D′を用いて、幅:50mm×厚さ:3mm×長さ:
75mmの寸法をもった無酸素銅からなるヒートシンク板材
A′の片面にはんだ付けすることにより従来基板を製造
した。
Also, for the purpose of comparison, as shown in FIG. 2, as insulating plate material C ′, width: 50 mm × thickness: 0.63 mm × length: 75 mm, purity: 96% Al 2 O 3 sintering For body and also for circuit formation and soldering, width: 45 mm × thickness: 0.3 mm × length:
Oxygen-free copper thin plate materials B '(2 sheets) having a dimension of 70 mm are prepared respectively, and in a state where these both are superposed, oxygen: 1
Cu 2 O formed in the oxidizing atmosphere by heating in an Ar atmosphere containing 10% by volume at a temperature of 1075 ° C. for 50 minutes.
And Cu by generating a liquid phase by the eutectic of Cu and Cu on the joint surface,
Then, this joined body was used with a solder material D ′ made of Pb-60% Sn alloy having a thickness of 300 μm, and width: 50 mm × thickness: 3 mm × length:
A conventional substrate was manufactured by soldering to one surface of a heat sink plate material A'made of oxygen-free copper having a dimension of 75 mm.

つぎに、この結果得られた本発明基板1〜8および従
来基板に対して、温度:150℃に加熱後、−55℃に冷却を
1サイクルとする繰り返し加熱冷却試験を行ない、本発
明基板については、絶縁板材Cと導体薄板材Bおよびヒ
ートシンク板材A間の剥離、および絶縁板材Cの割れが
発生するに至るまでのサイクル数を20サイクル毎に観察
し、また従来基板については、Cu薄板材B′とヒートシ
ンク板材A′間の剥離、および絶縁板材C′の割れが発
生するに至るまでのサイクル数を同じく20サイクル毎に
観察し、測定した。これらの結果を第1表に示した。
Next, the resulting substrates 1 to 8 of the present invention and the conventional substrate were subjected to a repeated heating and cooling test in which one cycle of heating to a temperature of 150 ° C. and then cooling to −55 ° C. was performed. Is observed every 20 cycles until the insulating plate material C is separated from the conductor thin plate material B and the heat sink plate material A, and the insulating plate material C is cracked. The number of cycles until peeling between B ′ and the heat sink plate material A ′ and cracking of the insulating plate material C ′ were also observed and measured every 20 cycles. The results are shown in Table 1.

〔発明の効果〕〔The invention's effect〕

第1表に示される結果から、本発明基板1〜8は、苛
酷な条件下での加熱・冷却の繰り返しによっても、剥離
や割れの発生がないので、すぐれた熱伝導性および放熱
性を示すのに対して、従来基板においては比較的早期に
剥離や割れが発生することが明らかである。
From the results shown in Table 1, the substrates 1 to 8 of the present invention show excellent thermal conductivity and heat dissipation because they do not cause peeling or cracking even after repeated heating and cooling under severe conditions. On the other hand, it is clear that in the conventional substrate, peeling or cracking occurs relatively early.

上述のように、この発明の半導体装置用基板は、苛酷
な温度サイクルによっても剥離や割れの発生がなく、す
ぐれた熱伝導性および放熱性を示すので、半導体装置の
高集積化および大電力化に十分に対応することができる
きわめて信頼性の高いものである。
As described above, the semiconductor device substrate of the present invention does not cause peeling or cracking even under severe temperature cycles, and exhibits excellent thermal conductivity and heat dissipation properties. Therefore, high integration and high power consumption of the semiconductor device can be achieved. It is a very reliable one that can fully cope with.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明半導体装置用基板の概略説明図、第2図
は従来半導体装置用基板の概略説明図である。 A,A′……ヒートシンク板材、B,B′……薄板材、C′…
…絶縁板材、D……高融点ろう材、D′……はんだ材。
FIG. 1 is a schematic explanatory diagram of a semiconductor device substrate of the present invention, and FIG. 2 is a schematic explanatory diagram of a conventional semiconductor device substrate. A, A '... Heat sink plate material, B, B' ... Thin plate material, C '...
... Insulating plate material, D ... High melting point brazing material, D '... Solder material.

フロントページの続き (56)参考文献 特開 昭63−289950(JP,A) 特開 昭63−65653(JP,A) 特開 昭62−226645(JP,A) 特開 昭61−30042(JP,A)Continuation of the front page (56) Reference JP 63-289950 (JP, A) JP 63-65653 (JP, A) JP 62-226645 (JP, A) JP 61-30042 (JP , A)

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】窒化アルミニウム焼結体からなる絶縁板材
の一方面に、W,Mo,W合金、およびMo合金のうちのいずれ
かからなる回路形成用導体薄板材を、前記絶縁板材の他
方面に、同じくW,Mo,W合金、およびMo合金のうちいずれ
かからなるヒートシンク板材をそれぞれ高融点ろう材を
用いて接合してなる半導体装置用基板。
1. A circuit forming conductor thin plate material made of any one of W, Mo, W alloys and Mo alloys is formed on one surface of an insulating plate material made of an aluminum nitride sintered body, and the other surface of the insulating plate material is made of And a heat sink plate material made of any one of W, Mo, W alloys, and Mo alloys, respectively, which is joined using a high melting point brazing material.
JP24709788A 1988-09-30 1988-09-30 Substrate for semiconductor device Expired - Lifetime JP2503775B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24709788A JP2503775B2 (en) 1988-09-30 1988-09-30 Substrate for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24709788A JP2503775B2 (en) 1988-09-30 1988-09-30 Substrate for semiconductor device

Publications (2)

Publication Number Publication Date
JPH0294649A JPH0294649A (en) 1990-04-05
JP2503775B2 true JP2503775B2 (en) 1996-06-05

Family

ID=17158385

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24709788A Expired - Lifetime JP2503775B2 (en) 1988-09-30 1988-09-30 Substrate for semiconductor device

Country Status (1)

Country Link
JP (1) JP2503775B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1020914B1 (en) * 1989-10-09 2004-04-28 Mitsubishi Materials Corporation Ceramic substrate used for fabricating electric or electronic circuit
JP3769139B2 (en) * 1999-03-04 2006-04-19 三菱電機株式会社 Power semiconductor module
JP3676268B2 (en) 2001-08-01 2005-07-27 株式会社日立製作所 Heat transfer structure and semiconductor device
US10347559B2 (en) * 2011-03-16 2019-07-09 Momentive Performance Materials Inc. High thermal conductivity/low coefficient of thermal expansion composites

Also Published As

Publication number Publication date
JPH0294649A (en) 1990-04-05

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