JPS59113630A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS59113630A
JPS59113630A JP57223188A JP22318882A JPS59113630A JP S59113630 A JPS59113630 A JP S59113630A JP 57223188 A JP57223188 A JP 57223188A JP 22318882 A JP22318882 A JP 22318882A JP S59113630 A JPS59113630 A JP S59113630A
Authority
JP
Japan
Prior art keywords
layer
wiring
alloy
alumina
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57223188A
Other languages
Japanese (ja)
Inventor
Hiroyuki Ishiwatari
広行 石渡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57223188A priority Critical patent/JPS59113630A/en
Publication of JPS59113630A publication Critical patent/JPS59113630A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Abstract

PURPOSE:To bond an electric wire in gold or aluminum excellently with a second layer wiring without precipitating Cu on the interface of the second layer wiring by forming an alumina layer on the second layer wiring formed in two layer structure of an Al/Cu alloy and an Al/Si alloy. CONSTITUTION:A through-hole 12a is bored to a PSG film 12, a wiring layer of two layer structure is grown and formed while positioning the Al/Cu alloy 13a at a lower section and the Al/Si alloy 13b at an upper section through sputtering, and the wiring layer is patterned to form the second layer wiring 13. The alumina layer 14 is formed through an anodic oxidation method using an oxalic acid liquid, and a cover film 15 for PSG is formed through a chemical vapor phase growth method. The precipitation of Cu to the interface of the second layer wiring 13 is inhibited because the alumina layer 14 is formed on the second layer wiring layer 13 at that time. An electrode window 15a is formed through dry etching using CHF3 gas, the alumina layer 14 of the window section is also removed through etching, and the electric wire in gold or aluminum is bonded with the two layer wiring 13 exposed in the electrode window 15a through wire bonding.

Description

【発明の詳細な説明】 （１１発明の技術分野 本発明は半導体装置の製造方法、詳しくは半導体製造プ
ロセスにおける多層配線形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION (11) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming multilayer wiring in a semiconductor manufacturing process.

（２）技術の背景 半導体装置の製造工程において、集積度を高める目的で
多層配線を形成することが広く行われている。例を２層
配線にとって説明すると、第１図（ａｌの半導体装置要
部すなわちスルーボール部分の断面図に示される如く、
半導体基板１上に絶縁膜例えば燐・シリケート・ガラス
（ＰｓＧ）　Ｂ’Ａ　（以下にはＰＳＧ膜という）２を
形成し、このＰＳＧ膜２にスルーホール２ａを窓開けし
、次いで２層目配線３を、下にアルミニウム・銅合金Ａ
Ｐ／Ｃｕ３ａと、上にアルミニウム・シリコン合金Ａβ
／５ｉ３ｂの２層構造にスパッターによって形成する。(2) Background of the Technology In the manufacturing process of semiconductor devices, it is widely practiced to form multilayer wiring for the purpose of increasing the degree of integration. To explain an example using two-layer wiring, as shown in the cross-sectional view of the main part of the semiconductor device, that is, the through ball part in
An insulating film such as phosphorus silicate glass (PsG) B'A (hereinafter referred to as PSG film) 2 is formed on a semiconductor substrate 1, a through hole 2a is opened in this PSG film 2, and then a second layer wiring is formed. 3, aluminum/copper alloy A below
P/Cu3a and aluminum silicon alloy Aβ on top
A two-layer structure of /5i3b is formed by sputtering.

次に、第１図（ｂｌに示される如く、全面にＰＳＧのカ
バー膜４を形成し、次いでこのカバー膜４の前記したス
ルーホール２ａの上方の部分に電極窓を形成し、この電
極窓を通して金またはアルミニウムの電線を２層目配線
３に公知のワイヤポンディ　７ング技術で接着し、２層
目配線３と外部配線との接続をとる。Next, as shown in FIG. 1 (bl), a PSG cover film 4 is formed on the entire surface, and then an electrode window is formed in the above-described through hole 2a of the cover film 4, and the electrode window is passed through the cover film 4. A gold or aluminum wire is bonded to the second layer wiring 3 using a known wire bonding technique to establish a connection between the second layer wiring 3 and external wiring.

ＡＪ／Ｃｕ合金３ａが用いられる理由はそれの電流容量
が大であるからであり、またＡｌ１Ｓｉ合金は前記した
金またはアルミニウム電線との接着がよいので、＾ｆｆ
ｉ／Ｃｕ合金＋＾ｆｆｉ／Ｓｔ合金の２１ｅｔ構造にお
いてＡＩｌ／Ｓｉ合金は電線が接着される表面層として
形成される。The reason why AJ/Cu alloy 3a is used is that it has a large current capacity, and the Al1Si alloy has good adhesion to the gold or aluminum electric wire mentioned above.
In the 21et structure of the i/Cu alloy+^ffi/St alloy, the Al/Si alloy is formed as a surface layer to which the wires are bonded.

（３）従来技術と問題点 上記したカバー１１契４ば、４２５℃の温度におけるＰ
ＳＧの化学気相成長法によって形成される。このとき、
４２５℃の加熱によって、　ＡＩｌ／Ｃｕ合金がＡｊ！
／Ｓｉ合金と共晶し、Ｃｕ成分が２層目配線３の表面に
析出する。このＣｕ成分は、前記した金またはアルミニ
ウムとの密着性が悪く、電線をワイヤボンディングで接
着しようとしても電線が良好に接着されない。そこで、
従来技術においては、前記した電極窓の形成後にスパッ
ター装置を用い逆スパッターによって析出したＣｕをエ
ツチング除去する。この工程は、高価な装置を用いる時
間のかかる工程であり、半導体装置の歩留り向上の見地
から改良が要望されている。(3) Prior art and problems When the above-mentioned cover 11 is connected, P at a temperature of 425°C
It is formed by the SG chemical vapor deposition method. At this time,
By heating at 425℃, the AIl/Cu alloy becomes Aj!
/Si alloy, and the Cu component is precipitated on the surface of the second layer wiring 3. This Cu component has poor adhesion to the above-mentioned gold or aluminum, and even if an attempt is made to bond the electric wires by wire bonding, the electric wires will not be bonded well. Therefore,
In the prior art, after the electrode window is formed, the deposited Cu is etched away by reverse sputtering using a sputtering device. This process is a time-consuming process that requires expensive equipment, and improvements are desired from the standpoint of increasing the yield of semiconductor devices.

（４）発明の目的 本発明は上記従来の問題点に鑑み、半導体プロセスの多
層配線を形成するための工程において、Ａｆｆｉ／Ｃｕ
合金と＾＃’／Ｓｉ合金の２層構造の２層目配線を用い
た場合に、カバー膜の成長時におけるＡＡ！／Ｃｕ合金
と　へβ／Ｓｉ合金の共晶によるＣｕの配線表面すなわ
ち界面への析出を抑止し、前記２層目配線への電線の接
着が改善される如き多層配線形成方法の提供を目的とす
る。(4) Purpose of the Invention In view of the above-mentioned conventional problems, the present invention provides a process for forming multilayer wiring in a semiconductor process using Affi/Cu.
When using a second layer wiring with a two-layer structure of alloy and ^#'/Si alloy, the AA! during growth of the cover film! The purpose of the present invention is to provide a method for forming multilayer wiring in which the deposition of Cu on the wiring surface, that is, the interface, by the eutectic of the /Cu alloy and the β/Si alloy is suppressed, and the adhesion of the electric wire to the second layer wiring is improved. do.

（５）発明の構成 そしてこの目的は本発明によれば、半導体基板上に絶縁
膜を形成し、この絶縁膜にスルーホールを形成する工程
、下はアルミニウム・銅合金、上はアルミニウム・シリ
コン合金の２層構造の配線層を形成しそれをバターニン
グして２層目配線を形成する工程、２層目配線上にアル
ミナ映を形成する工程、全面にカバー膜を成長し、この
カバー膜に電極窓をエツチングで形成し１．前記エツチ
ングにより電極窓の部分の前記アルミナ層をも除去して
２１砺目配線を露出する工程を含むことを特徴とする半
導体装置の製造方法を提供することによって達成される
。(5) Structure and purpose of the invention According to the present invention, an insulating film is formed on a semiconductor substrate and a through hole is formed in this insulating film. A process of forming a wiring layer with a two-layer structure and buttering it to form a second layer of wiring, a process of forming an alumina film on the second layer of wiring, a process of growing a cover film on the entire surface, and forming a cover film on the entire surface. Forming an electrode window by etching 1. This is achieved by providing a method for manufacturing a semiconductor device characterized by including the step of also removing the alumina layer in the electrode window portion by the etching to expose the 21st wire.

（６）発明の実施例 以下本発明実施例を図面によって詳述する。(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

第２図に本発明の方法を実施する工程における半導体装
置の要部すなわちスルーボール部分が断面図で示される
。FIG. 2 shows a cross-sectional view of the main part of the semiconductor device, that is, the through-ball part, in the process of carrying out the method of the present invention.

従来技術の場合と同様に、半導体基板ｌｌ上に１μ箱の
膜厚のＰＳＧＩＩ灸１２を形成し、このｐｓｃｌｌ美１
２にスルーボール１２ａ（例えば１．５μｍの幅）全窓
開けし、スパッターによってそれぞれ０．６μｍの厚さ
のＡ６／Ｃｕ合全Ｃｕａとへ＃／Ｓｉ合金１３ｂの２層
構造の配線層を、Ａβ／Ｃｕ合金は下にまたＡβ／Ｓｉ
合金は上に成長して形成し、それをパターニングして２
層目配線１３を形成する（第２図（ａ））。As in the case of the prior art, a PSGII film 12 with a film thickness of 1 μm is formed on a semiconductor substrate 11, and this pscll film 12 is
2, a full window is opened in the through ball 12a (for example, a width of 1.5 μm), and a wiring layer with a two-layer structure of A6/Cu alloy 13b and #/Si alloy 13b with a thickness of 0.6 μm is formed by sputtering. The Aβ/Cu alloy also has Aβ/Si below.
The alloy is grown on top, formed, and then patterned to form 2
Layer wiring 13 is formed (FIG. 2(a)).

次に公知のシュウ酸液を用いる陽極酸化法によってへβ
／Ｓｉ合金１３ｂの上に１００人〜２００人の厚さのア
ルミナｌ１ｉ１４を形成するく第２図（ｂ））。この工
程は簡単で安価な装置を用い、半導体基板１枚当り１０
秒程度の短時間で実施可能である。なおこの薄いアルミ
ナ層１４ば、図において誇張して大なる膜厚で図示しで
ある。Next, β was obtained by anodizing using a known oxalic acid solution
Alumina l1i14 having a thickness of 100 to 200 mm is formed on the /Si alloy 13b (FIG. 2(b)). This process uses simple and inexpensive equipment, and uses 10
It can be carried out in a short time of about seconds. Note that this thin alumina layer 14 is shown exaggerated in the drawings to have a large thickness.

次に、４２５℃の温度の化学気相成長法によりＰＳＧの
カバー１１央１５を１μｍの膜厚に形成する（第２図（
Ｃ））。このとき、２層目配線層１３の上にはアルミナ
層１４が形成されているので、２層目配線１３の界面へ
のＣｕの析出が抑止される。Next, the center 15 of the PSG cover 11 is formed to a thickness of 1 μm by chemical vapor deposition at a temperature of 425°C (see Fig. 2).
C)). At this time, since the alumina layer 14 is formed on the second wiring layer 13, precipitation of Cu on the interface of the second wiring layer 13 is suppressed.

次いで、Ｃ肝３ガスを用いるドライエツチングで、１．
５μｍ口の電極窓Ｌ５ａを形成し、このエツチングで電
極窓１５ａの部分のアルミナ層１４をもエツチング除去
する。なお、絶縁不良を発生することのないよう、アル
ミナ層１４はエツチングに十分時間をかけて完全に除去
する（第２図（ｄ））。Next, by dry etching using C liver 3 gas, 1.
A 5 μm electrode window L5a is formed, and the alumina layer 14 at the electrode window 15a is also etched away by this etching. It should be noted that the alumina layer 14 is etched for a sufficient amount of time to be completely removed in order to prevent insulation defects (FIG. 2(d)).

以下、金またはアルミニウムの電線をワイヤボンディン
グにより、電極窓１５ａ内に露出した２層配線１３に接
着するが、この配線１３の表面はＡβ／Ｓｉ合金であり
、そこにはｃｂが析出していないので、良好な電線接着
がなされる。Hereinafter, a gold or aluminum wire is bonded to the two-layer wiring 13 exposed in the electrode window 15a by wire bonding, but the surface of this wiring 13 is an Aβ/Si alloy, and no CB is precipitated there. Therefore, good wire adhesion is achieved.

（７）発明の効果 以上詳細に説明したように、本発明の方法によるときは
、　＾ｊ！／Ｃｕ合金とＡ＃／Ｓｉ合金の２層構造で形
成した２層目配線の上にアルミナ層を形成することによ
り、カバー膜成長時に基板に４２５℃の熱が加えられて
も、２層目配線界面にＣｕが析出することなく、このア
ルミナ層はカバー１１史に電極窓を形成するエツチング
工程で容易に除去されるので、２層目配線への金または
アルミニウムの電線接着は良好になされ、上記のアルミ
ナ層形成工程は、公知の簡単かつ安価な装置を用い短時
間内に実施可能であるので、半導体装置の製造歩留りの
向上に効果大である。(7) Effects of the invention As explained in detail above, when using the method of the present invention, ^j! By forming an alumina layer on the second layer wiring formed with a two-layer structure of /Cu alloy and A#/Si alloy, the second layer can be Since this alumina layer is easily removed in the etching process for forming electrode windows on the cover 11 without depositing Cu on the wiring interface, the adhesion of the gold or aluminum wire to the second layer wiring is good. The alumina layer forming step described above can be carried out within a short time using known simple and inexpensive equipment, and is therefore highly effective in improving the manufacturing yield of semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の多層配線形成方法を実施する工程におけ
る半導体装置要部の断面図、第２図は本発明の方法を実
施する工程における半導体装置要部の断面図である。 １１−半導体基板、１２−　ＰＳＧ　模、１２ａ　−ス
ルーホール、１３−２層目配線、１３ａ　−へＩｌ／Ｃ
ｕ合金、１３ｂ　−へｎ／Ｓｉ合金、１４−　アルミナ
層、１５−　カバー膜、１５ａ　−−電極窓 第１１ （ａ） 第２ 図 （ｂ） 図 ）FIG. 1 is a sectional view of a main part of a semiconductor device in a step of implementing a conventional multilayer interconnection forming method, and FIG. 2 is a sectional view of a main part of a semiconductor device in a step of implementing a method of the present invention. 11-Semiconductor substrate, 12-PSG pattern, 12a-Through hole, 13-2nd layer wiring, 13a-Il/C to
u alloy, 13b - n/Si alloy, 14 - alumina layer, 15 - cover film, 15a - electrode window 11 (a) Fig. 2 (b) Fig.)

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に絶縁膜を形成し、この絶縁膜にスルーホ
ールを形成する工程、下はアルミニウム・銅合金、上は
アルミニウム・シリコン合金の２層構造の配線層を形成
しそれをパターニングして２層目配線を形成する工程、
２層目配線上にアルミナ膜を形成する工程、全面にカバ
ー膜を成長し、このカバー膜に電極窓をエツチングで形
成し、前記エツチングにより電極窓の部分の前記アルミ
ナ層をも除去して２層目配線を６出する工程を含むこと
を特徴とする半導体装置の製造方法。A process of forming an insulating film on a semiconductor substrate and forming through holes in this insulating film, forming a wiring layer with a two-layer structure of aluminum/copper alloy on the bottom and aluminum/silicon alloy on the top, and patterning it. a step of forming layer wiring;
In the step of forming an alumina film on the second layer wiring, a cover film is grown on the entire surface, an electrode window is formed on this cover film by etching, and the alumina layer in the electrode window portion is also removed by the etching. A method for manufacturing a semiconductor device, comprising the step of producing six layer wirings.
JP57223188A 1982-12-20 1982-12-20 Manufacture of semiconductor device Pending JPS59113630A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57223188A JPS59113630A (en) 1982-12-20 1982-12-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57223188A JPS59113630A (en) 1982-12-20 1982-12-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS59113630A true JPS59113630A (en) 1984-06-30

Family

ID=16794175

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57223188A Pending JPS59113630A (en) 1982-12-20 1982-12-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59113630A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0251232A (en) * 1988-06-29 1990-02-21 Philips Gloeilampenfab:Nv Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0251232A (en) * 1988-06-29 1990-02-21 Philips Gloeilampenfab:Nv Manufacture of semiconductor device

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