JPS63311745A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63311745A JPS63311745A JP14713587A JP14713587A JPS63311745A JP S63311745 A JPS63311745 A JP S63311745A JP 14713587 A JP14713587 A JP 14713587A JP 14713587 A JP14713587 A JP 14713587A JP S63311745 A JPS63311745 A JP S63311745A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- bump
- bumps
- barrier metal
- window
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000007747 plating Methods 0.000 claims abstract description 13
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 10
- 230000004888 barrier function Effects 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 238000009713 electroplating Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims 2
- 230000000717 retained effect Effects 0.000 abstract 1
- 239000010931 gold Substances 0.000 description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 102100024282 Dynein axonemal assembly factor 11 Human genes 0.000 description 1
- 101000831210 Homo sapiens Dynein axonemal assembly factor 11 Proteins 0.000 description 1
- 241000238814 Orthoptera Species 0.000 description 1
- 241000797947 Paria Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- GOQFGEHFZBDYEC-UHFFFAOYSA-N [AlH2+] Chemical compound [AlH2+] GOQFGEHFZBDYEC-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
Ｃ′概要〕
ＴＡＢに用いるバンプ形成時に設けるレジストを、バン
プ形成部分にのみ局部的に残すことによりレジストにク
ランクが発生することを防止し、バンプを安定して再現
性良く形成する。[Detailed Description of the Invention] C'Summary] By leaving the resist provided during bump formation for TAB locally only in the bump formation area, cranks are prevented from occurring in the resist, and bumps can be formed stably and reproducibly. Form well.
本発明は半導体装置の製造方法に関し、特にテープ・オ
ートマティック・ボンディング（Ｔａｐｅ＾ｕｔｏｓａ
ｔｉｃ Ｂｏｎｄｉｎｇ、 ＴＡＢ）に用いるバンプを
安定に再現性良くメッキする方法に関する。The present invention relates to a method of manufacturing a semiconductor device, and in particular to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device.
This invention relates to a method for stably and reproducibly plating bumps used in tic bonding (TAB).
第３図の従来例平面図を参照すると、半導体チップ３１
に形成された電極３２と配線３３の接続方法としては、
ワイヤボンディング法が用いられていた。Referring to the conventional example plan view of FIG.
The method for connecting the electrode 32 and wiring 33 formed in
A wire bonding method was used.
図示しないボンディング装置から配線３３を引き出し、
配線３３の端部を電極３２上に配置し、例えば超音波を
用いて図示しないウェッジで配線３３を電極３２上に接
着する。かかる方法の実施においては、ポンディング装
置のウェッジなどの寸法の関係から電極３２間には所定
の距離をとらなければならず、それが半導体チップ３１
の集積度を高める際の障害であった。The wiring 33 is pulled out from a bonding device (not shown),
The end of the wiring 33 is placed on the electrode 32, and the wiring 33 is bonded onto the electrode 32 with a wedge (not shown) using, for example, ultrasonic waves. In implementing such a method, a predetermined distance must be maintained between the electrodes 32 due to the dimensions of the wedge of the bonding device, and this distance must be maintained between the semiconductor chips 31 and 32.
This was an obstacle to increasing the degree of integration.
かかる問題を解決するために開発されたのが第４図に示
されるＴＡＢ方式で、半導体基板４１上に形成された例
えばアルミニウム（ｉ）の電極４２（この電極は第３図
の電極３２に相当する）上に作られた絶縁膜４３に窓開
けし、この開口部にバリアメタル４４を介して金（Ａｕ
）のバンプ４５が設けられている。バンプ４５とのコン
タクトをとるには、テープに貼り付けたインナーリード
４６をバンプ４５に熱圧着し、バンプ４５とインナーリ
ード４６とを接続する。この方法によると、バンプ４５
のｅ７チを１００８ｍと小にすることができるだけでな
く、すべての電極４５とすべてのインナーリード４６と
を一時に接続することができる利点がある。The TAB method shown in FIG. 4 was developed to solve this problem, in which an electrode 42 of, for example, aluminum (i) is formed on a semiconductor substrate 41 (this electrode corresponds to the electrode 32 in FIG. 3). A window is opened in the insulating film 43 formed on the insulating film 43 formed on the insulating film 43 formed on the
) bumps 45 are provided. In order to make contact with the bump 45, the inner lead 46 attached to the tape is thermocompression bonded to the bump 45, and the bump 45 and the inner lead 46 are connected. According to this method, the bump 45
There is an advantage that not only can the e7 length of the circuit be reduced to 1008 m, but also that all the electrodes 45 and all the inner leads 46 can be connected at the same time.
第４図に示すバンプ４５を作るには、第５図の断面図を
参照すると、半導体基Ｆｉ４１上にＡＩの電極４２、絶
縁膜４３を作り、それに図示の如く窓開けをな°した後
に全面にバリアメタル４４をスパッタまたは蒸着で形成
し、全面にレジスト４７を塗布しそれを図示の如くパタ
ーニングし、次いで金をメッキしてバンプ４５を作る。To make the bump 45 shown in FIG. 4, referring to the cross-sectional view in FIG. A barrier metal 44 is formed by sputtering or vapor deposition, a resist 47 is applied to the entire surface and patterned as shown, and then gold is plated to form bumps 45.
このレジスト４７の膜厚は３０μｍ程度にする。The film thickness of this resist 47 is approximately 30 μm.
レジスト４７を３０μｍと膜厚大に形成する理由はレジ
ストを第６図に示す如＜１．０μｍ程度に薄く作ると、
金のメッキにおいてメッキされる金が等方的に拡がって
、きのこ状の形のものとなる。そうなると、横に拡がっ
た拡大部が高集積化の妨げとなるだけでなく、バンプの
幅Ｗがバンプと Ａｌ電極の接触部の幅Ｗ°よりも大き
くなりすぎ、バンプが不安定になってバンプと電極との
間の接触不良の原因となる。さらには、拡大部の存在に
よって、バンプと電極との接触状態を点検し難くなる問
題もある。そこで、レジストを厚くして第４図、５図に
示されるストレート・バンプと呼称される拡がることな
く直立したバンプを形成するようになった。なお前記し
たバリアメタルには、Ａ６．Ａｕとの間の反応を防止し
、導電性が良く （低抵抗の）、かつＡＩ、Ａｕとの密
着性の良いパラジウム（Ｐｄ）チタン（Ｔｉ）などを用
いる。第５図のレジスト４７を除去し、金のバンプ４５
をマスクにしてバリアメタル４４をエツチングすると、
第４図に示される構造が得られる。The reason why the resist 47 is formed as thick as 30 μm is that if the resist is made as thin as <1.0 μm as shown in FIG.
In gold plating, the gold plated spreads out isotropically, forming a mushroom-like shape. If this happens, not only will the horizontally expanding portion become an impediment to high integration, but the width W of the bump will become too large than the width W° of the contact area between the bump and the Al electrode, making the bump unstable and causing the bump to become unstable. This may cause poor contact between the electrode and the electrode. Furthermore, the presence of the enlarged portion makes it difficult to inspect the contact state between the bump and the electrode. Therefore, the resist was made thicker to form bumps that stand upright without spreading, which are called straight bumps as shown in FIGS. 4 and 5. Note that the barrier metal mentioned above includes A6. Palladium (Pd), titanium (Ti), etc., which prevent reactions with Au, have good conductivity (low resistance), and have good adhesion to AI and Au are used. The resist 47 in FIG. 5 is removed and the gold bumps 45 are removed.
When the barrier metal 44 is etched using as a mask,
The structure shown in FIG. 4 is obtained.
従来方法を説明する第５図を再び参照すると、レジスト
４７は３０μ僧と厚くウェハ全体にわたって塗布される
。このように厚いレジストが広い面積にわたって塗布さ
れると、熱膨張係数の差によってレジストにクランク（
割れ目）が発生する。そうなると、メッキでバンプを作
るときに、クランク内にも電流が流れ、バンプ形成部分
に流れる電流にバラツキが生じ、バンプが安定性、再現
性良（形成されないだけでなく、場合によっては所定の
厚さのバンプがメッキされない問題がある。Referring again to FIG. 5 for explaining the conventional method, the resist 47 is applied to a thickness of 30 μm over the entire wafer. When such thick resist is applied over a large area, the difference in thermal expansion coefficients causes the resist to crank (
cracks) occur. In this case, when creating bumps by plating, current also flows inside the crank, causing variations in the current flowing to the bump forming area, resulting in bumps that are not only not formed but also have a specified thickness. There is a problem that the bumps are not plated.
本発明はこのような点に鑑みて創作されたちので、数十
ミクロンの膜厚のレジストを用いてバンプをメッキする
場合に、レジストにクランクが発生“することを防止し
、バンプを安定性、再現性良くメッキする方法を提供す
ることを目的とする。The present invention was created with these points in mind, and is designed to prevent "crank" from occurring in the resist when plating bumps using a resist with a film thickness of several tens of microns, and to improve the stability and stability of the bumps. The purpose is to provide a method for plating with good reproducibility.
第１図は本発明第１実施例の断面図で、図中、１１は半
導体基板（シリコンウェハ）、１２はＳｉＯ２膜、１３
は例えばＡｆｆｉの電極、１４は例えばＰＳＧの絶縁膜
、１５はバリアメタル、１６はレジスト、１７はバンプ
である。FIG. 1 is a cross-sectional view of the first embodiment of the present invention, in which 11 is a semiconductor substrate (silicon wafer), 12 is a SiO2 film, and 13 is a sectional view of the first embodiment of the present invention.
14 is an insulating film such as PSG, 15 is a barrier metal, 16 is a resist, and 17 is a bump.
本発明第１実施例においては、レジスト１６を３０μｍ
の厚さに塗布した後に、バンプ１７形成部分（電極１２
の上方部分）に局部的にレジストをそのままの厚さで残
し、バンプ形成部分以外の部分ではパリアメクルをメッ
キにおいてマスクする程度のレジスト １６ａを残す如
くにパターニングし、しかる後にメッキによってバンプ
１７を形成する。本発明の第２実施例においては、バリ
アメタル１５の上に絶縁膜（例えばＣＶＤ ５ｉ０２膜
）１８を形成し、その上にレジスト１６を塗布し、バン
プ形成部分にのみ第２図に示される如（レジストを残し
、次いでメッキを行ってバンプ１７を形成する。In the first embodiment of the present invention, the resist 16 has a thickness of 30 μm.
After coating the bump 17 forming part (electrode 12
The resist is left locally at the same thickness in the upper part), and the resist 16a is left in areas other than the bump forming part to the extent that it masks the palliameckle during plating, and then the bumps 17 are formed by plating. . In the second embodiment of the present invention, an insulating film (for example, a CVD 5i02 film) 18 is formed on the barrier metal 15, a resist 16 is applied thereon, and only the bump forming portion is coated with the insulating film 18 as shown in FIG. (The resist is left and then plating is performed to form the bumps 17.
第３図には第１図のレジストが平面図で示される。この
ようにバンプ形成部分にのみ局部的に狭い領域にレジス
トを残すと、従来例にみられたクランクの発生が防止さ
れ、バンプが安定性、再現性良くメッキされることが実
験で確かめられた。FIG. 3 shows the resist of FIG. 1 in plan view. Experiments have confirmed that by leaving resist in a narrow local area only in the bump formation area, the occurrence of cranks seen in conventional methods is prevented, and the bumps are plated with good stability and reproducibility. .
以下、図面を参照して本発明の実施例を詳細に説明する
。Embodiments of the present invention will be described in detail below with reference to the drawings.
本発明の第１実施例においては、第１図（ａ）を参照す
゛ると、半導体基板１１上に５ｉＱｚ膜１２を形成し、
従来例の如く例えばＡ７！の電極１３を形成し、次いで
全面にＰＳＧ膜１４を堆積し、電極１２のほぼ中央部分
にバンプとの接触をとるための窓１９を開口し、次いで
全面にバリアメタル１５を形成する。パリアメクル１５
は例えば３０００人の厚さのバリアメタルとなるＴｉと
、３０００人の厚さの導電膜となるＩ’ｄを蒸着、ス′
バッタで堆積する。In the first embodiment of the present invention, referring to FIG. 1(a), a 5iQz film 12 is formed on a semiconductor substrate 11,
For example, A7 as in the conventional example! An electrode 13 is formed, then a PSG film 14 is deposited on the entire surface, a window 19 is opened approximately at the center of the electrode 12 for making contact with the bump, and then a barrier metal 15 is formed on the entire surface. Paria Mekuru 15
For example, Ti, which will become a barrier metal with a thickness of 3000 mm, and I'd, which will become a conductive film with a thickness of 3000 mm, are vapor-deposited and then
Deposited by locusts.
次いで、全面にネガレジスト１６を、形成すべきバンプ
の高さ例えば３０μｍの厚さに塗布する。次いで、バン
プ形成部分に第１図（ｂ）の平面図に示されるようにレ
ジストが残るようレジストをパターニングしてレジスト
に窓２０を窓開けするが、その際に、バリアメタル１５
の上にメッキにおいてバリアメタルをマスクするに足る
厚さ例えば１μｍ程度のレジスト１６ａが残るようにパ
ターニングする。 ″しかる後に電解メッキで金を
メッキしてバンプ１７を形成し、レジス）１６．１６ａ
を除去し、次にバンプ１７をマスクにしてバリアメタル
１５をエツチングし、第１図＋ａ）に示される構造を完
成させる。この実施例において、レジスト１６は膜厚は
大であるが、その面積が第１図（ｂ）に示される如く狭
いため、従来例のクラックが発生せず、バンプ１７が安
定して再現性良くメッキされた。Next, a negative resist 16 is applied to the entire surface to a thickness of, for example, 30 μm, which is the height of the bump to be formed. Next, the resist is patterned so that the resist remains in the bump formation area as shown in the plan view of FIG. 1(b), and a window 20 is opened in the resist.
A resist 16a having a thickness of about 1 μm, for example, sufficient to mask the barrier metal during plating is left on the resist 16a. ``After that, gold is plated by electrolytic plating to form bumps 17, and resists) 16.16a
Then, using the bumps 17 as a mask, the barrier metal 15 is etched to complete the structure shown in FIG. 1+a). In this embodiment, although the resist 16 has a large film thickness, its area is narrow as shown in FIG. plated.
本発明の第２実施例においては、第２図に示される如く
、第１実施例の場合と同様にバリアメタル１５を被着し
た後に、その上に絶縁膜１８を形成する。絶縁膜１８は
、例えば化学気相成長法（ＣＶＤ）法でＳｉＯ２を３０
００人程度０膜厚に成長する０次いで、バンプ形成用の
窓２０に対応する窓を絶縁膜１８に窓開けする。In the second embodiment of the present invention, as shown in FIG. 2, after the barrier metal 15 is deposited as in the first embodiment, an insulating film 18 is formed thereon. The insulating film 18 is made of SiO2 by, for example, chemical vapor deposition (CVD).
Next, a window corresponding to the window 20 for bump formation is opened in the insulating film 18.
しかる後に、バンプ形成部分にのみレジスト１６を残す
如（レジストをパターニングし、電解メッキで窓２０内
にバンプ１７を形成する。Thereafter, the resist 16 is patterned so as to remain only in the bump formation portion, and the bump 17 is formed within the window 20 by electrolytic plating.
次に、レジスト１６、続いて絶縁１１！ｔｉｌＢをエツ
チングで除去し、バンプ１７をマスクにバリアメタル１
５をエツチングして、第２図に示される構造を作る。Next, resist 16, followed by insulation 11! tilB is removed by etching, and barrier metal 1 is formed using bump 17 as a mask.
5 to produce the structure shown in FIG.
この第２実施例でも、厚い膜厚のレジスト１６はその面
積が第１図中）に示された場合と同様に小であるので、
クラックの発生は十分に抑えられ、安定したバンプ１７
がメンキされた。In this second embodiment as well, the area of the thick resist 16 is small as in the case shown in FIG.
The generation of cracks is sufficiently suppressed and the bump is stable17.
was teased.
以上述べてきたように本発明によれば、ＴＡＢのための
バンプが安定して形成され、製造歩留りの向上に有効で
あることが確認された。As described above, according to the present invention, bumps for TAB can be stably formed, and it has been confirmed that the present invention is effective in improving manufacturing yield.
第１図（ａ）は本発明第１実施例断面図、同図（ｂｌは
同図（ａ）のレジストの平面図、第２図は本発明第２実
施例断面図、
第３図は従来例電極配置の平面図、
第４図はＴＡＢ方式の断面図、
第５図はバンプの形成方法を示す断面図、第６図はきの
こ形バンプの断面図である。
第１図と第２図において、
１１は半導体基板、
１２は ＳｉＯ＋膜、
１３は電極、
１４はｐｓｃ膜、
１５はバリアメタル、
Ｉ６と１６ａはレジスト、
１７はバンプ、
１８は絶縁膜、
１９と２０は窓である。
代理人 弁理士 久木元 彰
復代理人 弁理士 大 菅 義 之
沫來例を釉りこ１の平面間
第３図
＝＝６１−４ ＞ｊ−’／−１′４６
ＴＡＢ方入の訴面閃
第４図
一り二
÷
セ
バンブの骨外べ゛禽−ｉｔ禾ず−ｒ丘バｎ第５図
きめ二Ｉ／ぐンフ０のＭ置■刀
第６図FIG. 1(a) is a sectional view of the first embodiment of the present invention, BL is a plan view of the resist shown in FIG. 1(a), FIG. 2 is a sectional view of the second embodiment of the present invention, and FIG. FIG. 4 is a cross-sectional view of the TAB method, FIG. 5 is a cross-sectional view showing the bump formation method, and FIG. 6 is a cross-sectional view of the mushroom-shaped bump. 11 is a semiconductor substrate, 12 is a SiO+ film, 13 is an electrode, 14 is a PSC film, 15 is a barrier metal, I6 and 16a are resists, 17 is a bump, 18 is an insulating film, and 19 and 20 are windows. Person: Patent attorney Hajime Kuki, agent Akifuku, patent attorney Yoshio Osuga Figure 4: 1 ri 2 ÷ Sebanbu's extra-bone baby bird-it wazu-r hill-ban Figure 5: Kime 2 I/Gunfu 0's M setting■ Sword Figure 6
Claims (2)
のバンプを形成する方法において、 バンプ（１７）のメッキに用いるレジスト（１６）を、
バンプ形成部分に窓（２０）が作られ、かつ、窓（２０
）のまわりはそのままの厚さで、かつ、電極（１２）の
上に延在するバリアメタル（１５）にはバリアメタルを
メッキにおいて被覆するに足る膜のレジスト（１６ａ）
を残す如くにパターニングし、しかる後に電解メッキを
行うことを特徴とする半導体装置の製造方法。(1) In a method of forming bumps for tape automatic bonding, the resist (16) used for plating the bumps (17) is
A window (20) is formed in the bump forming part, and the window (20)
), and the barrier metal (15) extending over the electrode (12) is coated with a resist film (16a) of sufficient thickness to cover the barrier metal during plating.
1. A method for manufacturing a semiconductor device, which comprises patterning the semiconductor device so as to leave a pattern, and then performing electrolytic plating.
を形成し、それをバンプの寸法に対応して窓開けし、し
かる後にレジスト（１６）を塗布し、このレジストを、
バンプ形成部分に作られた窓（２０）のまわりにそのま
まに残す如くにパターニングすることを特徴とする特許
請求の範囲第１項記載の方法。(2) An insulating film (18) on the barrier metal (15)
A window is formed on it according to the dimensions of the bump, and then a resist (16) is applied, and this resist is
2. A method as claimed in claim 1, characterized in that the patterning is carried out in such a way that the window (20) formed in the bump formation area remains intact.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14713587A JPS63311745A (en) | 1987-06-15 | 1987-06-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14713587A JPS63311745A (en) | 1987-06-15 | 1987-06-15 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63311745A true JPS63311745A (en) | 1988-12-20 |
Family
ID=15423358
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14713587A Pending JPS63311745A (en) | 1987-06-15 | 1987-06-15 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63311745A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0287629A (en) * | 1988-09-26 | 1990-03-28 | Nec Corp | Semiconductor device |
| US6462425B1 (en) | 1999-04-19 | 2002-10-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
| JP2009177036A (en) * | 2008-01-28 | 2009-08-06 | Casio Comput Co Ltd | Method for manufacturing semiconductor device |
-
1987
- 1987-06-15 JP JP14713587A patent/JPS63311745A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0287629A (en) * | 1988-09-26 | 1990-03-28 | Nec Corp | Semiconductor device |
| US6462425B1 (en) | 1999-04-19 | 2002-10-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
| JP2009177036A (en) * | 2008-01-28 | 2009-08-06 | Casio Comput Co Ltd | Method for manufacturing semiconductor device |
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