JPS59101447U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS59101447U
JPS59101447U JP1982197776U JP19777682U JPS59101447U JP S59101447 U JPS59101447 U JP S59101447U JP 1982197776 U JP1982197776 U JP 1982197776U JP 19777682 U JP19777682 U JP 19777682U JP S59101447 U JPS59101447 U JP S59101447U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
semiconductor
semiconductor device
metal wire
thin metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1982197776U
Other languages
Japanese (ja)
Inventor
中川 正美
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP1982197776U priority Critical patent/JPS59101447U/en
Publication of JPS59101447U publication Critical patent/JPS59101447U/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は出力部をシングルエンドプッシュプル接続した
音声増巾装置の回路例、第2図は半導体集積回路装置の
一部透視平面図、第3図は第2図半導体装置に用いられ
る半導体ペレットの一部平面図、第4図は本考案による
半導体装置に用いられる半導体ベレットを形成したウェ
ハの一部平面図、第5図は第4図ペレットの出力′部を
示す−・一部4・回路図、第6図は第4図ウニ/>の検
査法を示す接続図、第7図は本考案による半導体装置の
−1一部透視平面図、第8図は本考案の他の実施例を示
す要部平面図である。 19 a −−−−−−外部リード、20a、20b、
20′・・・・・・金属細線、24・・・・・・ベレッ
ト、Q?’ + QIO′・・・・・・半導体素子、E
、 C・・・・・・出力電極。
Figure 1 is a circuit example of an audio amplification device in which the output section is connected in a single-end push-pull manner, Figure 2 is a partially transparent plan view of a semiconductor integrated circuit device, and Figure 3 is a semiconductor pellet used in the semiconductor device shown in Figure 2. FIG. 4 is a partial plan view of a wafer on which a semiconductor pellet used in a semiconductor device according to the present invention is formed, and FIG. 6 is a connection diagram showing the inspection method of FIG. 4, FIG. 7 is a partially transparent plan view of the semiconductor device according to the present invention, and FIG. 8 is another embodiment of the present invention. FIG. 19a -------External lead, 20a, 20b,
20'...Thin metal wire, 24...Bellet, Q? ' + QIO'... Semiconductor element, E
, C...Output electrode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 同一ペレット内に形成され独立した出力電極を有する一
対の半導体素子の各出力電極と外部リードとをそれぞれ
金属細線にて接続しシングルエン ・ドブツシュプル接
続したことを特徴とする半導体装置。
A semiconductor device characterized in that each output electrode of a pair of semiconductor elements formed in the same pellet and having independent output electrodes and an external lead is connected by a thin metal wire to form a single-end dobutsu pull connection.
JP1982197776U 1982-12-24 1982-12-24 semiconductor equipment Pending JPS59101447U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982197776U JPS59101447U (en) 1982-12-24 1982-12-24 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982197776U JPS59101447U (en) 1982-12-24 1982-12-24 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS59101447U true JPS59101447U (en) 1984-07-09

Family

ID=30423272

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982197776U Pending JPS59101447U (en) 1982-12-24 1982-12-24 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS59101447U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006344643A (en) * 2005-06-07 2006-12-21 Sanyo Electric Co Ltd Battery pack

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006344643A (en) * 2005-06-07 2006-12-21 Sanyo Electric Co Ltd Battery pack
JP4716795B2 (en) * 2005-06-07 2011-07-06 三洋電機株式会社 Pack battery

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