JPS5910049A - クロツク再生方式 - Google Patents

クロツク再生方式

Info

Publication number
JPS5910049A
JPS5910049A JP57117991A JP11799182A JPS5910049A JP S5910049 A JPS5910049 A JP S5910049A JP 57117991 A JP57117991 A JP 57117991A JP 11799182 A JP11799182 A JP 11799182A JP S5910049 A JPS5910049 A JP S5910049A
Authority
JP
Japan
Prior art keywords
circuit
signal
envelope curve
adder
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57117991A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0134414B2 (enrdf_load_stackoverflow
Inventor
Tokihiro Mishiro
御代　時博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57117991A priority Critical patent/JPS5910049A/ja
Publication of JPS5910049A publication Critical patent/JPS5910049A/ja
Publication of JPH0134414B2 publication Critical patent/JPH0134414B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP57117991A 1982-07-07 1982-07-07 クロツク再生方式 Granted JPS5910049A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57117991A JPS5910049A (ja) 1982-07-07 1982-07-07 クロツク再生方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57117991A JPS5910049A (ja) 1982-07-07 1982-07-07 クロツク再生方式

Publications (2)

Publication Number Publication Date
JPS5910049A true JPS5910049A (ja) 1984-01-19
JPH0134414B2 JPH0134414B2 (enrdf_load_stackoverflow) 1989-07-19

Family

ID=14725318

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57117991A Granted JPS5910049A (ja) 1982-07-07 1982-07-07 クロツク再生方式

Country Status (1)

Country Link
JP (1) JPS5910049A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3417083B2 (ja) 1994-10-04 2003-06-16 セイコーエプソン株式会社 携帯用無線機

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55112059A (en) * 1979-02-22 1980-08-29 Nec Corp Clock extracting circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55112059A (en) * 1979-02-22 1980-08-29 Nec Corp Clock extracting circuit

Also Published As

Publication number Publication date
JPH0134414B2 (enrdf_load_stackoverflow) 1989-07-19

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