JPS5897846U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5897846U
JPS5897846U JP19588281U JP19588281U JPS5897846U JP S5897846 U JPS5897846 U JP S5897846U JP 19588281 U JP19588281 U JP 19588281U JP 19588281 U JP19588281 U JP 19588281U JP S5897846 U JPS5897846 U JP S5897846U
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor equipment
ridge
brazing material
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19588281U
Other languages
English (en)
Inventor
下斗米　将昭
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP19588281U priority Critical patent/JPS5897846U/ja
Publication of JPS5897846U publication Critical patent/JPS5897846U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は従来の半導体装置を示すリードフレー　゛ム部
の平面図、第２図は第１図のリードフレームの電極部に
トランジスタ素子を接着している状態を示す正面図、第
３図はこの考案の一実施例による半導体装置を示すリー
ドフレーム部の平面図、　　　　゛第４図は第３図のリ
ードフレームの電極部にトランジスタ素子を接着してい
る状態を示す正面図で、ある。 ７・・・ろう材、８・・・トランジスタ素子、１１・・
・リードフレーム、１３・・・電極部、１３ｂ・・・山
高状面。 なお、図中同一符号は同−又は相当部分を示す。

Claims (3)

    【実用新案登録請求の範囲】
  1. （１）　　リードフレームの電極の半導体素子がろう材
    接着される箇所の面を山高状面に形成し、上記ろう材の
    溶融による気体の巻込みをなくしたことを特徴とする半
    導体装置。
  2. （２）電極部の山高状面を球状面にしたことを特徴とす
    る実用新案登録請求の範囲第１項記載の半導体装置。
  3. （３）　　電極部の山高状面をかまぼこ状面にしたこと
    を特徴とする実用新案登録請求の範囲第１項記載の半導
    体装置。
JP19588281U 1981-12-24 1981-12-24 半導体装置 Pending JPS5897846U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19588281U JPS5897846U (ja) 1981-12-24 1981-12-24 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19588281U JPS5897846U (ja) 1981-12-24 1981-12-24 半導体装置

Publications (1)

Publication Number Publication Date
JPS5897846U true JPS5897846U (ja) 1983-07-02

Family

ID=30109140

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19588281U Pending JPS5897846U (ja) 1981-12-24 1981-12-24 半導体装置

Country Status (1)

Country Link
JP (1) JPS5897846U (ja)

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