JPS5896763A - 絶縁ゲート型電界効果トランジスタ素子の製造方法 - Google Patents

絶縁ゲート型電界効果トランジスタ素子の製造方法

Info

Publication number
JPS5896763A
JPS5896763A JP56194974A JP19497481A JPS5896763A JP S5896763 A JPS5896763 A JP S5896763A JP 56194974 A JP56194974 A JP 56194974A JP 19497481 A JP19497481 A JP 19497481A JP S5896763 A JPS5896763 A JP S5896763A
Authority
JP
Japan
Prior art keywords
source
drain
field effect
effect transistor
insulated gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56194974A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0221148B2 (enrdf_load_stackoverflow
Inventor
Juri Kato
樹理 加藤
Seiichi Iwamatsu
誠一 岩松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP56194974A priority Critical patent/JPS5896763A/ja
Publication of JPS5896763A publication Critical patent/JPS5896763A/ja
Publication of JPH0221148B2 publication Critical patent/JPH0221148B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP56194974A 1981-12-03 1981-12-03 絶縁ゲート型電界効果トランジスタ素子の製造方法 Granted JPS5896763A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56194974A JPS5896763A (ja) 1981-12-03 1981-12-03 絶縁ゲート型電界効果トランジスタ素子の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56194974A JPS5896763A (ja) 1981-12-03 1981-12-03 絶縁ゲート型電界効果トランジスタ素子の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP1033138A Division JPH02353A (ja) 1989-02-13 1989-02-13 Ｃｍｏｓ型半導体装置

Publications (2)

Publication Number Publication Date
JPS5896763A true JPS5896763A (ja) 1983-06-08
JPH0221148B2 JPH0221148B2 (enrdf_load_stackoverflow) 1990-05-11

Family

ID=16333434

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56194974A Granted JPS5896763A (ja) 1981-12-03 1981-12-03 絶縁ゲート型電界効果トランジスタ素子の製造方法

Country Status (1)

Country Link
JP (1) JPS5896763A (enrdf_load_stackoverflow)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS601862A (ja) * 1983-06-20 1985-01-08 Seiko Epson Corp 半導体装置の製造方法
JPS6077419A (ja) * 1983-10-04 1985-05-02 Seiko Epson Corp 半導体装置の製造方法
JPH0629316A (ja) * 1993-01-18 1994-02-04 Seiko Epson Corp 半導体装置の製造方法
US6218270B1 (en) 1998-03-04 2001-04-17 Nec Corporation Method of manufacturing semiconductor device having shallow junction
JP2002332073A (ja) * 2001-05-08 2002-11-22 Rootarii Kk 微小穿孔シート

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
APPL PHYS LETT INCOHERENT-LIGHT-FLASH ANNEALING OF PHOSPHORUS-IMPLANTED SILICON=1980 *
JAPANESE JOURNAL OF APPLIED PHYSICS RADIATION ANNEALING OF BORON-IMPLANTED SILICON WITH A HALOGEN LAMP=1980 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS601862A (ja) * 1983-06-20 1985-01-08 Seiko Epson Corp 半導体装置の製造方法
JPS6077419A (ja) * 1983-10-04 1985-05-02 Seiko Epson Corp 半導体装置の製造方法
JPH0629316A (ja) * 1993-01-18 1994-02-04 Seiko Epson Corp 半導体装置の製造方法
US6218270B1 (en) 1998-03-04 2001-04-17 Nec Corporation Method of manufacturing semiconductor device having shallow junction
JP2002332073A (ja) * 2001-05-08 2002-11-22 Rootarii Kk 微小穿孔シート

Also Published As

Publication number Publication date
JPH0221148B2 (enrdf_load_stackoverflow) 1990-05-11

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