JPS5895856A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5895856A JPS5895856A JP19402781A JP19402781A JPS5895856A JP S5895856 A JPS5895856 A JP S5895856A JP 19402781 A JP19402781 A JP 19402781A JP 19402781 A JP19402781 A JP 19402781A JP S5895856 A JPS5895856 A JP S5895856A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type region
- surge
- type
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000002955 isolation Methods 0.000 claims abstract description 9
- 230000002093 peripheral effect Effects 0.000 claims abstract 2
- 238000000926 separation method Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 6
- 230000015556 catabolic process Effects 0.000 abstract description 12
- 238000010586 diagram Methods 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はサージ破壊を防止する機能を有する半導体装置
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a function of preventing surge damage.
サージ破壊防止のために従来は第１図の等測的回路構成
に示す様に、入力あるいは出力端子０（ボンディングバ
ット２につながる配線に対して、正負それぞれのサージ
吸収用として、二つのダイオードＤ１およびＤ２が挿入
される構成を使用していた。これらのダイオードを半導
体装置内に設けるには、正サージ吸収用ダイオードＤ１
は、第２図の様に、Ｐ型基板１にエピタキシャル形成さ
れたｎ型領域２および分離領域３を有する半導体内に電
源と同電位のｎ型領域２とその中に形成されたＰ＋型領
域４とで構成され、一方、負サージ吸収用ダイオードＤ
２は、Ｄｌとは別の部分で第３図の様にｎ型領域２およ
びｎ 型領域６と接地電位の前記Ｐ型基板１及び分離領
域３とで構成されるのが一般的である。In order to prevent surge damage, conventionally, as shown in the isometric circuit configuration in Figure 1, two diodes D1 are connected to the input or output terminal 0 (wire connected to the bonding bat 2) for positive and negative surge absorption. In order to provide these diodes in a semiconductor device, a positive surge absorbing diode D1 is inserted.
As shown in FIG. 2, an n-type region 2 having the same potential as the power supply and a P+ type region formed therein are formed in a semiconductor having an n-type region 2 and an isolation region 3 epitaxially formed on a P-type substrate 1. 4, and on the other hand, a negative surge absorption diode D
Reference numeral 2 denotes a portion other than Dl, and as shown in FIG. 3, it is generally composed of an n-type region 2, an n-type region 6, the P-type substrate 1 at ground potential, and an isolation region 3.
しかし、この構造では、表面絶縁膜６の上に、Ｐ＋型領
域２あるいはｎ 型領域６の配線７のほかに、特に正サ
ージに対しては、前記ｎ 型領域２を電源鴫位と同−位
にするだめのアルミ配線８が必要となり、その分だけ配
線が複雑になる。また、０を入力端子として用いた場合
、入力端子ポンディングパッドに電源電圧＋ダイオード
の順方向重圧より高い゛成田をかけると、サージ破壊防
止用ダイオードを通して電源に電流が逃げるため、通常
の回路動作のために各端子に印加し得る電圧は［零ポル
トから（電源電圧）＋（ダイオードの順方向電圧）まで
」という制限ができてしまう。However, in this structure, in addition to the wiring 7 in the P+ type region 2 or the n-type region 6 on the surface insulating film 6, the n-type region 2 is placed at the same level as the power supply level, especially for positive surges. An extra aluminum wiring 8 is required for each position, and the wiring becomes complicated accordingly. In addition, when using 0 as the input terminal, if a voltage higher than the power supply voltage + forward pressure of the diode is applied to the input terminal bonding pad, the current will escape to the power supply through the surge protection diode, resulting in normal circuit operation. Therefore, the voltage that can be applied to each terminal is limited to ``from zero port to (power supply voltage) + (diode forward voltage)''.
本発明は、上述の問題点を解消し、電源からサージ破壊
防止用ダイオードへの配線を不用とし入力端子への印加
電圧の上限を、Ｐｎ接合の降服電圧にまで引き上げるこ
とを可能にしたものである。The present invention solves the above-mentioned problems, eliminates the need for wiring from the power supply to the surge protection diode, and makes it possible to raise the upper limit of the voltage applied to the input terminal to the breakdown voltage of the Pn junction. be.
以下に、本発明を実施例によって、詳述する。The present invention will be explained in detail below using examples.
第４図は本発明の半導体装置の等測的回路構成であり、
第５図は本発明によるサージ吸収ダイオード構造を有す
る半導体装置を示す断面概略図であるが、これは、分離
領域Ｐ型領域３で囲まれたｎ型領域２工ピタキシヤル層
の中にｎ 型領域５を・形成し、さらに、その周辺部に
前記分離領域３にまたかり、かつ、前記Ｐ型基板１や同
分鹸領域３よりも高濃度のＰ 型領域９を形成したもの
である。FIG. 4 shows an isometric circuit configuration of the semiconductor device of the present invention,
FIG. 5 is a schematic cross-sectional view showing a semiconductor device having a surge absorbing diode structure according to the present invention. Further, a P type region 9 is formed at the periphery thereof, spanning the separation region 3 and having a higher concentration than the P type substrate 1 and the same separation region 3.
この−造では、前記第４図に示されるように、負サージ
に対しては、従来と同様に１前記ｎ型領成されるダイオ
ードＤ２を使用してサージ破壊を防止し、正サージに対
しては、前記ｎ型領域２と高濃度のＰ＋型ｉ域９とで構
成されるダイオードＤ３のブレークダウンによってサー
ジ破壊を防止している。すなわち、前記ｎ 型領域６に
近接して、その周辺部に前記分離領域３にまたがる前記
Ｐ＋型領域９を設け、かつ、その不純物濃度が高いため
、この部分と前記ｎ 型領域６とで構成されるダイオー
ドの逆耐圧は低く、サージが来るとブレークダウンを起
こし、サージはＰ型基板１の接地側にバイパスされるも
のである。In this structure, as shown in FIG. 4, surge damage is prevented by using the n-type diode D2 in the same manner as in the past for negative surges, and for positive surges. In addition, surge damage is prevented by breakdown of the diode D3, which is composed of the n-type region 2 and the highly concentrated P+ type i-region 9. That is, the P+ type region 9 is provided in the vicinity of the n type region 6 and extends over the isolation region 3, and since the impurity concentration thereof is high, this region and the n type region 6 are formed. The reverse breakdown voltage of the diode is low, and breakdown occurs when a surge occurs, and the surge is bypassed to the ground side of the P-type substrate 1.
したがって、本装置では入力あるいは出力端子配線部０
に乗った正サージは前記ｎ＋型領領域からｎ型領域２の
エピタキシャル層に流れ、このｎ型領域２のエピタキシ
ャル層と前記高濃度Ｐ 型領域９のブレークダウン現象
によって前記Ｐ型分離領域３に流れる。さらにその電流
は、分離領域３を通してＰ型基板１の接地側に流れる。Therefore, in this device, the input or output terminal wiring section 0
The positive surge riding on the current flows from the n+ type region to the epitaxial layer of the n type region 2, and due to the breakdown phenomenon between the epitaxial layer of the n type region 2 and the high concentration P type region 9, it flows into the P type isolation region 3. flows. Further, the current flows through the isolation region 3 to the ground side of the P-type substrate 1.
そしてブレークダウン電圧は、Ｐ型領域９、ｎ型領域２
の濃度を制御することにより様々に設定することガでき
る。And the breakdown voltage is P type region 9, N type region 2
Various settings can be made by controlling the concentration of .
以上のように本発明の構造によると、電源からサージ破
壊防止用ダイオードへの配線が不用となり、また入力端
子へ印加し得る電圧が前記ｎ型領域エピタキシャル層２
と高濃度の前記Ｐ 型領域９の逆耐圧にまでになり、半
導体集積回路に大きく寄与するものである。なお、本発
明において導電型が実施例と逆の場合であってもよいこ
とは当然である。As described above, according to the structure of the present invention, there is no need for wiring from the power supply to the surge damage prevention diode, and the voltage that can be applied to the input terminal is applied to the n-type region epitaxial layer 2.
This increases the reverse breakdown voltage of the highly concentrated P-type region 9 and greatly contributes to semiconductor integrated circuits. Incidentally, in the present invention, it goes without saying that the conductivity type may be reversed to that in the embodiments.
第１図は従来例装メの等価的回路構成図、第２図、第３
図は従来例のサージ破壊防止用ダイオードの断面構造図
、第４図は本発明装置の等価的回路構成図、第６図は本
発明実施例装置の断面構造図である。Figure 1 is an equivalent circuit configuration diagram of a conventional example, Figures 2 and 3.
FIG. 4 is a cross-sectional structural diagram of a conventional surge damage prevention diode, FIG. 4 is an equivalent circuit diagram of a device according to the present invention, and FIG. 6 is a cross-sectional structural diagram of a device according to an embodiment of the present invention.
Claims (2)
反対導電型の第１導電体領域内に形成され、外部端子用
配線に接続された前記第１導電体領域と同導電型の第２
導電体領域と、前記第２導ｄ体領域の周辺部に、前記分
離領域に達しかつ前記基板より高濃度の基板と同導電型
の第３導電体領域を備えたことを特徴とする半導体装置
。(1) A first conductor region of the same conductivity type as the first conductor region, which is formed in a first conductor region of an opposite conductivity type surrounded by a substrate region of a predetermined conductivity type and a separation region, and connected to an external terminal wiring. 2
A semiconductor device comprising: a conductor region; and a third conductor region having the same conductivity type as the substrate and reaching the isolation region and having a higher concentration than the substrate, in a peripheral portion of the second conductor region. .
こと１ｆ特徴とする特許請求の範囲第１項に記載の半導
体装置。(2) The semiconductor device according to claim 1, characterized in that an input or output wiring is connected to the second semiconductor region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19402781A JPS5895856A (en) | 1981-12-02 | 1981-12-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19402781A JPS5895856A (en) | 1981-12-02 | 1981-12-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5895856A true JPS5895856A (en) | 1983-06-07 |
Family
ID=16317718
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19402781A Pending JPS5895856A (en) | 1981-12-02 | 1981-12-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5895856A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62137861A (en) * | 1985-12-12 | 1987-06-20 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPS648654A (en) * | 1987-06-30 | 1989-01-12 | Rohm Co Ltd | Semiconductor device |
| EP0807979A3 (en) * | 1996-05-15 | 1998-02-25 | SILICONIX Incorporated | Diode |
| JP2001148484A (en) * | 1999-11-22 | 2001-05-29 | Rohm Co Ltd | Anode common zener diode |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5248469A (en) * | 1975-10-15 | 1977-04-18 | Matsushita Electric Ind Co Ltd | Process for production of semiconductor device |
-
1981
- 1981-12-02 JP JP19402781A patent/JPS5895856A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5248469A (en) * | 1975-10-15 | 1977-04-18 | Matsushita Electric Ind Co Ltd | Process for production of semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62137861A (en) * | 1985-12-12 | 1987-06-20 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPS648654A (en) * | 1987-06-30 | 1989-01-12 | Rohm Co Ltd | Semiconductor device |
| EP0807979A3 (en) * | 1996-05-15 | 1998-02-25 | SILICONIX Incorporated | Diode |
| US5818084A (en) * | 1996-05-15 | 1998-10-06 | Siliconix Incorporated | Pseudo-Schottky diode |
| US6476442B1 (en) | 1996-05-15 | 2002-11-05 | Siliconix Incorporated | Pseudo-Schottky diode |
| JP2001148484A (en) * | 1999-11-22 | 2001-05-29 | Rohm Co Ltd | Anode common zener diode |
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