JPH0516194B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a surge absorbing semiconductor device that mainly utilizes the reverse nonlinear resistance characteristics of a PN junction.

In general, surge voltages are generated in communication lines and control lines of various electrical devices due to direct strikes or induction of natural lightning, or switching of loads, etc., and especially with the progress of high-density modularization of communication devices and other electronic devices. As a result, ICs that are extremely susceptible to surge voltages and overvoltages,
As LSI devices and other devices are being used extensively, it is becoming increasingly necessary to use surge absorbers to absorb surges before they enter electronic equipment.

Such surge absorbers can be roughly divided into discharge type ones and solid-state elements such as metal oxide varistors or silicon semiconductor varistors.The solid-state elements to which the present invention belongs have the function of absorbing surge voltage at high speed. The surge resistance is relatively small, and the larger the surge resistance, the larger the capacitance, which is a contradictory relationship. As capacitance increases, power loss increases, and this tendency is particularly noticeable in high-frequency transmission lines and high-speed digital signal transmission lines. It is becoming important to reduce capacity.

The present invention aims to reduce the equivalent capacitance of a semiconductor device for surge absorption, and the present invention provides a main PN junction and a main PN junction in a semiconductor device that utilizes the reverse nonlinear resistance characteristics of one or more main PN junctions. By forming a secondary PN junction for small capacitance reduction in the opposite direction and utilizing its forward characteristics, the capacitance for small capacitance reduction by the secondary PN junction is connected in series with the capacitance due to the main PN junction. It is an object of the present invention to provide a semiconductor device for surge absorption, which can thereby sufficiently reduce the capacitance of the entire semiconductor element.

Embodiments of the present invention will be described below with reference to the drawings.

An embodiment of the present invention will be explained with reference to FIGS. 1A, B, and C.

An embodiment of the present invention will be explained with reference to FIGS. 1A, B, and C. 1 is an n ^- conductivity type semiconductor substrate with a low impurity concentration, 2 is a p ⁺ high impurity concentration semiconductor layer with a high impurity concentration, and 3 is a semiconductor substrate with a high impurity concentration. The insulating film 4 formed on the main surface of this region is an important small region of the present invention formed using the opening of the insulating film 3. First, a p conductivity type impurity is diffused from one side of an n ^- conductivity type semiconductor substrate 1 having a low impurity concentration to form a p ⁺ high impurity concentration layer 2 to form a main PN junction J ₁ . These semiconductor layers 1, 2 and the main PN junction _J1 provide an avalanche breakdown function. Generally, to increase the surge withstand capacity, the junction area of the main PN junction _J1 is increased, but since the junction area and the capacitance due to the PN junction are almost proportional, if you try to increase the surge withstand capacity, the PN The capacitance due to the junction also increases. Therefore, in this embodiment, in order to reduce the capacitance C ₁ due to the main PN junction J ₁ , p is A conductive type impurity is diffused to form a small region 4 with a ^high p
A PN junction J ₂ is formed to provide a small capacitance C ₂ in series with the capacitance C ₁ .

_{According to} this structure _, as shown in FIG. small
This is equivalent to connecting a diode D ₂ with a PN junction J ₂ in series. Therefore, these main PN junctions J ₁
Capacitance C ₁ due to and capacitance C ₂ due to PN junction J ₂
are connected in series, and the combined capacitance is
In other words, the equivalent capacitance C of the entire semiconductor device
becomes C≒C ₁ C ₂ /C ₁ +C ₂ .

Here, if C ₂ ≪ C ₁ , the above capacitance C is C
≒ becomes ₂ .

Therefore, compared to the joint area of the main PN junction _J1 , the secondary PN
_Small area 4 is
If the equivalent capacitance C of the semiconductor device is formed,
is approximately equal to the capacitance C ₂ due to secondary PN junction J ₂ .

Here, PN junction J ₂ is a capacitance reduction PN junction used only to reduce capacitance, and since this PN junction J ₂ is used in a forward bias state, PN junction J ₂ The bonding area can be made sufficiently small without limiting the withstand capacity.

In the figure, 5 and 6 are electrodes, and 7 and 8 are terminals drawn out from these respective electrodes. In use, a negative voltage is applied to the terminal 7, and a positive voltage is applied to the terminal 8.

Next, in another embodiment shown in FIG. 2, the equivalent capacitance C of the entire semiconductor device is reduced, and
In order to make it easier for the surge current to flow uniformly through the semiconductor substrate 1, small regions 4a, 4b, 4 with high p ⁺ impurity concentration are formed.
A plurality of electrodes 6a, 6b, 6c, . . . formed in these small regions are all commonly connected. In this example, the small area 4
Since the respective capacitances C _a , C _b , C _c ... formed with the formation of a, 4b, 4c ... are connected in parallel with each other, the combined capacitance C ₂ is C ₂
≒C _a +C _b +C _c +... Therefore, small area 4
It is preferable to make a, 4b, 4c... sufficiently small.

In another embodiment shown in FIG. 3, the semiconductor substrate 1 has a very low n ^- type impurity concentration.
By using , the capacitance C ₂ due to the PN junction J ₂ formed by the substrate 1 and the small region 4
can be made even smaller.

Next, another embodiment of the present invention will be described with reference to FIGS. 4A and 4B. When p conductivity type impurities are diffused into the semiconductor substrate 1 to form a small region 4 with a high p ⁺ impurity concentration, the small region A second small region 4' having a p ⁺ high impurity concentration is formed separately from the p+ impurity concentration, and a third small region 9 having an n ⁺ high impurity concentration is formed as a small region 4' using a normal photolithography method. form within. Since the PN junction formed between the n ^- low impurity concentration semiconductor layer 1 and the second small region 4' is unnecessary, the conductive thin film 10 is formed so as to straddle this PN junction. and the second small region 4' are electrically short-circuited.
Then, by commonly connecting the electrode 11 formed in the third small region 9 and the electrode 6 formed in the small region 4, the avalanche regulator is down with the main PN junction _J1 as shown in FIG. In contrast to the functional diode D ₁ , the PN junctions J ₂ and J ₃ have a small junction area.
It is possible to obtain a semiconductor device having a structure equivalent to a structure in which diodes D ₂ and D ₃ each having diodes D 2 and D 3 are connected in series in antiparallel. By soldering the respective electrodes 5 of the two semiconductor elements back to back via the intermediate lead-out terminals 12, such a semiconductor device can be made into a bi-directional device with three lead-out terminals as shown in FIG. Suitable for obtaining surge absorption elements with avalanche breakdown function,
A bidirectional semiconductor device with only a small regulated capacitance can be obtained.

In the above embodiments, a unidirectional surge absorbing semiconductor device has been described. Next, an embodiment of a bidirectional semiconductor varistor will be explained with reference to FIGS ^. 6A and 6B. By diffusing p-type impurities from both sides to form semiconductor layers 2 and 2' with p-doped concentrations, the main PN junctions J ₁ ,
form J ₁ ′. A small region 4a with n ⁺ high impurity concentration and a small region 4b with n+ impurity concentration are formed in the semiconductor layer 2, and a small region 4' with n ⁺ high impurity concentration is formed in the semiconductor layer 2'.
a' and a small region 4'b with n impurity concentration are formed.
Furthermore, small regions 11 and 11' with high p ⁺ impurity concentration are formed in the small regions 4b and 4'b, respectively, and the electrode 11 formed in the small region 9 and the electrode 6 formed in the small region 4a are electrically connected. The electrode 11' formed in the small region 9' and the electrode 6' formed in the small region 4'a are electrically coupled. Further, similarly to the embodiment shown in FIG. 4, the conductive thin films 10, 10'
The semiconductor layer 2 and the small region 4b are electrically short-circuited, and the semiconductor layer 2' and the small region 4'b are electrically short-circuited. According to such a configuration, it is possible to obtain a bidirectional semiconductor varistor that can reduce the capacitance as shown in FIG. 2B even with a single semiconductor substrate.

As described above, according to the present invention, the reverse nonlinear resistance characteristic is mainly used to compensate for the capacitance of the semiconductor element itself having the main PN junction, that is, to reduce the capacitance of the entire semiconductor device. Since a PN junction with a small junction area that provides a small capacitance is formed, it is possible to easily manufacture a surge absorbing semiconductor device with a capacitance adjusted to a predetermined value, and it is also sufficiently small. Since a PN junction with a large junction area can be easily formed, the capacitance of the semiconductor device for surge series can be sufficiently reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining one embodiment of the present invention, in which A is a cross-sectional view, B is a top view of a semiconductor substrate,
C is an equivalent diagram, FIGS. 2 and 3 are cross-sectional views showing other embodiments of the present invention, and FIG. 4 is a diagram showing another embodiment of the present invention, in which A is a cross-sectional view. figure,
B is an equivalent diagram thereof, FIG. 5 is a diagram for explaining another embodiment of the present invention, FIG. 6 is a diagram for explaining another embodiment of the present invention, A is a cross-sectional diagram, B is its equivalent diagram. 1... Semiconductor substrate, 2, 2'... Semiconductor layer, 3,
3'...Insulating coating, 4,4'...Small area, 5,6...
...electrode, 7,8...output terminal, 9,9'...small area, 10,10'...conductive thin film, J ₁ , J ₂ , J ₃
...PN junction.

Claims (1)

[Claims] 1. A unidirectional surge in which one or more main PN junctions formed by a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type exhibit reverse nonlinear resistance characteristics. In the absorption semiconductor device, one or more small regions having an area sufficiently smaller than the semiconductor layer and having an opposite conductivity type are formed in the semiconductor layer of the first conductivity type, and the capacitance of the main PN junction is increased. A secondary PN junction for capacitance reduction having a sufficiently small capacitance compared to that of the main PN junction is provided in series with the main PN junction to reduce the capacitance of the entire semiconductor device, and a positive voltage is applied to the small region of the electrode. What is claimed is: 1. A unidirectional surge absorbing semiconductor device, characterized in that an electrode to which a negative voltage is applied to the semiconductor layer of the second conductivity type is formed. 2. A bidirectional surge absorbing semiconductor that utilizes the nonlinear directional characteristics of two or more main PN junctions formed in series by at least two semiconductor layers of a first conductivity type and a semiconductor layer of a second conductivity type. In the device, a plurality of small regions having an area sufficiently smaller than that of the first conductivity type semiconductor layer and having an opposite conductivity type are formed in the semiconductor layer of the first conductivity type to form a secondary PN junction for capacitance reduction between the main PN junction and the second conductivity type semiconductor layer.
The PN junction for capacitance reduction is formed in series with the junction, and at least one of these small regions is formed with another small region of a conductivity type opposite to that of this small region. The bidirectional device is provided in series with the PN junction, further electrically coupling the other small region and the small region where this small region is not formed, and forming electrodes on these small regions. Semiconductor device for absorbing electrical surges.