JPS6370459A - Surge absorbing semiconductor device - Google Patents

Abstract

PURPOSE:To decrease a voltage drop in a forward direction, by doping a second conductivity type impurities in a low impurity concentration region on one hand, and doping second conductivity type impurities in a low impurity concen tration region so as to reach a part within the free running path distance of carriers on the other hand. CONSTITUTION:A first P-N junction J1, which is formed by a first region 3 and an embedded region 2, is subject to avalanche breakdown when a voltage exceeding a preset voltage is applied across electrodes 6 and 7. The voltage between the electrodes 6 and 7 is kept at a value less than the preset voltage. A second P-N junction J2, which is formed by a second region 4 and a low impurity concentration layer 1, has a sufficiently small area in comparison with the first P-N junction J1. A low impurity concentration layer part 1', which is held between the second region 4 and the embedded region 2, is formed so that the thickness of the part 1' is less than the free running path distance of the carriers. Even if the resistivity of the low impurity concentration layer part 1' is large, the drop in the forward direction in the low impurity concentra tion layer part 1' at a region, where a large current flows, is not increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device for surge absorption that mainly utilizes the reverse nonlinear resistance characteristics of a PN junction.

[Conventional technology]

In general, in communication lines and other communication lines, pressure is generated due to surges due to direct strikes or guidance from natural lightning, or the switching of loads, especially in high-density modules such as communication equipment and other electronic equipment. With the advancement of technology, ICs, LSI devices, etc. that are extremely susceptible to surge voltages and overvoltages are being used more and more, so it is increasingly necessary to use surge absorbers to absorb surges before they can infiltrate single-device devices. Such surge absorbers can be roughly divided into discharge type ones and solid-state elements such as metal Efide varistors or silicon semiconductor varistors. Ability to absorb at high speed? However, the surge resistance is relatively small, and the larger the surge resistance, the larger the capacitance, which is a contradictory relationship. As the capacitance increases, the electric loss increases, and this tendency becomes remarkable in flat frequency transmission lines, flat speed digital signal transmission lines, etc. Stability of semiconductor devices without giving r! ! It has become necessary to reduce the capacitance.
There is a semiconductor device disclosed in Japanese Patent No. 140878. The main purpose of this is to reduce the equivalent capacitance of the semiconductor device, as shown in FIG. By forming a small PN junction J2yt in the small semiconductor substrate in the opposite direction to the main PN junction J1 and utilizing its forward characteristics, the capacitance can be reduced compared to the capacitance due to the main PN junction. A capacitance for reducing capacitance is provided in series by a PN junction, thereby sufficiently reducing the capacitance of the entire semiconductor element.

this? In the circuit diagram, as shown in Figure 6 (kun), the main P
This is equivalent to connecting in series a surge absorbing element D1 having an N junction J0 and a capacitance reducing element D2 having a capacitance reducing PN junction J2 in the opposite direction.

[Problem that the invention seeks to solve]

However, in such a conventional surge absorbing semiconductor device, since impurities must be doped from both main surfaces of the semiconductor substrate 1, the manufacturing process is complicated and the cost is high. In the conventional method, a semiconductor substrate 1 with a low impurity concentration is used in order to reduce the electric conductivity, and a region 2.4 with a high impurity concentration of a conductivity type different from that of the semiconductor substrate is formed in a predetermined region of the semiconductor substrate. Since it is difficult to make the semiconductor substrate even thinner than 300 to 400 μm due to mechanical strength and the characteristics of the semiconductor device, it is difficult to reduce the thickness of the semiconductor substrate by 300 to 400 μm. The thickness of the semiconductor substrate portion with high concentration must become large. It is desirable that the thickness W#'i be thinner than the free path distance of the carrier. In this way, the forward voltage drop of the capacitance reduction element connected in series with the surge absorption element that performs the surge absorption function increases. This goes against the purpose of suppressing surges, and not only does the clamp voltage rise and the power loss during surge absorption increases, but also heat generation increases, limiting the surge absorption capacity t. It also has the disadvantage of being stored away.

[Means and operations for solving the problem] In order to eliminate all the drawbacks of the conventional surge absorbing semiconductor device as described above, the present invention uses a first specialized I-type low impurity impurity that is once embedded in a small area. In addition, a high impurity concentration region of the same conductivity type is common, and a second 4',! L-type impurity? doping and doping a second type of impurity into the low impurity concentration region such that the other does not reach the high impurity concentration region but preferably reaches within the free path distance of carriers; This feature enables the formation of a surge absorbing element and a capacitance reduction element for reducing the capacitance in the same IL-conductor layer in the same manufacturing process, and the robustness of the capacitance reduction element. Directional pressure drop can be reduced.

[Implementation l/+] J An example of a semiconductor device for surge absorption related to a cine +jl will be described with reference to FIG. 1. 1 is a non-n' A semiconductor substrate having an N-type epitaxial layer with a low impurity concentration or a FiN-type conductivity type (hereinafter referred to as a low impurity, A degree layer) is formed by implanting phosphorus atoms etc. using ion implantation technology. Alternatively, as will be described later, an N+ type buried region 6 with a sufficiently high impurity concentration formed by a diffusion method, and a P type first region 6 forming a P+ N junction J1 with a Nu buried region 2 are formed. Region 4 is a P+C type second region formed in the same manner as the first region 2 so as to form a low impurity concentration 1-1 and a PN junction J2r in the vicinity without reaching the male penetration junction J22. 'AAs2 insulating film, 6.7 is 21.
This is a basket j formed to make ohmic contact with the 22Q forehead f6.4.

The first PN junction J1 formed by the first region 6 and the buried mast region 2 has a voltage higher than the set voltage.
Avalanche surrender occurs when T is applied between T! L
The voltage between poles 6 and 7 is maintained below the set voltage. The second P formed by the second region 4 and the low impurity concentration I
Is the junction area of N junction J2 sufficiently smaller than that of first PN junction J1? ! -Nurture. The low impurity concentration layer portion 1 sandwiched between the second region 4 and the buried region 2 is preferably formed to have a thickness within the free path distance of the carriers. This means that the low impurity concentration layer portion 1'
Even if the specific resistance of The low impurity concentration layer portion 1' constitutes an element for reducing each amount, and when these conditions are the same, the larger the resistivity of the low impurity concentration layer portion 1', the smaller the capacitance. However, on the other hand, the disadvantage is that the forward voltage drop increases. In this invention, the thickness of the low impurity concentration portion 1' is preferably set to be within the free path distance of carriers. 1, even in a large current range, the resistivity of the low impurity concentration j part 1' can be reduced, and the voltage drop in one direction will not be too large, so the junction surface of the PN junction J2 can be made sufficiently pebble. In addition, the n tolerance amount of the capacitance reducing element can be sufficiently reduced. In this embodiment of the reed octopus, the impurity concentration of the low impurity concentration No. 1 can be made sufficiently small, so the first and second value ranges 6.4 can be arranged relatively close together. An example of a manufacturing method using a diffusion method will be briefly described.

First, a layer (i/m
) k form. This shrimp layer is the low impurity layer 1 in Figure 1.
It is equivalent to 613 minutes p, or less impurity? It is called a leakage layer 1a. Next, as shown in Figure 2 (A),
Insulating film 10 on PJ plugging layer 1a? After the window is formed, the shape is exhausted and there are impurities? Diffusion is performed to form an N type region 2ak having a sufficiently high impurity concentration. Next, after removing the insulating film 10, a low impurity concentration +
*Grow 1b ((8) in the same figure).

At this time, impurities are diffused from the N0 type region 2a into the low impurity concentration layer 1b, and the diffusion is performed almost symmetrically with respect to the growth surface 11, so that the region 2b? ! - form. The region formed by these regions 2a and 2b in the shape Iy, -j corresponds to the buried region 2 in FIG. 1, and the region formed by the regions 1a and 1b corresponds to the low impurity concentration layer 1 in FIG. Next, as shown in Figure C), a window is applied to the insulating film 5' formed on the top surface of the low impurity concentration layer 1b, and the accessor impurity is diffused to a predetermined depth through the window. Further, as shown in FIG. 5D, the acceptor seed material is diffused through a window provided at a predetermined position in the insulating film 5 to form a P-type 20th region 4.

At this time, impurity diffusion in the r-type region 6' also progresses, and the first region 6 is formed.

In this way, each region is formed, but there is a width between the second region 4 and the embedded region 2, preferably a thickness equal to or less than the free travel distance of the gear. 1' is always present.

〔Effect of the invention〕

As described above, according to the invention, even if the resistivity of the low impurity concentration layer is sufficiently increased in the structure of the capacitance reducing element for reducing the static 14'8 amount, the 7
”: The voltage drop in the n-direction is prevented from increasing, so the static capacity i of the semiconductor device for surge absorption can be made sufficiently small, and it goes without saying that the manufacturing process can be performed evenly from one side. Since the specific resistance of the impurity-concentrated region can be made sufficiently large, the isolation region can be formed, and the surge absorbing element part and the capacitance reducing element part can be formed close to the gold, allowing the semiconductor device to be made smaller.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the surge absorbing semiconductor device according to the invention, and FIGS. , (B, l are diagrams showing general surge absorption semi-45 body dimensions. 1.1'...Low impurity 1 degree jj 2...Blow-up area 6.4...21, No. 2 A area 5... Insulating film 6.7... Electrode patent applicant Origin Electric Co., Ltd. Hitsuji 3 Figure

Claims (1)

[Claims] A first conductivity type high impurity concentration region embedded in a first conductivity type low impurity concentration layer and the first conductivity type high impurity concentration region such that a PN junction is formed with the first conductivity type high impurity concentration region. A portion of the low impurity concentration layer of the first conductivity type is between the first region of the second conductivity type formed in the low impurity concentration layer and the high impurity concentration region of the first conductivity type. 1. A surge absorbing semiconductor device comprising: a second region of a second conductivity type formed within the low impurity concentration layer of the first conductivity type.