JPS6373673A - Semiconductor device for absorbing surge - Google Patents

Abstract

PURPOSE:To reduce a voltage drop of a surge absorber itself and to simultaneously reduce an electrostatic capacity of a capacity reducing element by providing a first conductivity type high impurity concentration region, a second conductivity type first region formed on the first conductivity type low impurity concentration region and a second conductivity type second region. CONSTITUTION:A low impurity concentration region is an N<-> type epitaxial layer having a very low impurity concentration formed on a single crystal semiconductor substrate or an N<-> type semiconductor substrate, buried regions 2, 2' are sufficiently high impurity concentration N<+> type buried regions, a first region 3 is a P<+> type region for commonly forming an anode region of one surge absorber SA1 and an anode region of a capacity reducing element D1, and a second region 3' is a P<+> type region for applying a common anode region of other surge absorber AB2 and a capacity reducing element D2. Most of the first region 3 form the region 2 and a main P-N junction J1, and a P-N junction is formed partly with a very thin low impurity concentration region 1a to the other buried region 2'.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device for surge absorption that mainly utilizes the reverse nonlinear characteristics of a PN junction.

[Conventional technology]

In general, surge voltages are generated in communication lines and control lines for various electrical equipment due to direct lightning strikes, induction, or switching of loads.In particular, surge voltages occur in communication lines and control lines for various electrical equipment, and surge voltages occur due to the development of high-density modularization of communication equipment and other electronic equipment. Accordingly, ICs, LSI elements, and the like that are extremely susceptible to surge voltages and overvoltages are often used, so it is increasingly necessary to use surge absorbers to absorb surges before they enter electronic devices.

Such surge absorbers can be broadly classified into group 1! type and
Solid-state devices are divided into metal oxide varistors and silicon semiconductor varistors, and the solid-state devices to which the present invention belongs have the function of absorbing surge voltage at high speed, but their surge withstand capacity is relatively small, and if the surge withstand capacity is increased, There is a contradictory relationship in which the amount of n tolerance increases. As capacitance increases, power loss increases, and this tendency is particularly noticeable in high-frequency transmission lines and high-speed digital signal transmission lines. The cost of molding is due to the reduction in capacity.

like this! #Unexamined Japanese Patent Publication No. 111 with reduced tolerance amount
A semiconductor device disclosed in B60-140878 is disclosed. The main purpose of this is to reduce the equivalent capacitance of a semiconductor device, and to utilize the reverse nonlinear characteristics of one or more main PN junctions. By forming a capacitance-reducing PN junction and utilizing its forward characteristics, the capacitance-reducing PN junction provides a small capacitance-reducing capacitance t' in series with the capacitance of the main PN junction. This provides a semiconductor device that can sufficiently reduce the capacitance of the entire semiconductor element. A conventional example in which an element and a capacitance reducing element are formed will be described.

Regarding the conventional surge absorption element, by first diffusing p-type impurities from both sides of the semiconductor substrate 10 having a low n-impurity concentration to form semiconductors 146 & 6b having a p-impurity concentration,
A small head region 7a of n+ high impurity concentration and a small region 7b of n impurity concentration are formed in the semiconductor layer 6a forming the main PN junction J1*J1', and the semiconductor layer 6bKn+small region 71 of high impurity concentration 71a and n Small regions 7/b and t with impurity concentration are formed. Furthermore, a small region 1'' with high p+ impurity is formed in the capitular region 7b, 7'b, and the electrode 8 formed in the capitular region 9 and the electrode formed in the capitular region 7a are connected to each other. An electrode 8' formed in the small area 9' and an electrode 10'' formed in the small head area 7'a are electrically coupled to each other. 'So, semiconductor layer 6
& and the small head region 7b, and the semiconductor layer 6b and the small head region 7'b Fi are electrically short-circuited. According to such a configuration, it is possible to obtain a bidirectional surge absorbing semiconductor device 1!12 as shown in the same figure (B) with a single semiconductor substrate. r: In comparison, the main PN junctions J1 + Jl' are surge absorbing elements D□ and D, respectively.
1', and the PN junctions J2 e 'z' provide the PN junctions of the capacitance reducing elements D3sD3', respectively.

Also, the capacitance reducing element is different from the structure of D3', or is a PNN junction, l J3' is the capacitance reducing element D2
+ D2' PN junctions are provided respectively.

Therefore, according to such a bidirectional surge absorbing semiconductor device, the surge absorbing elements DI connected in series in opposite directions
+ Since the pair of capacitance reducing elements D2, D2' and D2' are connected in series in opposite directions and connected in parallel with respect to DI', the capacitance of the entire semiconductor device can be reduced. At the same time, it is possible to suppress the splash VT pressure to a minimum when absorbing a surge current.

[Problem that the invention seeks to solve]

However, in such a conventional surge absorbing semiconductor device, since impurities must be doped from both main surfaces of the semiconductor substrate 10, the manufacturing process becomes complicated and the cost inevitably increases. , terminals 12 and 12'
Since there are many PN junctions between them, there is a drawback that the voltage drop is large. In addition, in order to reduce the capacitance, it is preferable to use a semiconductor substrate 1 with a small concentration of tungsten. It is difficult to make the semiconductor substrate 10 thin, and the structure is such that the impurity concentration regions 7aw7'ae7b+7'bh are shallowly formed (to reduce the capacitance) in predetermined regions on both sides of the semiconductor substrate 10, so these regions 7a and 71a, 7b and 7 There was a drawback that the voltage drop between 'b' and 'b' had to become even larger.

[Means to resolve the problem]

In order to eliminate the drawbacks of the conventional surge absorbing semiconductor device as described above, the present invention includes a first conductivity type high impurity concentration region embedded in a first conductivity type low impurity concentration region; a tenth region of a second conductivity type formed in a low impurity concentration region of a conductivity type 1 to form a PN junction with a high impurity concentration region of a conductivity type 1; A first conductivity type low impurity concentration region formed within the first conductivity type low impurity concentration region such that a portion of the first conductivity type low impurity concentration region exists between the conductivity type high n-doped concentration region. 2nd conductivity type
It has an area of

[For production]

Since the present invention has such characteristics, it is possible to form a surge absorbing element by combining high impurity concentration regions of different conductivity types even though it is used on a semiconductor substrate with a low impurity concentration. Furthermore, since the thickness of the low impurity concentration layer forming a part of the capacitance reducing element is very thin, preferably within the carrier free path distance, the total voltage drop of the surge absorbing element itself can be reduced. Even in a large current region, the capacitance ilt can be sufficiently reduced without increasing the voltage drop of the capacitance reducing element.

[Embodiment 1] Fig. 1, Fig. 2 (A) and CB) showing the cross sections along the lines X-X' and Y-Y' in Fig. 1, and the semiconductor device shown in Fig. 1 An example of the semiconductor device To explain, 1 is an N-type epitaxial no or N-type semiconductor substrate (hereinafter referred to as a low impurity concentration filling region) with a very low impurity concentration formed on a single crystal semiconductor substrate (not shown); 2. 2' is an N+ type buried region with a sufficiently high impurity concentration formed by implanting donor impurities using ion implantation technology or by a diffusion method; 3 is an anode of one surge absorbing element SA1 shown in FIG. 6; Area and capacity reduction element D
a P+ type region that commonly forms an anode region of 1;
3' is a common 7-node region between the other surge absorbing element SA and the capacitance reducing element D2 shown in FIG. 6, and is a P+ type region. As can be seen from FIG. 2(B), most of the region 6 forms a main PN contact &J,t- with the buried region 2, and a part of it forms a very thin low impurity contact with the other buried region 2'. A PNN association is formed with the concentration layer region 1a. It is preferable that the thickness of this low impurity concentration region 1a be less than or equal to the free path distance of the carriers.
-on) The voltage drop in the large current region does not increase. To explain here, it is known that in a P''N-N+ diode, as the resistivity in the N- type region increases, the capacitance in the region decreases. Most of 6' is buried area 2' and main PN.
A junction r1'w is formed, and a part thereof forms a PN junction with the very thin low impurity concentration region 1/ between the other buried region 2. Here the main PN junction J1 e
J1' is the surge absorbing element 5A11 sA shown in FIG.
, each PN junction is fully formed, and each PN junction Jz
*J2' is the capacitance reducing element D1. It forms a PN junction of D2.

Note that 4.4' are t-poles that form ohmic contact with the P+ type regions 6 and 6', respectively, and in FIG.
Conductor p connecting the anodes of elements SA1 and Dl
1. Element SA and D2.

- Provide a conductor 2□ which is connected to each other for km. The numeral 5 is an insulating film.

A bidirectional surge absorbing semiconductor device with such a structure
According to K., the low impurity concentration region in the surge absorbing element can be made sufficiently thinner than in conventional devices, so the capacitance can be sufficiently reduced, and the forward voltage drop t can also be reduced, and the PN junction Since the required number can be reduced to 1/2, this further reduces the forward voltage drop.Next, another embodiment of the present invention will be explained with reference to FIG. 4 LA) and (B,). . The same figure (B) is the same figure (A) showing the top surface.
A cross section taken along x-x' is shown. In the same figure, the same symbols as those shown in FIGS. 1 and 2 (AJ, (B)) are indicated by the same members.

The P+ type first and second regions 6,6' have a 5-shape and are arranged to face each other in opposite directions, so that miniaturization is possible. Most of the regions 6, 3' form the main PN junction J1. J.
A small portion of the regions 6, 6' extends above the buried regions 2', 2, respectively, and is arranged so as to face the buried regions 2', 2 through a thin low impurity concentration region. It will be done.

Next, referring to FIG. 5, another embodiment of the present invention will be fully explained.
(A,) is a plan view, (B) and <C) are respectively (A)
It is a figure which shows the cross section in XX' and YYK of.

Also in the figure, FIG. 1 and FIG. 2 (A).

Symbols that are the same as those shown in CB) indicate the same members.

In this embodiment, in addition to the P+ type high impurity concentration regions 3.6', r type regions 3X and 3'X are formed in the low impurity concentration region 1 to be shallower than in the previous embodiment. Accordingly, the portions 2.X and 2'X of the embedded region 2.2' corresponding to the regions 5
It protrudes toward the 3'X direction, and the area 3'X, 3
A part of the very thin low impurity concentration region 1 exists between the regions 2'X and 2X corresponding to 'X'. P+ type regions 3 and 3X, and 3' and 3'X are connected by poles 4.4', respectively. According to this embodiment, the P+ type region 3X forming the anode region of each capacitance reducing element,
In addition to the fact that 3'X is shallow, the total junction area can be made even smaller than in the embodiment described above, so that the capacitance can be made even smaller.

In the embodiment, the surge absorbing element SA1 or SA
, the capacitance ttC, the capacitance reducing element D2 or I/iD1
Let the capacitance kc be , and the capacitance ire of the elements SAl and D2, or SA2 and Dl, then the capacitance C1
and C2 are in series, so C=C,@C2/(C, 102). Here, if C□〉C2, then Cki02 is obtained. Therefore, the capacitance of the entire semiconductor device for surge absorption is sufficient compared to the capacitance of the capacitance reduction element or the capacitance of the surge absorption element. It can be seen that if the value is smaller than , then it becomes equal to the amount of wLW of the capacitance reducing element. Therefore, according to the surge absorbing semiconductor device according to the present invention, it is not necessary to particularly design the surge absorbing element itself to reduce its capacitance, so that desired surge absorbing characteristics can be easily obtained. , it is also possible to have a structure in which the forward voltage drop of the surge absorbing element is small.

Note that when the surge absorbing element performs the surge absorbing function, the capacitance reducing element is always passed through four in the forward direction, so
Compared to the surge absorbing element, the effective surface C1 through which current flows can be made much smaller. This is one of the major reasons why the capacitance reduction element has a much smaller capacitance than the surge absorption element.

In addition, the capacitance reducing element must have a reverse withstand voltage greater than the avalanche breakdown voltage of the surge absorbing element.
P+ type region 6X or 3'X of the capacitance reducing element,! :N
Even if the thickness of the low impurity concentration region between the + type buried regions 2 or 2' is made equal to or less than the carrier free path distance, a voltage higher than the normally required voltage, for example 200 to 250
A reverse withstand voltage of about V can be easily obtained.

According to the structure of this semiconductor device for surge absorption in bamboo, LS
Since it is easy to incorporate it into the semiconductor chip of I, it is suitable for use as a stage protector for each conductor with all the functional circuits incorporated therein.

Furthermore, it is of course possible to form an arbitrary number of the surge absorbing structures according to the above embodiments on a single semiconductor chip if necessary.

〔Effect of the invention〕

As described above, according to the present invention, a capacitance reducing element with very low capacitance can be provided in series with a surge absorbing element within the same semiconductor substrate without adversely affecting the surge absorbing element. Therefore, it is possible to provide a surge absorbing semiconductor device with an extremely small capacitance, and since the voltage drop can be minimized, power loss can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a perspective view of an embodiment of a semiconductor device for surge absorption according to the present invention, and FIG. 2 is a perspective view of a semiconductor device for surge absorption according to the present invention. 26 is a diagram showing a cross section of this surge absorbing semiconductor device, and FIG.
Figures 4 (A), (, and B) are plan and cross-sectional views of another embodiment of the present invention, and Figure 5 is a diagram showing another embodiment of the present invention. (A) is a diagram showing a plane, (B)
, <C) is a diagram showing a cross section along xx' and Y-Y' in (A), and FIGS. 6(A) and 6(CB) are diagrams showing a conventional example. 1...Low impurity concentration region 2.2'...Buried region 6.6'...First and second regions 4.4'...Electrode patent applicant Origin Electric Co., Ltd. No. Z 3 Figure 2' (A) CB) Teigoguchi No. S

Claims (1)

[Claims] first and second high impurity concentration regions of a first conductivity type embedded separately in the low impurity concentration region of the first conductivity type;
A PN junction is formed with a part of the first high impurity concentration region, and the low impurity concentration region faces a part of the second high impurity concentration region through a certain part of the low impurity concentration region. The first region of the second conductivity type formed in PN and a portion of the second high impurity concentration region are PN.
A second conductive layer of a second conductivity type formed in the low impurity concentration region faces a portion of the first high impurity concentration region through another portion of the low impurity concentration region to form a junction. A semiconductor device for surge absorption, characterized by comprising a region.