JPH0580834B2 - - Google Patents
Info
- Publication number
- JPH0580834B2 JPH0580834B2 JP57217243A JP21724382A JPH0580834B2 JP H0580834 B2 JPH0580834 B2 JP H0580834B2 JP 57217243 A JP57217243 A JP 57217243A JP 21724382 A JP21724382 A JP 21724382A JP H0580834 B2 JPH0580834 B2 JP H0580834B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- bonding pad
- semiconductor substrate
- pad electrode
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 39
- 238000002955 isolation Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 15
- 238000009792 diffusion process Methods 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000010521 absorption reaction Methods 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 description 10
- 238000000926 separation method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は酸化膜分離法を用いて作られる半導体
装置に関し、特にマイナスサージによつて半導体
素子が破壊されることがないようにサージ吸収用
の保護ダイオードが配置された半導体装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device manufactured using an oxide film separation method, and in particular to protection for surge absorption to prevent semiconductor elements from being destroyed by negative surges. The present invention relates to a semiconductor device in which a diode is arranged.
従来例の構成とその問題点
半導体装置がサージによつて破壊されることを
防止するには、半導体装置に具備された外付端子
と接地間および電源間にサージ吸収用の保護ダイ
オードを配置することがよく用いられる。これら
の保護ダイオードは実質的に半導体装置の中に作
り込まれることが多い。とりわけ、マイナスサー
ジに対する保護ダイオードは、Ｐ型半導体基板が
用いられる半導体装置であるならば、保護ダイオ
ードのアノード領域を前記半導体基板が有するＰ
型領域をもつて共用できる。即ち、マイナスサー
ジ対策用の保護ダイオードの形成は、カソード領
域を設けることでよいことになる。Conventional configuration and its problems To prevent semiconductor devices from being destroyed by surges, surge absorbing protection diodes are placed between the external terminals of the semiconductor device and the ground and power supply. is often used. These protection diodes are often built substantially into the semiconductor device. In particular, if the protection diode against negative surge is a semiconductor device using a P-type semiconductor substrate, the protection diode may be a P-type semiconductor substrate having an anode region of the protection diode.
It has a type area and can be shared. In other words, a protective diode for negative surge protection can be formed by providing a cathode region.
第１図は、半導体デバイスがPN接合によつて
分離される従来の半導体装置であつて、ボンデイ
ングパツド領域内に作り込まれた保護ダイオード
の断面構成図を示す。図中１はＰ型の半導体基
板、２はＮ型エピタキシヤル層、３はP+型分離
拡散層、４はN+型拡散層、５は熱酸化膜、そし
て６はボンデイングパツド電極である。 FIG. 1 is a conventional semiconductor device in which semiconductor devices are separated by a PN junction, and shows a cross-sectional configuration diagram of a protection diode built into a bonding pad region. In the figure, 1 is a P-type semiconductor substrate, 2 is an N-type epitaxial layer, 3 is a P + type isolation diffusion layer, 4 is an N + type diffusion layer, 5 is a thermal oxide film, and 6 is a bonding pad electrode. .
第１図においては、熱酸化膜５の厚さは0.8μ〜
1.5μ程度であるので、この上にボンデイングパツ
ド電極６を被着させ、さらにこの上にワイヤボン
デイングを行つても、機械的圧力に対して強く、
クラツクが生じることはない。即ち、PN接合で
分離される半導体装置であるならば、ボンデイン
グパツド領域内に前記保護ダイオードを形成する
ことは何等支障のないことである。 In FIG. 1, the thickness of the thermal oxide film 5 is 0.8μ~
Since the thickness is about 1.5μ, even if the bonding pad electrode 6 is placed on top of this and wire bonding is performed on top of this, it will still be strong against mechanical pressure.
No cracks will occur. That is, if the semiconductor device is separated by a PN junction, there is no problem in forming the protection diode in the bonding pad region.
一方においては、近年、高速、高集積のIC化
が望まれ、その１つとして、従来のPN接合分離
法に替る酸化膜分離を用いる方法が導入されてき
ている。 On the other hand, in recent years, there has been a desire for high-speed, highly integrated ICs, and one method that uses oxide film separation to replace the conventional PN junction separation method has been introduced.
第２図は、従来の酸化膜分離法によつて形成さ
れたボンデイングパツド領域内にマイナスサージ
吸収用の保護ダイオードを配置させた断面構造図
である。第１図と同番号を付した個所は同じ作用
や機能を有する。図中７は酸化膜および窒化膜
（以下保護膜と記す）、８は分離酸化膜である。こ
こで、保護膜７の厚さは、第１図の熱酸化膜５の
ように厚くできない。即ち、酸化膜分離法の採用
は、前記のように高速、高集積度の具現化のため
には必然的にシヤロー拡散を形成しなければなら
ず、その手段としてイオン打込み法を用いること
に依拠する。本発明者の実験においては、保護膜
７の厚さを500Å〜4000Åに設定した。 FIG. 2 is a cross-sectional structural diagram in which a negative surge absorbing protection diode is disposed within a bonding pad region formed by a conventional oxide film separation method. Components with the same numbers as in FIG. 1 have the same functions and functions. In the figure, 7 is an oxide film and a nitride film (hereinafter referred to as a protective film), and 8 is an isolation oxide film. Here, the thickness of the protective film 7 cannot be as thick as the thermal oxide film 5 shown in FIG. In other words, the adoption of the oxide film separation method is based on the use of ion implantation as a method for achieving shallow diffusion, which is necessary in order to achieve high speed and high integration as described above. do. In the inventor's experiments, the thickness of the protective film 7 was set to 500 Å to 4000 Å.
上記のような薄い保護膜７の上にボンデイング
パツド電極６を被着して、この上にワイヤボンデ
イングを行うと、機械的圧力によつて、保護膜７
にクラツクが生じ、半導体装置の信頼性が著しく
低下する不都合が存在する。 When the bonding pad electrode 6 is deposited on the thin protective film 7 as described above and wire bonding is performed thereon, the protective film 7 is bonded by mechanical pressure.
There is an inconvenience that cracks occur in the semiconductor device and the reliability of the semiconductor device is significantly reduced.
発明の目的
そこで本発明は上記の欠点を除去するためにな
されたものであつて、ボンデイングパツド電極下
に分離酸化膜を形成して、ワイヤボンデイングの
際に受ける機械的圧力によつて、クラツクが生じ
ないようにした半導体装置を提供する目的を有す
る。Purpose of the Invention The present invention has been made to eliminate the above-mentioned drawbacks, and it is possible to prevent cracks by forming an isolation oxide film under the bonding pad electrode and by applying mechanical pressure during wire bonding. It is an object of the present invention to provide a semiconductor device in which this phenomenon does not occur.
発明の構成
本発明は、一導電型の半導体基板上に同半導体
基板とは逆導電型のエピタキシヤル層が形成さ
れ、選択酸化によつて前記エピタキシヤル層を貫
通する分離酸化膜によつて半導体素子が分離され
る半導体装置において、前記半導体装置のボンデ
イングパツド電極の真下部に前記ボンデイングパ
ツド電極の面積と近似的に等しい面積で、前記分
離酸化膜を介して前記半導体基板とは逆導電型の
埋込層が前記半導体基板上に形成されるととも
に、前記ボンデイングパツド電極下の前記分離酸
化膜の存在しない一部分に前記埋込層に接続され
る前記埋込層と同一導電型の拡散層が形成され、
前記半導体基板と前記埋込層との接合によつてサ
ージ吸収用の保護ダイオードが形成されたもので
ある。これにより、前記半導体基板と前記埋込層
との接合によつて形成された保護ダイオードが、
半導体素子に加えられるサージを吸収し、さらに
ボンデイングパツド電極下の厚い分離酸化膜は、
ワイヤボンデイング時に受ける機械的な圧力に対
して強固な半導体装置が提供できるものである。Structure of the Invention The present invention provides an epitaxial layer having a conductivity type opposite to that of the semiconductor substrate formed on a semiconductor substrate of one conductivity type, and an isolation oxide film penetrating the epitaxial layer by selective oxidation. In a semiconductor device in which elements are separated, a bonding pad electrode of the semiconductor device has an area approximately equal to the area of the bonding pad electrode directly below the bonding pad electrode, and a conductivity opposite to that of the semiconductor substrate is provided through the isolation oxide film. A buried layer of the mold type is formed on the semiconductor substrate, and a diffusion layer of the same conductivity type as the buried layer is connected to the buried layer in a portion of the isolation oxide film under the bonding pad electrode. layers are formed,
A protection diode for surge absorption is formed by the junction between the semiconductor substrate and the buried layer. As a result, a protection diode formed by bonding the semiconductor substrate and the buried layer,
The thick isolation oxide film under the bonding pad electrode absorbs the surge applied to the semiconductor element, and
It is possible to provide a semiconductor device that is strong against mechanical pressure applied during wire bonding.
実施例の説明
第３図は本発明の一実施例を示す半導体装置で
ある。第２図の従来例とは、N+型の埋込層９が
形成されたことと、この埋込層９のコンタクト部
のN+型拡散層４上を除いて、ボンデイング電極
６の真下は分離酸化膜８を形成したことで相違す
る。この分離酸化膜８は、窒化膜をマスクとして
選択酸化法による高圧酸化等で1μ〜2μの厚さに
形成されている。したがつて、この上にボンデイ
ングパツド電極６を被着して、この電極上にワイ
ヤボンデイングを行つても、機械的圧力によつて
クラツクが生じることはなく、極めて好都合であ
る。ところで、ボンデイングパツド電極６下に分
離酸化膜８を形成する場合には、既存のエピタキ
シヤル層をエツチングし、そののち分離酸化膜を
形成するので、このときにエピタキシヤル層が存
在しなくなるために、保護ダイオードの形成が困
難になるが、本発明によるならばこの問題点に対
しては、N+型埋込層９をエピタキシヤル層の成
長前に形成することで解決できる。DESCRIPTION OF EMBODIMENTS FIG. 3 shows a semiconductor device showing an embodiment of the present invention. The conventional example shown in FIG. 2 is that an N + type buried layer 9 is formed, and except for the area on the N + type diffusion layer 4 at the contact portion of this buried layer 9, the area directly under the bonding electrode 6 is The difference is that an isolation oxide film 8 is formed. This isolation oxide film 8 is formed to a thickness of 1 μm to 2 μm by high-pressure oxidation using a selective oxidation method using the nitride film as a mask. Therefore, even if the bonding pad electrode 6 is placed thereon and wire bonding is performed on this electrode, no cracks will occur due to mechanical pressure, which is extremely convenient. By the way, when forming the isolation oxide film 8 under the bonding pad electrode 6, the existing epitaxial layer is etched and then the isolation oxide film is formed, so at this time the epitaxial layer no longer exists. However, according to the present invention, this problem can be solved by forming the N + type buried layer 9 before the growth of the epitaxial layer.
発明の効果
以上のように本発明は、酸化膜分離法によつて
作られる半導体装置において、ボンデイングパツ
ド領域下にマイナスサージ対策用の保護ダイオー
ドを形成することによつて、集積度を向上せし
め、さらに保護ダイオードのカソード領域に埋込
層を形成することにより、ボンデイングパツド電
極下の酸化膜を厚くすることが可能となり、ワイ
ヤボンデイング時の機械的圧力に対しても強固な
半導体装置が提供できる。Effects of the Invention As described above, the present invention improves the degree of integration in a semiconductor device manufactured by the oxide film separation method by forming a protective diode for negative surge protection under the bonding pad region. Furthermore, by forming a buried layer in the cathode region of the protection diode, it is possible to thicken the oxide film under the bonding pad electrode, providing a semiconductor device that is strong against mechanical pressure during wire bonding. can.
第１図は従来のPN接合分離を用いて作られた
マイナスサージ対策用の保護ダイオードを示す断
面構造図、第２図は従来の酸化膜分離を用いて作
られたマイナスサージ対策用の保護ダイオードを
示す断面構造図、第３図は本発明の一実施例にか
かる酸化膜分離による保護ダイオードの構造断面
図である。
１……半導体基板、２……エピタキシヤル層、
３……P+型分離拡散層、４……N+型拡散層、５
……熱酸化膜、６……ボンデイングパツド電極、
７……保護膜、８……分離酸化膜、９……N+型
埋込層。
Figure 1 is a cross-sectional structure diagram showing a protective diode for negative surge countermeasures made using conventional PN junction isolation, and Figure 2 is a protective diode for negative surge countermeasures made using conventional oxide film isolation. FIG. 3 is a structural cross-sectional view of a protection diode using oxide film separation according to an embodiment of the present invention. 1... Semiconductor substrate, 2... Epitaxial layer,
3...P + type separation diffusion layer, 4...N + type diffusion layer, 5
...Thermal oxide film, 6...Bonding pad electrode,
7... Protective film, 8... Isolation oxide film, 9... N + type buried layer.
Claims (1)
逆導電型のエピタキシヤル層が形成され、選択酸
化によつて前記エピタキシヤル層を貫通する分離
酸化膜によつて半導体素子が分離される半導体装
置において、前記半導体装置のボンデイングパツ
ド電極の真下部に前記ボンデイングパツド電極の
面積と近似的に等しい面積で、前記分離酸化膜を
介して前記半導体基板とは逆導電型の埋込層が前
記半導体基板上に形成されるとともに、前記ボン
デイングパツド電極下の電極分離酸化膜の存在し
ない一部分に前記埋込層に接続される前記埋込層
と同一導電型の拡散層が形成され、前記半導体基
板と前記埋込層との接合によつてサージ吸収用の
保護ダイオードが形成されていることを特徴とす
る半導体装置。1 A semiconductor in which an epitaxial layer of a conductivity type opposite to that of the semiconductor substrate is formed on a semiconductor substrate of one conductivity type, and semiconductor elements are separated by an isolation oxide film that penetrates the epitaxial layer by selective oxidation. In the device, a buried layer having an area approximately equal to the area of the bonding pad electrode and having a conductivity type opposite to that of the semiconductor substrate is provided directly below the bonding pad electrode of the semiconductor device through the isolation oxide film. A diffusion layer having the same conductivity type as the buried layer is formed on the semiconductor substrate and is connected to the buried layer in a portion of the bonding pad electrode where the electrode isolation oxide film does not exist. A semiconductor device characterized in that a protection diode for surge absorption is formed by bonding a semiconductor substrate and the buried layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57217243A JPS59106162A (en) | 1982-12-10 | 1982-12-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57217243A JPS59106162A (en) | 1982-12-10 | 1982-12-10 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59106162A JPS59106162A (en) | 1984-06-19 |
| JPH0580834B2 true JPH0580834B2 (en) | 1993-11-10 |
Family
ID=16701091
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57217243A Granted JPS59106162A (en) | 1982-12-10 | 1982-12-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59106162A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07232552A (en) * | 1994-02-23 | 1995-09-05 | Toyonaga Takemori | Two stage type vehicle sunvisor |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01262654A (en) * | 1988-04-14 | 1989-10-19 | Toshiba Corp | Semiconductor device |
| CN105378923B (en) * | 2013-07-11 | 2019-09-27 | 三菱电机株式会社 | The manufacturing method and PIN diode of semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5243382A (en) * | 1975-10-02 | 1977-04-05 | Matsushita Electronics Corp | Mos type diode |
| JPS5429587A (en) * | 1977-08-10 | 1979-03-05 | Hitachi Ltd | Semiconductor device |
| JPS54139374A (en) * | 1978-04-21 | 1979-10-29 | Toshiba Corp | Semiconductor device |
| JPS56105670A (en) * | 1980-01-28 | 1981-08-22 | Mitsubishi Electric Corp | Semiconductor device |
-
1982
- 1982-12-10 JP JP57217243A patent/JPS59106162A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5243382A (en) * | 1975-10-02 | 1977-04-05 | Matsushita Electronics Corp | Mos type diode |
| JPS5429587A (en) * | 1977-08-10 | 1979-03-05 | Hitachi Ltd | Semiconductor device |
| JPS54139374A (en) * | 1978-04-21 | 1979-10-29 | Toshiba Corp | Semiconductor device |
| JPS56105670A (en) * | 1980-01-28 | 1981-08-22 | Mitsubishi Electric Corp | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07232552A (en) * | 1994-02-23 | 1995-09-05 | Toyonaga Takemori | Two stage type vehicle sunvisor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59106162A (en) | 1984-06-19 |
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| JPS618963A (en) | Semiconductor device |