JPS6066477A - Manufacture of mesa diode - Google Patents
Manufacture of mesa diodeInfo
- Publication number
- JPS6066477A JPS6066477A JP17457283A JP17457283A JPS6066477A JP S6066477 A JPS6066477 A JP S6066477A JP 17457283 A JP17457283 A JP 17457283A JP 17457283 A JP17457283 A JP 17457283A JP S6066477 A JPS6066477 A JP S6066477A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type layer
- bevel
- etching
- out quantity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000005530 etching Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims abstract description 4
- 230000007423 decrease Effects 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 238000003754 machining Methods 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は一導電形の高抵抗層と下側の逆導電形層の間に
ＰＮ接合を有し、高抵抗層の上側には同じ導電形の低抵
抗層が設けられ、各層の横断面積が下側から上側に進む
につれて小さくなるメサ形ダイオード製造方法に関する
。[Detailed description of the invention] [Technical field to which the invention pertains] The present invention has a PN junction between a high resistance layer of one conductivity type and an opposite conductivity type layer below, and a layer of the same conductivity above the high resistance layer. The present invention relates to a method for manufacturing a mesa-shaped diode, in which a low-resistance layer of a shape is provided, and the cross-sectional area of each layer decreases from the bottom to the top.
そのようなメサ形ダイオードはいわゆる正ベベル構造を
有し、例えば１０００ Ｖ以上の高圧ダイオードに通常
採用されている構造である。一方半導体基板にけ、例え
ば単結晶棒からの切断時などに生ずる結晶表面の歪層ま
た機械加工によるメサ形成時に生ずる表面の歪層がダイ
オード完成時になおメサ形の傾斜面表面に残留すると初
期耐圧の低下あるいは運転時の耐圧劣化の原因となる。Such a mesa diode has a so-called positive bevel structure, which is a structure normally employed in high voltage diodes of 1000 V or higher, for example. On the other hand, in semiconductor substrates, if a strained layer on the surface of a crystal that occurs when cutting a single crystal bar, or a strained layer on the surface that occurs when forming a mesa by machining, remains on the sloped surface of the mesa shape when the diode is completed, the initial breakdown voltage This may cause a decrease in pressure or deterioration of pressure resistance during operation.
本発明はメサ形傾斜面表面に歪層が残留しないような耐
圧特性に対する信頼性の高いメサ形ダイオードの製造方
法を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a mesa diode with high reliability in terms of withstand voltage characteristics, such that no strained layer remains on the surface of a mesa-shaped inclined surface.
本発明は冒順に述べたようなＰ Ｎ接合をイ）する３層
構造の半導体板に加工によりベベル角を形成後、表面か
らのエツチングにより板面方向に２００〜３００μｍの
範囲を除去し、上面周辺に周縁において上面より３０〜
７０μｍに達する傾斜面を形成することにより上記の目
的を連成する。In the present invention, after forming a bevel angle by processing a three-layer structure semiconductor board that has a P-N junction as described above, etching is performed from the surface to remove an area of 200 to 300 μm in the direction of the board surface. 30~ from the top surface at the periphery
The above objectives are achieved by forming an inclined surface of up to 70 μm.
第１図において、シリコン板１は、基板本体の高携抗Ｎ
層２の下側にＰ／１ｉｉ３．上側にＮ層４を有し、両面
にアノード電極となる金属支持板５．カソード電極６が
固着されており、Ｎ層２をＰｆｉ３の間にＰＮ接合を有
する。このシリコン板１に機械加工によって、例えば２
０°のベベル角θを有するベベル形状を形成する。この
あとベベル成形のための機械加工ならびにそれ以前の加
工によって生じた歪層除去のためにエツチングを行うが
、その際の横方向エッチアウト欧７は本発明により２０
０〜３００μｍである。一方電極６の周囲のシリコン露
出面へのエツチングにより基板面に対してベベル角θよ
り小さい角度を示す傾斜面８が形成される。In FIG. 1, the silicon plate 1 has a high conductivity N of the substrate body.
P/1ii3. below layer 2. A metal support plate 5 having an N layer 4 on the upper side and serving as an anode electrode on both sides. A cathode electrode 6 is fixed, and a PN junction is formed between the N layer 2 and Pfi3. By machining this silicon plate 1, for example, 2
A bevel shape having a bevel angle θ of 0° is formed. After this, machining for bevel forming and etching are performed to remove the strained layer caused by the previous machining.
It is 0 to 300 μm. On the other hand, by etching the exposed silicon surface around the electrode 6, an inclined surface 8 is formed which exhibits an angle smaller than the bevel angle .theta. with respect to the substrate surface.
このため周縁においては本発明により３０〜７０μｍの
縦方向エッチアウト量９を示す。横方向および縦方向の
エッチアウト量が少なすぎると半導体結晶表面の歪層が
充分に取り切れず、初期耐圧不足あるいは電圧印加によ
る耐圧低下が生じる。エッチアウト量が多すぎるとシリ
コン板の面積が小さくなり、順方向の通電抵抗が増大し
て通電容量の低下につながる。また縦方向エッチアウト
ｆ＃Ｌ９が７０μｍを越えると、ダイオードに逆電圧を
印加したときは表面近くでカソード側に大きく折れ曲る
空乏層１０がＮ層４に到達しやすくなり、耐圧の低下を
引き起こす。Therefore, the peripheral edge exhibits a longitudinal etch-out amount 9 of 30 to 70 μm according to the present invention. If the amount of etch-out in the horizontal and vertical directions is too small, the strained layer on the surface of the semiconductor crystal cannot be removed sufficiently, resulting in insufficient initial breakdown voltage or a decrease in breakdown voltage due to voltage application. If the amount of etch-out is too large, the area of the silicon plate will become smaller, and the forward current carrying resistance will increase, leading to a decrease in the current carrying capacity. Furthermore, if the vertical etchout f#L9 exceeds 70 μm, the depletion layer 10, which bends largely toward the cathode near the surface, will easily reach the N layer 4 when a reverse voltage is applied to the diode, causing a decrease in breakdown voltage. cause.
以上の実施例ではＮ形シリコン板を用いているがＰ形シ
リコン板を用いても同様に実施できる。In the above embodiment, an N-type silicon plate is used, but a P-type silicon plate can also be used.
本発明はベベル形ダイオードのベベル形成後の表面エッ
チアウト量を適正に限定することにより、表面の歪層の
完全除去による耐圧の信頼性の向上のほかに空乏層の拡
がりの制限２通電容量の確保を達成し、電圧印加および
通電の双方に対してすぐれた特性を持つ、特に高耐圧用
のメサ形ダイオードを得ることができる。By appropriately limiting the amount of surface etch-out after bevel formation in a bevel diode, the present invention not only improves the reliability of withstand voltage by completely removing the strained layer on the surface, but also limits the expansion of the depletion layer2. In particular, it is possible to obtain a mesa-type diode for high voltage use, which has excellent characteristics for both voltage application and current conduction.
第１図は本発明の一実施例を示ずメサ形ダイオードの断
面図である。
１・・・シリコン板１．２・・・高抵抗Ｎ層、３・・・
Ｐ層、４・・・ＮＪｔ６．７・・・横方向エッチアウト
量、８・・・傾斜面、９・・・縦方向エッチ下パット世
。
第１ 図FIG. 1 is a cross-sectional view of a mesa diode showing an embodiment of the present invention. 1... Silicon plate 1.2... High resistance N layer, 3...
P layer, 4... NJt6.7... Lateral etch-out amount, 8... Inclined surface, 9... Vertical etch bottom pad. Figure 1
Claims (1)
接合を有し、高抵抗層の上側には同じ導電形の低抵抗層
が設けられ、各層の横断面積が下側から上側に進むにつ
れて小さくなる半導体板を製造するに際して、加工によ
りベベル角を形成後、表面からのエツチングにより半導
体板面方向に°２００〜３００μｍの範囲を除去し、上
面周辺に周縁において上面より３０〜７０μｍに達する
傾斜面を形成することを特徴とするメサ形ダイオードの
製造方法。1) - PN between the conductivity type high resistance layer and the lower opposite conductivity type layer
When manufacturing a semiconductor board, a low-resistance layer of the same conductivity type is provided above a high-resistance layer, and the cross-sectional area of each layer decreases from the bottom to the top, and a bevel angle is formed by processing. A method for manufacturing a mesa diode, characterized in that a region of 200 to 300 μm in the direction of the surface of the semiconductor substrate is removed by etching from the surface, and an inclined surface reaching 30 to 70 μm from the top surface is formed around the top surface. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17457283A JPS6066477A (en) | 1983-09-21 | 1983-09-21 | Manufacture of mesa diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17457283A JPS6066477A (en) | 1983-09-21 | 1983-09-21 | Manufacture of mesa diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6066477A true JPS6066477A (en) | 1985-04-16 |
Family
ID=15980902
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17457283A Pending JPS6066477A (en) | 1983-09-21 | 1983-09-21 | Manufacture of mesa diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6066477A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013079235A1 (en) * | 2011-11-30 | 2013-06-06 | Infineon Technologies Bipolar Gmbh & Co. Kg | Semiconductor component with optimized edge termination |
| EP2786403B1 (en) * | 2011-11-30 | 2018-11-07 | Infineon Technologies Bipolar GmbH & Co. KG | Method for doping a semiconductor body, and semiconductor component |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4826430A (en) * | 1971-08-11 | 1973-04-07 |
-
1983
- 1983-09-21 JP JP17457283A patent/JPS6066477A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4826430A (en) * | 1971-08-11 | 1973-04-07 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013079235A1 (en) * | 2011-11-30 | 2013-06-06 | Infineon Technologies Bipolar Gmbh & Co. Kg | Semiconductor component with optimized edge termination |
| US8946867B2 (en) | 2011-11-30 | 2015-02-03 | Infineon Technologies Bipolar Gmbh & Co. Kg | Semiconductor component with optimized edge termination |
| EP2786403B1 (en) * | 2011-11-30 | 2018-11-07 | Infineon Technologies Bipolar GmbH & Co. KG | Method for doping a semiconductor body, and semiconductor component |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| GB2082836A (en) | Corrugated semiconductor devices | |
| JP2002026341A (en) | Semiconductor device and its manufacturing method | |
| JPS5933272B2 (en) | semiconductor equipment | |
| US4255757A (en) | High reverse voltage semiconductor device with fast recovery time with central depression | |
| JP3072753B2 (en) | Semiconductor device and manufacturing method | |
| KR100491851B1 (en) | Semiconductor device and manufacturing method therefor | |
| JPS6066477A (en) | Manufacture of mesa diode | |
| JPH05259436A (en) | Schottky barrier rectifying semiconductor device | |
| CN108550652A (en) | The preparation method of avalanche photodide | |
| JPH0629557A (en) | Manufacture of semiconductor device | |
| JP3581027B2 (en) | Schottky barrier semiconductor device | |
| JPS6364060B2 (en) | ||
| JPS584815B2 (en) | Manufacturing method of semiconductor device | |
| JPS6245710B2 (en) | ||
| US4058824A (en) | Semiconductor diode | |
| KR20240143061A (en) | SiC Schottky Barrier Diode And Fabricating Method Thereof | |
| JP2004022743A (en) | Semiconductor device having schottky barrier | |
| JPS6047470A (en) | Semiconductor device | |
| JPH0429223B2 (en) | ||
| JPS61144871A (en) | Beveled structure of semiconductor element | |
| JP2024057596A (en) | Power diode element and manufacturing method thereof | |
| JPS5992575A (en) | Schottky barrier diode in semiconductor integrated circuit device | |
| JPH05275719A (en) | Semiconductor element and its manufacture | |
| JPH0448024Y2 (en) | ||
| JPS621273A (en) | Reverse-conducting gto thyristor |