JPS61144871A - Beveled structure of semiconductor element - Google Patents
Beveled structure of semiconductor elementInfo
- Publication number
- JPS61144871A JPS61144871A JP26774184A JP26774184A JPS61144871A JP S61144871 A JPS61144871 A JP S61144871A JP 26774184 A JP26774184 A JP 26774184A JP 26774184 A JP26774184 A JP 26774184A JP S61144871 A JPS61144871 A JP S61144871A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- junction
- bevel structure
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 230000002093 peripheral effect Effects 0.000 claims abstract description 9
- 238000009792 diffusion process Methods 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims abstract description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000003486 chemical etching Methods 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 5
- 238000005488 sandblasting Methods 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 7
- 230000006698 induction Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
- H01L29/7392—Gated diode structures with PN junction gate, e.g. field controlled thyristors (FCTh), static induction thyristors (SITh)
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）〈産業上の利用分野〉
本発明は半導体素子のベベル構造に係り、特にｐｎ接合
の低抵抗半導体層の厚さが小さい、つまり浅いｐｎ接合
のベベル構造を有する例えば埋込みゲート形半導体素子
に関する。Detailed Description of the Invention (a) <Industrial Application Field> The present invention relates to a bevel structure of a semiconductor element, and particularly relates to a bevel structure of a pn junction in which the low resistance semiconductor layer of the pn junction has a small thickness, that is, a shallow pn junction bevel structure. For example, the present invention relates to a buried gate type semiconductor device having a buried gate type semiconductor device.
（ロ）〈従来技術〉
従来、例えば埋込みゲート形半導体素子としての静電誘
導サイリスタ（以下８Ｉサイリスタと呼称する）や静電
誘導トランジスタなどの外周部分のｐｎ接合表面を角度
整形してベベル構造にし、ｐｎ接合の表面耐圧を向上し
安定化することは一般によく知られている。(b) <Prior art> Conventionally, for example, a static induction thyristor (hereinafter referred to as 8I thyristor) or a static induction transistor as a buried gate type semiconductor device, the angle of the pn junction surface on the outer periphery is shaped to create a bevel structure. It is generally well known that the surface breakdown voltage of a pn junction is improved and stabilized.
このベベル構造はサイリスタや整流ダイオードなどの電
力用半導体素子に活用され、半導体の主表面から接合ま
での厚さ、すなわち低抵抗半導体層の厚さは通常５０Ｊ
ｍ程度以上あり、比較的深い接合で形成されている。This bevel structure is used in power semiconductor devices such as thyristors and rectifier diodes, and the thickness from the main surface of the semiconductor to the junction, that is, the thickness of the low-resistance semiconductor layer, is usually 50 J.
m or more, and is formed by a relatively deep bond.
ｅ啼＜発明が解決しようとする問題点〉かくして、ベベ
ル構造を浅い接合を有する半導体素子に適用する場合に
は次のような問題点かありた０すなわち、
■ 半導体の外周部分の欠けなどの損傷による耐圧の低
下。<Problems to be solved by the invention> Thus, when applying a bevel structure to a semiconductor element having a shallow junction, there are the following problems: ■ Chips on the outer periphery of the semiconductor, etc. Decrease in pressure resistance due to damage.
■ 低抵抗半導体層側への空乏層拡がりの減少による最
大電界強度の増大による高耐圧化が離しい。■ The reduction in the spread of the depletion layer toward the low-resistance semiconductor layer increases the maximum electric field strength, making it difficult to achieve high breakdown voltage.
■ 主として負ベベル構造ではベベル整形面を化学エツ
チング仕上したのちのベベル部分の低抵抗半導体層の厚
さ不足による耐圧の低下。■ Mainly in negative bevel structures, the breakdown voltage decreases due to insufficient thickness of the low-resistance semiconductor layer in the bevel area after finishing the beveled surface by chemical etching.
などがありた。There were such things.
本発明は前述０〜０項の問題点を解決し、半導体素子の
耐圧向上と安定化を目的とする半導体素子のベベル構造
を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a bevel structure for a semiconductor device, which solves the above-mentioned problems in items 0 to 0 and aims to improve and stabilize the withstand voltage of the semiconductor device.
に）〈問題点を解決するための手段〉
その手段は、ｐｎ接合でベベル構造を形成せしめる外周
部分の低抵抗半導体層の厚さを、該低抵抗半導体層の中
央部分の厚さより大きくすると共に、最大不純物濃度を
中央部分の濃度より低くする。(ii) <Means for solving the problem> The means is to make the thickness of the low resistance semiconductor layer at the outer peripheral part where the bevel structure is formed by the pn junction larger than the thickness at the center part of the low resistance semiconductor layer, and , the maximum impurity concentration is lower than the concentration in the central part.
また、正ベベル構造あるいは負ベベル構造であって、低
抵抗半導体層の少なくとも外周部分をボロン拡散で形成
する。Further, it has a positive bevel structure or a negative bevel structure, and at least the outer peripheral portion of the low resistance semiconductor layer is formed by boron diffusion.
次に、これらの作用について以下に説明する。Next, these effects will be explained below.
（ホ）〈作 用〉
すなわち、厚さの大きい低抵抗半導体層があることによ
りて、半導体素子の外周部分が欠けた場合（は、電圧の
印加される接合表面まで損傷が到達しない。また、主と
して負ベベル構造の場合にベベル整形面を化学エツチン
グ仕上することによるベベル部分の低抵抗半導体層の厚
さが不足しない。一方、外周部分の厚さの大きい低抵抗
半導体層を、表面不純物濃度の低減した拡散層とするこ
とによって、接合近くの低抵抗半導体層の不純物濃度が
低下し、ひいては最大電界強度が低下することにより高
耐圧化が可能となる。この効果は負ベベル構造において
著しい。(E) <Function> In other words, if the outer peripheral part of the semiconductor element is chipped due to the presence of a thick low-resistance semiconductor layer, the damage will not reach the bonding surface where the voltage is applied. Mainly in the case of a negative bevel structure, the thickness of the low-resistance semiconductor layer at the bevel part is not insufficient by finishing the bevel-shaped surface by chemical etching. By creating a reduced diffusion layer, the impurity concentration of the low resistance semiconductor layer near the junction is reduced, which in turn reduces the maximum electric field strength, making it possible to achieve a high breakdown voltage.This effect is remarkable in the negative bevel structure.
かような半導体素子を図面に基づいて詳細に説明する。Such a semiconductor device will be explained in detail based on the drawings.
（へ）〈実施例〉
第１図は本発明のＳＩサイリスタへの実施例を示す断面
図で、ｌはＰ形ガード領域、２はｎ形高抵抗領域、３は
ｐ形エミッタ領域、４はｐ形ゲート領域、５および７は
ｎ影領域、６はｎ形エミッタ領域であり、これら２〜７
はシリコン半導体である。ｐ形エミッタ領域３にはアノ
ード電極８が、ｐ形ゲート領域４にはゲート電極１０が
、またｎ形エミッタ領域６にはカソード電極９が接続さ
れてｔす１ｐ形ガード領域１とｎ形高抵抗領域２の間の
ｐｎ接合１１と、ｐ形エミッタ領域３とｎ形高抵抗領域
２の間のｐｎ接合１３に、それぞれ正ベベル構造１２お
゛よび１４が形成されている。(F) <Embodiment> Fig. 1 is a cross-sectional view showing an embodiment of the present invention in an SI thyristor, where l is a P-type guard region, 2 is an n-type high resistance region, 3 is a p-type emitter region, and 4 is a p-type gate region, 5 and 7 are n-shade regions, 6 is n-type emitter region, and these 2 to 7 are
is a silicon semiconductor. An anode electrode 8 is connected to the p-type emitter region 3, a gate electrode 10 is connected to the p-type gate region 4, and a cathode electrode 9 is connected to the n-type emitter region 6. Positive bevel structures 12 and 14 are formed at the pn junction 11 between the resistance region 2 and the pn junction 13 between the p-type emitter region 3 and the n-type high resistance region 2, respectively.
第３図〜第５図はｙ４１図に示した実施例の８Ｉサイリ
スタを製造する方法を説明するための断面図である。第
３図に示すとと＜、ｎ形高抵抗半導体基板の両面に１例
えばボロンを拡散してｐ形エミッタ領域３とｐ形ガード
領域ｌを形成せしめた後、第４図に示すごとくｐ形ゲー
ト領域を選択的に拡散法で形成し、続いて第５図に示す
ごとくｐ形ゲート領域４側面上にエピタキシャル成長法
でｎ影領域５．７を形成し、更にこのｎ影領域５に選択
的にｎ形エミッタ領域６を形成せしめる。3 to 5 are cross-sectional views for explaining a method of manufacturing the 8I thyristor of the embodiment shown in FIG. y41. As shown in FIG. 3, after forming a p-type emitter region 3 and a p-type guard region l by diffusing 1, for example, boron, on both sides of an n-type high-resistance semiconductor substrate, as shown in FIG. A gate region is selectively formed by a diffusion method, and then an n-shade region 5.7 is formed by an epitaxial growth method on the side surface of the p-type gate region 4 as shown in FIG. An n-type emitter region 6 is formed.
しかる後、ｎ形エミッタ領域のうちｐ形ゲート領域４へ
のゲート電極１０の接続部分を化学エツチング法で掘り
込む。その後、ｐ形エミッタ領域３０表面にアノード電
極８としてタングステンまたはモリブデン板を合金接着
し、次にゲート電極ｌＯとカソード電極９としてアルミ
ニウムを、露出したゲート領域４の表面およびｎ形エミ
ッタ領域６の表面にそれぞれ蒸着法で形成する。Thereafter, a portion of the n-type emitter region where the gate electrode 10 is connected to the p-type gate region 4 is etched by chemical etching. Thereafter, a tungsten or molybdenum plate is alloy-bonded as an anode electrode 8 on the surface of the p-type emitter region 30, and then aluminum is bonded to the surface of the exposed gate region 4 and the surface of the n-type emitter region 6 as a gate electrode lO and a cathode electrode 9. Each layer is formed using a vapor deposition method.
次に、半導体の外周部をサンドブラスト法で加工して、
第１図に示したようにｐｎ接合１１および１３に、それ
ぞれ正ベベル構造１２および１４を作成した後、化学エ
ツチング仕上げする。ｐ形ゲート領域４の厚さは主とし
て順方向オフ電圧に、またｎ影領域７のエピタキシャル
成長層の厚さは主としてゲートルカソード間の耐圧に応
じて設定するとよいが、これらは各々ｌＯ〜３０μｍと
される場合が多い０
また、ｐ形ガード領域１の厚さは、ｐ形ゲート領域４の
厚さよりも大きく、例えば３０〜１００μｍとする。Next, the outer periphery of the semiconductor is processed by sandblasting,
As shown in FIG. 1, positive bevel structures 12 and 14 are formed on pn junctions 11 and 13, respectively, and then finished by chemical etching. The thickness of the p-type gate region 4 is preferably set mainly according to the forward off-voltage, and the thickness of the epitaxial growth layer of the n-shade region 7 is preferably set mainly according to the withstand voltage between the gate cathode, and each of these is set to 10 to 30 μm. In addition, the thickness of the p-type guard region 1 is larger than the thickness of the p-type gate region 4, and is, for example, 30 to 100 μm.
本発明にかかる半導体素子のベベル構造は、エピタキシ
ャル成長層であるｎ影領域７を素子外周部に残すことに
よって、第１図に示した角部１５での欠けや形状の乱れ
が生じても、ｐｎ接合１１まで到達し離くなり、ｐｎ接
合１１の外周表面での高耐圧化の実現に効果がある。The bevel structure of the semiconductor device according to the present invention allows the pn shadow region 7, which is an epitaxial growth layer, to remain on the outer periphery of the device, so that even if the corner portion 15 shown in FIG. 1 is chipped or the shape is disturbed, the pn It reaches the junction 11 and separates, which is effective in realizing a high breakdown voltage on the outer peripheral surface of the pn junction 11.
第２図は本発明の８Ｉサイリスタへの他の実施例を示す
断面図で、第１図と同一の符号は同一部分を示す。ｐｎ
接合１１は負ベベル構造１６に、ｐｎ接合１３は正ベベ
ル構造１７に形成されている。FIG. 2 is a sectional view showing another embodiment of the 8I thyristor of the present invention, and the same reference numerals as in FIG. 1 indicate the same parts. pn
The junction 11 is formed in a negative bevel structure 16 and the pn junction 13 is formed in a positive bevel structure 17.
これの製造方法は、第３図に示される構造を経て第５図
に示される形状に至るまでは先に第１図の実施例におい
て説明したと同様にして加工される。しかる後、ｊｇ２
図に破線１８に示される形状に研磨法で整形した後、化
学エツチング仕上げして負ベベル構造１６と正ベベル構
造１７が形成される。The manufacturing method for this is the same as that previously explained in the embodiment of FIG. 1, from the structure shown in FIG. 3 to the shape shown in FIG. 5. After that, jg2
After shaping by polishing into the shape shown by the broken line 18 in the figure, a negative bevel structure 16 and a positive bevel structure 17 are formed by chemical etching.
本実施例では、エピタキシャル成長層７が素子外周部分
に残されることによって負ベベル構造１６の厚さが、ゲ
ート領域４の厚さ程度に維持され得ることから、接合１
１の表面での高耐圧実現に効果がある。一方ｐ形ガード
領域１はｐ形ゲート領域４に比較して表面濃度を低く、
かつ厚さを大きくすることによりて、負ベベル構造の耐
圧は向上することから、高耐圧化に有効となる。In this embodiment, the thickness of the negative bevel structure 16 can be maintained at about the thickness of the gate region 4 by leaving the epitaxial growth layer 7 on the outer peripheral portion of the device.
This is effective in achieving high voltage resistance on the surface of 1. On the other hand, the p-type guard region 1 has a lower surface concentration than the p-type gate region 4,
In addition, by increasing the thickness, the withstand voltage of the negative bevel structure is improved, which is effective for increasing the withstand voltage.
次に、従来のベベル構造と本発明によるベベル構造との
順方向オフ電圧の実験結果は表にて示される数値となり
た。Next, the experimental results of the forward off-voltage of the conventional bevel structure and the bevel structure according to the present invention are shown in the table.
第１図ないし第２図において、ｐ形エミッタ領域２をｎ
形低抵抗領域とするだけで、静電誘導形トランジスタに
なることは明らかである。In FIGS. 1 and 2, the p-type emitter region 2 is
It is clear that a static induction type transistor can be obtained simply by setting the transistor to a low resistance region.
（ト）〈発明の効果〉
上記のよう国ベベル構造を有する半導体素子の耐圧の安
定に効果があり、中でも埋め込みゲート形半導体素子の
高耐圧化に効果的である。(g) <Effects of the Invention> As described above, the present invention is effective in stabilizing the breakdown voltage of a semiconductor element having a bevel structure, and is particularly effective in increasing the breakdown voltage of a buried gate type semiconductor element.
第１図は本発明の静電誘導サイリスタへの実施例を示す
断面図、第３図〜第５図は第１図に示した実施例の静電
誘導サイリスタを製造する方法を説明するための断面図
であり、第２図は本発明の静電誘導サイリスタへの他の
実施例を示す断面図である。
ｌ・・・・・・ｐ形ガード領域、２・・・・・・ｎ形高
抵抗領域、３・・・・・・ｐ形エミッタ領域、４・・・
・・・ｐ形ゲート領域、５．７・・・・・・ｎ影領域、
６・・・・・・ｎ形エミッタ領域、８・・・・・・アノ
ード電極、９・・・・・・カソード電極、１０・・・・
・・ゲート電極、１１．１３・・・・・・ｐｎ接合、１
２，１４．１７・・・・・・正ベベル構造、１５・・・
・・・角部、１６・・・・・・負ベベル構造０FIG. 1 is a sectional view showing an embodiment of the electrostatic induction thyristor of the present invention, and FIGS. FIG. 2 is a sectional view showing another embodiment of the electrostatic induction thyristor of the present invention. 1...p-type guard region, 2...n-type high resistance region, 3...p-type emitter region, 4...
...p-type gate region, 5.7...n shadow region,
6... N-type emitter region, 8... Anode electrode, 9... Cathode electrode, 10...
...Gate electrode, 11.13...pn junction, 1
2,14.17... Regular bevel structure, 15...
... Corner, 16 ... Negative bevel structure 0
Claims (2)
る半導体素子において、前記ｐｎ接合でベベル構造を形
成せしめる外周部分の低抵抗半導体層の厚さを、該低抵
抗半導体層の中央部分の厚さより大きくすると共に、最
大不純物濃度を前記中央部分の濃度より低くすることを
特徴とする半導体素子のベベル構造。(1) In a semiconductor device in which the portion where the pn junction is exposed on the outer periphery has a bevel structure, the thickness of the low resistance semiconductor layer at the outer periphery where the pn junction forms the bevel structure is equal to the thickness of the low resistance semiconductor layer at the central portion of the low resistance semiconductor layer. A bevel structure of a semiconductor device, characterized in that the bevel structure is larger than the thickness and the maximum impurity concentration is lower than the concentration of the central portion.
抵抗半導体層の少なくとも外周部分をボロン拡散で形成
せしめることを特徴とする特許請求の範囲第１項記載の
半導体素子のベベル構造。(2) The bevel structure of a semiconductor device according to claim 1, which is a positive bevel structure or a negative bevel structure, and is characterized in that at least the outer peripheral portion of the low-resistance semiconductor layer is formed by boron diffusion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26774184A JPS61144871A (en) | 1984-12-19 | 1984-12-19 | Beveled structure of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26774184A JPS61144871A (en) | 1984-12-19 | 1984-12-19 | Beveled structure of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61144871A true JPS61144871A (en) | 1986-07-02 |
Family
ID=17448924
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26774184A Pending JPS61144871A (en) | 1984-12-19 | 1984-12-19 | Beveled structure of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61144871A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6466965A (en) * | 1987-08-11 | 1989-03-13 | Asea Brown Boveri | Gate turn-off thyristor |
| US5389815A (en) * | 1992-04-28 | 1995-02-14 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor diode with reduced recovery current |
| US5608244A (en) * | 1992-04-28 | 1997-03-04 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor diode with reduced recovery current |
| JP2001185727A (en) * | 1999-10-15 | 2001-07-06 | Fuji Electric Co Ltd | Semiconductor device and its manufacturing method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS48101886A (en) * | 1972-04-03 | 1973-12-21 | ||
| JPS5068663A (en) * | 1973-10-22 | 1975-06-09 | ||
| JPS5630756A (en) * | 1979-08-22 | 1981-03-27 | Nec Corp | Semiconductor device |
| JPS58128765A (en) * | 1982-01-27 | 1983-08-01 | Fuji Electric Co Ltd | High dielectric-resistance semiconductor element |
-
1984
- 1984-12-19 JP JP26774184A patent/JPS61144871A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS48101886A (en) * | 1972-04-03 | 1973-12-21 | ||
| JPS5068663A (en) * | 1973-10-22 | 1975-06-09 | ||
| JPS5630756A (en) * | 1979-08-22 | 1981-03-27 | Nec Corp | Semiconductor device |
| JPS58128765A (en) * | 1982-01-27 | 1983-08-01 | Fuji Electric Co Ltd | High dielectric-resistance semiconductor element |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6466965A (en) * | 1987-08-11 | 1989-03-13 | Asea Brown Boveri | Gate turn-off thyristor |
| US5389815A (en) * | 1992-04-28 | 1995-02-14 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor diode with reduced recovery current |
| US5608244A (en) * | 1992-04-28 | 1997-03-04 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor diode with reduced recovery current |
| JP2001185727A (en) * | 1999-10-15 | 2001-07-06 | Fuji Electric Co Ltd | Semiconductor device and its manufacturing method |
| JP4696337B2 (en) * | 1999-10-15 | 2011-06-08 | 富士電機システムズ株式会社 | Semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5028548A (en) | Method of manufacturing a planar semiconductor device having a guard ring structure | |
| JP6708257B2 (en) | Semiconductor device and manufacturing method thereof | |
| WO2018139556A1 (en) | Semiconductor device | |
| US3252003A (en) | Unipolar transistor | |
| CN107017158A (en) | Semiconductor device and its manufacture method | |
| JPH04127480A (en) | High breakdown strength low resistance semiconductor device | |
| US3994011A (en) | High withstand voltage-semiconductor device with shallow grooves between semiconductor region and field limiting rings | |
| GB2082836A (en) | Corrugated semiconductor devices | |
| JP2005136064A (en) | Semiconductor device | |
| JPS61144871A (en) | Beveled structure of semiconductor element | |
| JPS5933272B2 (en) | semiconductor equipment | |
| JP2002185016A (en) | Semiconductor device and its manufacturing method | |
| JP3297087B2 (en) | High voltage semiconductor device | |
| JP3917202B2 (en) | Manufacturing method of semiconductor devices | |
| JP2004303927A (en) | Semiconductor device | |
| JPS607178A (en) | Semiconductor device | |
| JPH0629557A (en) | Manufacture of semiconductor device | |
| JPS584815B2 (en) | Manufacturing method of semiconductor device | |
| US4586070A (en) | Thyristor with abrupt anode emitter junction | |
| JP2603083B2 (en) | High voltage semiconductor device | |
| JP2000252457A (en) | Mesa semiconductor device | |
| JPH0618280B2 (en) | Schottky barrier semiconductor device | |
| JPS61137361A (en) | Bevel structure of semiconductor element | |
| JP2022130748A (en) | Method for manufacturing semiconductor device | |
| JP2022130747A (en) | Semiconductor device |