JPS593961A - Laminated type high withstand voltage diode - Google Patents

Abstract

PURPOSE:To enable to laminate stably when mesa type chips are to be formed regardless of swelling of passivation films at the circumferential part of a pellet by a method wherein protruding parts are provided on the antiparallel face with the etched face for formation of junction as to have the area smaller than the area of the upper electrode side on the surface. CONSTITUTION:A P type diffusion region is formed in an N type silicon substrate from the face on one side according to the diffusion method, and an N<+> type diffusion region is formed from the face on another side to form a diffusion wafer having a P-N-N<+> layer. Then SiO2 films at the mesa parts and an etch down region are etched to be removed, and the exposed Si face is etched. Then, a deep mesa groove for formation of junction is formed by etching. After wax is removed, the exposed junction parts are protected with the passivation films. After the SiO2 films at the unnecessary parts are removed for formation of electrodes, the electrodes are formed, and the wafer is divided into individual chips according to dicing, laser scribing, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure and manufacturing method of individual semiconductor elements (hereinafter referred to as chips) constituting a stacked high voltage diode.

Since then, a method for manufacturing multi-layer rvl type high voltage diodes has been to use a P-N-P-
Glue as many sheets as N using kl-8i or IA 3+, etc., and make 9 to the desired chip size.
It is known that the joints exposed by etching the cut surfaces and removing the φ layer are passivated with rubber, glass, etc. If this is σ, then V(-, the surface rEIJff is 'l' of the +nt pressure of the chip each time.
o t a I, and a diode with high breakdown voltage can be obtained overall. Recently, mesa-shaped dies/! ---
Towo S r 02, Sl 02 +jj Ra-'l e
i 'J if'j, 'jj las, S io.

+Pol i5i A chip that is passivated with Nato and sealed with glass has also appeared.

Passivation is performed in the state of each chip (see FIG. 1). However, in order to form a device using this method, it is necessary to achieve the flatness of both sides of the chip due to lamination. Therefore, it is necessary to devise measures such as etching or polishing one main surface of the chip. However, these methods have poor workability and cause wafer cracking and characteristic deterioration.

The present invention aims to improve the above-mentioned problems associated with lamination and provide a structure and manufacturing method for a whylet that is easy to assemble.

In other words, when forming a mesa-shaped chip, the surface that is antiparallel to the surface etched to form a bond (hereinafter this surface will be referred to as the back surface and the surface on which the mesa is formed will be referred to as the front surface) is the upper electrode side of the front surface. The structure is such that the arrowed part is smaller than the area of the arrow.

For this purpose, portions other than the desired protrusions on the back surface are etched down. These wrinkles are sufficiently hidden that they do not cause any trouble during assembly, so it is considered that it is sufficient to remove them by a few microns to 20 microns.

The structure of the chip according to the present invention will be shown in the third part. In this structure, since there is no stacking between the protruding part and the electrode during stacking, it is possible to stably stack the pellets regardless of the mound of the passive carbon film around the pellets.
In addition, by actively leaving a padding film on the pellet around the electrode, it can be used as a stopper for pellet displacement during stacking.

Next, the manufacturing method of the present invention will be explained in detail based on Examples. For example, a diffusion wafer having P-N-N0M is made by forming a P-type diffusion region on one side and an N+ type diffusion region on the other side using a diffusion method on an N-type silicon substrate. (Fig.) Next, for example, the 810. The exposed Sl surface is etched by several microns to about 20 microns (Figure 5). Next, a deep mesa groove for forming the joint is etched. At this time, it is recommended to protect the back side with wax, etc. containing an etching-resistant liquid (Fig. 6). Next, after removing the wax, the exposed joint part should be etched with padgage resistant liquid. (Figure 7).

Protection is done whether it is a single layer or an N pattern.Next, since it is an electrode type, unnecessary parts of the SiO2 film are removed, and the electrode is shaped (Figure 8).Next, dimming laser scribing is performed. Separate into individual chips.

FIG. 3 shows a cross-sectional view of the chip. This example is a laminated film. In addition to the above implementation example 1, for example,
As shown in Figure 1, Si is first etched on the back side, and then Si is etched.
It is also possible to reapply the film and perform mesa etching on the front and surface. This is effective when you do not want to attach glass to the back side when using an electric die to attach glass using the permanent motion method. Various actual manufacturing flows can be considered, but in any case, the feature of the present invention is that the back surface is etched down to create a chip shape with a protrusion.

In this example, only the process of mesa etching an IJ N type diode from the P side has been described, but the above explanation in which a mesa groove is formed from the fiN+ side of a positive type diode in which the formation angles of the junction and mesa are reversed is explained. The same holds true for the opposite structure.

This structure is advantageous in generating a high withstand voltage, and has the advantage that the number of pellets needed to obtain the same suppression is small. However, there will be more rain that causes cracking.

In this example, using a negative type mesa-shaped N substrate with a specific resistance of 30±5Ω-tm, it was possible to obtain individual chips of 700 to 1000 Ω.
By laminating multiple layers, we were able to obtain a withstand voltage of about 93,500 to 6,000 V and fly.

The breakdown voltage can be easily controlled by changing the number of stacked chips in relation to Vr.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a conventional stacked high voltage diode, FIG. 2 is a cross-sectional view of a high voltage diode according to the present invention, FIG. 3 is a cross-sectional view of an individual chip according to the present invention, and FIGS.
Each figure is a sectional view of a wafer in the order of steps for explaining this embodiment, and FIGS. 9 to 11 show other embodiments of the steps shown in FIGS. 5 to 7. In the drawing, 1... N-type silicon 7 is placed on a plate, 2...
...P type diffusion layer, 3...N0 type diffusion layer,
4...8iQ. Membrane, 5...engine? Chipped silicone part, 6.
Mesa groove for curved/joint form, 7...wax, 8゜8'8'...pudge page carbon [,9
, 10... electrodes, 11... leads. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] In a high-voltage diode obtained by stacking mesa-type diodes, the main surface that is mesa-etched to form a junction between the individual diodes is slightly smaller than the plane of the main surface on the side where the mesa is formed. A multilayer high-voltage diode characterized in that it is etched down leaving just the area, and has a protrusion at a position corresponding to an electrode on the main surface side of about tA.